src/arch/arm/insts/misc.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_ARM_INSTS_MISC_HH__
  41 #define __ARCH_ARM_INSTS_MISC_HH__
  42
  43 #include "arch/arm/insts/pred_inst.hh"
  44
  45 class MrsOp : public PredOp
  46 {
  47   protected:
  48     IntRegIndex dest;
  49
  50     MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  51             IntRegIndex _dest) :
  52         PredOp(mnem, _machInst, __opClass), dest(_dest)
  53     {}
  54
  55     std::string generateDisassembly(
  56             Addr pc, const SymbolTable *symtab) const override;
  57 };
  58
  59 class MsrBase : public PredOp
  60 {
  61   protected:
  62     uint8_t byteMask;
  63
  64     MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  65             uint8_t _byteMask) :
  66         PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
  67     {}
  68
  69     void printMsrBase(std::ostream &os) const;
  70 };
  71
  72 class MsrImmOp : public MsrBase
  73 {
  74   protected:
  75     uint32_t imm;
  76
  77     MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  78              uint32_t _imm, uint8_t _byteMask) :
  79         MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
  80     {}
  81
  82     std::string generateDisassembly(
  83             Addr pc, const SymbolTable *symtab) const override;
  84 };
  85
  86 class MsrRegOp : public MsrBase
  87 {
  88   protected:
  89     IntRegIndex op1;
  90
  91     MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
  92              IntRegIndex _op1, uint8_t _byteMask) :
  93         MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
  94     {}
  95
  96     std::string generateDisassembly(
  97             Addr pc, const SymbolTable *symtab) const override;
  98 };
  99
 100 class MrrcOp : public PredOp
 101 {
 102   protected:
 103     MiscRegIndex op1;
 104     IntRegIndex dest;
 105     IntRegIndex dest2;
 106     uint32_t    imm;
 107
 108     MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 109            MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
 110            uint32_t _imm) :
 111         PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
 112         dest2(_dest2), imm(_imm)
 113     {}
 114
 115     std::string generateDisassembly(
 116             Addr pc, const SymbolTable *symtab) const override;
 117 };
 118
 119 class McrrOp : public PredOp
 120 {
 121   protected:
 122     IntRegIndex op1;
 123     IntRegIndex op2;
 124     MiscRegIndex dest;
 125     uint32_t    imm;
 126
 127     McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 128            IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest,
 129            uint32_t _imm) :
 130         PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
 131         dest(_dest), imm(_imm)
 132     {}
 133
 134     std::string generateDisassembly(
 135             Addr pc, const SymbolTable *symtab) const override;
 136 };
 137
 138 class ImmOp : public PredOp
 139 {
 140   protected:
 141     uint64_t imm;
 142
 143     ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 144              uint64_t _imm) :
 145         PredOp(mnem, _machInst, __opClass), imm(_imm)
 146     {}
 147
 148     std::string generateDisassembly(
 149             Addr pc, const SymbolTable *symtab) const override;
 150 };
 151
 152 class RegImmOp : public PredOp
 153 {
 154   protected:
 155     IntRegIndex dest;
 156     uint64_t imm;
 157
 158     RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 159              IntRegIndex _dest, uint64_t _imm) :
 160         PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
 161     {}
 162
 163     std::string generateDisassembly(
 164             Addr pc, const SymbolTable *symtab) const override;
 165 };
 166
 167 class RegRegOp : public PredOp
 168 {
 169   protected:
 170     IntRegIndex dest;
 171     IntRegIndex op1;
 172
 173     RegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 174              IntRegIndex _dest, IntRegIndex _op1) :
 175         PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
 176     {}
 177
 178     std::string generateDisassembly(
 179             Addr pc, const SymbolTable *symtab) const override;
 180 };
 181
 182 class RegOp : public PredOp
 183 {
 184   protected:
 185     IntRegIndex dest;
 186
 187     RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 188              IntRegIndex _dest) :
 189         PredOp(mnem, _machInst, __opClass), dest(_dest)
 190     {}
 191
 192     std::string generateDisassembly(
 193             Addr pc, const SymbolTable *symtab) const override;
 194 };
 195
 196 class RegImmRegOp : public PredOp
 197 {
 198   protected:
 199     IntRegIndex dest;
 200     uint64_t imm;
 201     IntRegIndex op1;
 202
 203     RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 204                 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) :
 205         PredOp(mnem, _machInst, __opClass),
 206         dest(_dest), imm(_imm), op1(_op1)
 207     {}
 208
 209     std::string generateDisassembly(
 210             Addr pc, const SymbolTable *symtab) const override;
 211 };
 212
 213 class RegRegRegImmOp : public PredOp
 214 {
 215   protected:
 216     IntRegIndex dest;
 217     IntRegIndex op1;
 218     IntRegIndex op2;
 219     uint64_t imm;
 220
 221     RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 222                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 223                    uint64_t _imm) :
 224         PredOp(mnem, _machInst, __opClass),
 225         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
 226     {}
 227
 228     std::string generateDisassembly(
 229             Addr pc, const SymbolTable *symtab) const override;
 230 };
 231
 232 class RegRegRegRegOp : public PredOp
 233 {
 234   protected:
 235     IntRegIndex dest;
 236     IntRegIndex op1;
 237     IntRegIndex op2;
 238     IntRegIndex op3;
 239
 240     RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 241                    IntRegIndex _dest, IntRegIndex _op1,
 242                    IntRegIndex _op2, IntRegIndex _op3) :
 243         PredOp(mnem, _machInst, __opClass),
 244         dest(_dest), op1(_op1), op2(_op2), op3(_op3)
 245     {}
 246
 247     std::string generateDisassembly(
 248             Addr pc, const SymbolTable *symtab) const override;
 249 };
 250
 251 class RegRegRegOp : public PredOp
 252 {
 253   protected:
 254     IntRegIndex dest;
 255     IntRegIndex op1;
 256     IntRegIndex op2;
 257
 258     RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 259                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
 260         PredOp(mnem, _machInst, __opClass),
 261         dest(_dest), op1(_op1), op2(_op2)
 262     {}
 263
 264     std::string generateDisassembly(
 265             Addr pc, const SymbolTable *symtab) const override;
 266 };
 267
 268 class RegRegImmOp : public PredOp
 269 {
 270   protected:
 271     IntRegIndex dest;
 272     IntRegIndex op1;
 273     uint64_t imm;
 274
 275     RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 276                 IntRegIndex _dest, IntRegIndex _op1,
 277                 uint64_t _imm) :
 278         PredOp(mnem, _machInst, __opClass),
 279         dest(_dest), op1(_op1), imm(_imm)
 280     {}
 281
 282     std::string generateDisassembly(
 283             Addr pc, const SymbolTable *symtab) const override;
 284 };
 285
 286 class MiscRegRegImmOp : public PredOp
 287 {
 288   protected:
 289     MiscRegIndex dest;
 290     IntRegIndex op1;
 291     uint64_t imm;
 292
 293     MiscRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 294                     MiscRegIndex _dest, IntRegIndex _op1,
 295                     uint64_t _imm) :
 296         PredOp(mnem, _machInst, __opClass),
 297         dest(_dest), op1(_op1), imm(_imm)
 298     {}
 299
 300     std::string generateDisassembly(
 301             Addr pc, const SymbolTable *symtab) const override;
 302 };
 303
 304 class RegMiscRegImmOp : public PredOp
 305 {
 306   protected:
 307     IntRegIndex dest;
 308     MiscRegIndex op1;
 309     uint64_t imm;
 310
 311     RegMiscRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 312                     IntRegIndex _dest, MiscRegIndex _op1,
 313                     uint64_t _imm) :
 314         PredOp(mnem, _machInst, __opClass),
 315         dest(_dest), op1(_op1), imm(_imm)
 316     {}
 317
 318     std::string generateDisassembly(
 319             Addr pc, const SymbolTable *symtab) const override;
 320 };
 321
 322 class RegImmImmOp : public PredOp
 323 {
 324   protected:
 325     IntRegIndex dest;
 326     uint64_t imm1;
 327     uint64_t imm2;
 328
 329     RegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 330                 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) :
 331         PredOp(mnem, _machInst, __opClass),
 332         dest(_dest), imm1(_imm1), imm2(_imm2)
 333     {}
 334
 335     std::string generateDisassembly(
 336             Addr pc, const SymbolTable *symtab) const override;
 337 };
 338
 339 class RegRegImmImmOp : public PredOp
 340 {
 341   protected:
 342     IntRegIndex dest;
 343     IntRegIndex op1;
 344     uint64_t imm1;
 345     uint64_t imm2;
 346
 347     RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 348                    IntRegIndex _dest, IntRegIndex _op1,
 349                    uint64_t _imm1, uint64_t _imm2) :
 350         PredOp(mnem, _machInst, __opClass),
 351         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
 352     {}
 353
 354     std::string generateDisassembly(
 355             Addr pc, const SymbolTable *symtab) const override;
 356 };
 357
 358 class RegImmRegShiftOp : public PredOp
 359 {
 360   protected:
 361     IntRegIndex dest;
 362     uint64_t imm;
 363     IntRegIndex op1;
 364     int32_t shiftAmt;
 365     ArmShiftType shiftType;
 366
 367     RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 368                      IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
 369                      int32_t _shiftAmt, ArmShiftType _shiftType) :
 370         PredOp(mnem, _machInst, __opClass),
 371         dest(_dest), imm(_imm), op1(_op1),
 372         shiftAmt(_shiftAmt), shiftType(_shiftType)
 373     {}
 374
 375     std::string generateDisassembly(
 376             Addr pc, const SymbolTable *symtab) const override;
 377 };
 378
 379 class UnknownOp : public PredOp
 380 {
 381   protected:
 382
 383     UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
 384         PredOp(mnem, _machInst, __opClass)
 385     {}
 386
 387     std::string generateDisassembly(
 388             Addr pc, const SymbolTable *symtab) const override;
 389 };
 390
 391 /**
 392  * Certain mrc/mcr instructions act as nops or flush the pipe based on what
 393  * register the instruction is trying to access. This inst/class exists so that
 394  * we can still check for hyp traps, as the normal nop instruction
 395  * does not.
 396  */
 397 class McrMrcMiscInst : public ArmStaticInst
 398 {
 399   protected:
 400     uint64_t iss;
 401     MiscRegIndex miscReg;
 402
 403   public:
 404     McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
 405                    uint64_t _iss, MiscRegIndex _miscReg);
 406
 407     Fault execute(ExecContext *xc,
 408                   Trace::InstRecord *traceData) const override;
 409
 410     std::string generateDisassembly(
 411             Addr pc, const SymbolTable *symtab) const override;
 412
 413 };
 414
 415 /**
 416  * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc
 417  * behaviour is trappable even for unimplemented registers.
 418  */
 419 class McrMrcImplDefined : public McrMrcMiscInst
 420 {
 421   public:
 422     McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
 423                       uint64_t _iss, MiscRegIndex _miscReg);
 424
 425     Fault execute(ExecContext *xc,
 426                   Trace::InstRecord *traceData) const override;
 427
 428     std::string generateDisassembly(
 429             Addr pc, const SymbolTable *symtab) const override;
 430
 431 };
 432
 433 #endif