src/arch/arm/insts/misc64.cc

   1 /*
   2  * Copyright (c) 2011-2013,2017-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/insts/misc64.hh"
  39 #include "arch/arm/isa.hh"
  40
  41 using namespace ArmISA;
  42
  43 std::string
  44 ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  45 {
  46     std::stringstream ss;
  47     printMnemonic(ss, "", false);
  48     ccprintf(ss, "#0x%x", imm);
  49     return ss.str();
  50 }
  51
  52 std::string
  53 RegRegImmImmOp64::generateDisassembly(
  54         Addr pc, const Loader::SymbolTable *symtab) const
  55 {
  56     std::stringstream ss;
  57     printMnemonic(ss, "", false);
  58     printIntReg(ss, dest);
  59     ss << ", ";
  60     printIntReg(ss, op1);
  61     ccprintf(ss, ", #%d, #%d", imm1, imm2);
  62     return ss.str();
  63 }
  64
  65 std::string
  66 RegRegRegImmOp64::generateDisassembly(
  67     Addr pc, const Loader::SymbolTable *symtab) const
  68 {
  69     std::stringstream ss;
  70     printMnemonic(ss, "", false);
  71     printIntReg(ss, dest);
  72     ss << ", ";
  73     printIntReg(ss, op1);
  74     ss << ", ";
  75     printIntReg(ss, op2);
  76     ccprintf(ss, ", #%d", imm);
  77     return ss.str();
  78 }
  79
  80 std::string
  81 UnknownOp64::generateDisassembly(
  82         Addr pc, const Loader::SymbolTable *symtab) const
  83 {
  84     return csprintf("%-10s (inst %#08x)", "unknown", encoding());
  85 }
  86
  87 Fault
  88 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
  89                   ExceptionLevel el, uint32_t immediate) const
  90 {
  91     ExceptionClass ec = EC_TRAPPED_MSR_MRS_64;
  92
  93     // Check for traps to supervisor (FP/SIMD regs)
  94     if (el <= EL1 && checkEL1Trap(tc, misc_reg, el, ec, immediate)) {
  95         return std::make_shared<SupervisorTrap>(machInst, immediate, ec);
  96     }
  97
  98     // Check for traps to hypervisor
  99     if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
 100         checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
 101         return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
 102     }
 103
 104     // Check for traps to secure monitor
 105     if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
 106         checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
 107         return std::make_shared<SecureMonitorTrap>(machInst, immediate, ec);
 108     }
 109
 110     return NoFault;
 111 }
 112
 113 bool
 114 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 115                           ExceptionLevel el, ExceptionClass &ec,
 116                           uint32_t &immediate) const
 117 {
 118     const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
 119     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 120     const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
 121     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 122
 123     bool trap_to_sup = false;
 124     switch (misc_reg) {
 125       case MISCREG_DAIF:
 126         trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
 127         trap_to_sup = trap_to_sup ||
 128             (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
 129         break;
 130       case MISCREG_DC_ZVA_Xt:
 131         // In syscall-emulation mode, this test is skipped and DCZVA is always
 132         // allowed at EL0
 133         trap_to_sup =  el == EL0 && !sctlr.dze && FullSystem;
 134         break;
 135       case MISCREG_DC_CIVAC_Xt:
 136       case MISCREG_DC_CVAC_Xt:
 137         trap_to_sup = el == EL0 && !sctlr.uci;
 138         break;
 139       case MISCREG_FPCR:
 140       case MISCREG_FPSR:
 141       case MISCREG_FPEXC32_EL2:
 142         if ((el == EL0 && cpacr.fpen != 0x3) ||
 143             (el == EL1 && !(cpacr.fpen & 0x1))) {
 144             trap_to_sup = true;
 145             ec = EC_TRAPPED_SIMD_FP;
 146             immediate = 0x1E00000;
 147         }
 148         break;
 149       case MISCREG_DC_CVAU_Xt:
 150         trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
 151             el == EL0;
 152         break;
 153       case MISCREG_CTR_EL0:
 154         trap_to_sup = el == EL0 && !sctlr.uct &&
 155             (!hcr.tge || (!scr.ns && !scr.eel2));
 156         break;
 157        case MISCREG_MDCCSR_EL0:
 158          {
 159              DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
 160              trap_to_sup = el == EL0 && mdscr.tdcc &&
 161                      (hcr.tge == 0x0 || ( scr.ns == 0x0));
 162          }
 163          break;
 164      case MISCREG_ZCR_EL1:
 165         trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
 166         break;
 167       // Generic Timer
 168       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 169         trap_to_sup = el == EL0 &&
 170                       isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
 171         break;
 172       default:
 173         break;
 174     }
 175     return trap_to_sup;
 176 }
 177
 178 bool
 179 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 180                           ExceptionLevel el, ExceptionClass &ec,
 181                           uint32_t &immediate) const
 182 {
 183     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
 184     const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
 185     const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
 186     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 187     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 188     const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
 189
 190     bool trap_to_hyp = false;
 191
 192     switch (misc_reg) {
 193       case MISCREG_IMPDEF_UNIMPL:
 194         trap_to_hyp = EL2Enabled(tc) && hcr.tidcp && el == EL1;
 195         break;
 196       // GICv3 regs
 197       case MISCREG_ICC_SGI0R_EL1:
 198         {
 199             auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
 200             if (isa->haveGICv3CpuIfc())
 201                 trap_to_hyp = EL2Enabled(tc) && hcr.fmo && el == EL1;
 202         }
 203         break;
 204       case MISCREG_ICC_SGI1R_EL1:
 205       case MISCREG_ICC_ASGI1R_EL1:
 206         {
 207             auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
 208             if (isa->haveGICv3CpuIfc())
 209                 trap_to_hyp = EL2Enabled(tc) && hcr.imo && el == EL1;
 210         }
 211         break;
 212       case MISCREG_FPCR:
 213       case MISCREG_FPSR:
 214       case MISCREG_FPEXC32_EL2:
 215         {
 216             bool from_el2 = (el == EL2) && (scr.ns || scr.eel2) &&
 217                              ELIs64(tc,EL2) &&
 218                              ((!hcr.e2h && cptr.tfp) ||
 219                               (hcr.e2h && (cptr.fpen == 0x0 ||
 220                                            cptr.fpen == 0xa)));
 221             bool from_el1 = (el == EL1) && hcr.nv &&
 222                             (!hcr.e2h || (hcr.e2h && !hcr.tge));
 223             trap_to_hyp = from_el2 || from_el1;
 224             ec = EC_TRAPPED_SIMD_FP;
 225             immediate = 0x1E00000;
 226         }
 227         break;
 228       case MISCREG_CPACR_EL1:
 229             trap_to_hyp =  EL2Enabled(tc) && (el == EL1) && cptr.tcpac;
 230         break;
 231       case MISCREG_SCTLR_EL1:
 232       case MISCREG_TTBR0_EL1:
 233       case MISCREG_TTBR1_EL1:
 234       case MISCREG_TCR_EL1:
 235       case MISCREG_ESR_EL1:
 236       case MISCREG_FAR_EL1:
 237       case MISCREG_AFSR0_EL1:
 238       case MISCREG_AFSR1_EL1:
 239       case MISCREG_MAIR_EL1:
 240       case MISCREG_AMAIR_EL1:
 241       case MISCREG_CONTEXTIDR_EL1:
 242         {
 243             bool tvm = miscRead? hcr.trvm: hcr.tvm;
 244             trap_to_hyp = EL2Enabled(tc) && (el == EL1) && tvm;
 245         }
 246         break;
 247       case MISCREG_CPACR_EL12:
 248       case MISCREG_SCTLR_EL12:
 249       case MISCREG_TTBR0_EL12:
 250       case MISCREG_TTBR1_EL12:
 251       case MISCREG_TCR_EL12:
 252       case MISCREG_ESR_EL12:
 253       case MISCREG_FAR_EL12:
 254       case MISCREG_AFSR0_EL12:
 255       case MISCREG_AFSR1_EL12:
 256       case MISCREG_MAIR_EL12:
 257       case MISCREG_AMAIR_EL12:
 258       case MISCREG_CONTEXTIDR_EL12:
 259       case MISCREG_SPSR_EL12:
 260       case MISCREG_ELR_EL12:
 261       case MISCREG_VBAR_EL12:
 262         trap_to_hyp = EL2Enabled(tc) && (el == EL1) &&
 263            (hcr.nv && (hcr.nv1 || !hcr.nv2));
 264         break;
 265       case MISCREG_TLBI_VMALLE1:
 266       case MISCREG_TLBI_VAE1_Xt:
 267       case MISCREG_TLBI_ASIDE1_Xt:
 268       case MISCREG_TLBI_VAAE1_Xt:
 269       case MISCREG_TLBI_VALE1_Xt:
 270       case MISCREG_TLBI_VAALE1_Xt:
 271 //      case MISCREG_TLBI_RVAE1:
 272 //      case MISCREG_TLBI_RVAAE1:
 273 //      case MISCREG_TLBI_RVALE1:
 274 //      case MISCREG_TLBI_RVAALE1:
 275       case MISCREG_TLBI_VMALLE1IS:
 276       case MISCREG_TLBI_VAE1IS_Xt:
 277       case MISCREG_TLBI_ASIDE1IS_Xt:
 278       case MISCREG_TLBI_VAAE1IS_Xt:
 279       case MISCREG_TLBI_VALE1IS_Xt:
 280       case MISCREG_TLBI_VAALE1IS_Xt:
 281 //      case MISCREG_TLBI_RVAE1IS:
 282 //      case MISCREG_TLBI_RVAAE1IS:
 283 //      case MISCREG_TLBI_RVALE1IS:
 284 //      case MISCREG_TLBI_RVAALE1IS:
 285 //      case MISCREG_TLBI_VMALLE1OS:
 286 //      case MISCREG_TLBI_VAE1OS:
 287 //      case MISCREG_TLBI_ASIDE1OS:
 288 //      case MISCREG_TLBI_VAAE1OS:
 289 //      case MISCREG_TLBI_VALE1OS:
 290 //      case MISCREG_TLBI_VAALE1OS:
 291 //      case MISCREG_TLBI_RVAE1OS:
 292 //      case MISCREG_TLBI_RVAAE1OS:
 293 //      case MISCREG_TLBI_RVALE1OS:
 294 //      case MISCREG_TLBI_RVAALE1OS:
 295         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.ttlb;
 296         break;
 297       case MISCREG_IC_IVAU_Xt:
 298       case MISCREG_ICIALLU:
 299       case MISCREG_ICIALLUIS:
 300         trap_to_hyp = (el == EL1) && EL2Enabled(tc) && hcr.tpu;
 301         break;
 302       case MISCREG_DC_CVAU_Xt:
 303         {
 304             const bool el2_en = EL2Enabled(tc);
 305             if (el == EL0 && el2_en) {
 306                 const bool in_host = hcr.e2h && hcr.tge;
 307                 const bool general_trap = el2_en && !in_host && hcr.tge &&
 308                                           !sctlr.uci;
 309                 const bool tpu_trap = el2_en && !in_host && hcr.tpu;
 310                 const bool host_trap = el2_en && in_host && !sctlr2.uci;
 311                 trap_to_hyp = general_trap || tpu_trap || host_trap;
 312             }
 313             else if (el == EL1 && el2_en) {
 314                 trap_to_hyp = hcr.tpu;
 315             }
 316         }
 317         break;
 318       case MISCREG_DC_IVAC_Xt:
 319         trap_to_hyp = EL2Enabled(tc) && el == EL1 && hcr.tpc;
 320         break;
 321       case MISCREG_DC_CVAC_Xt:
 322 //      case MISCREG_DC_CVAP_Xt:
 323       case MISCREG_DC_CIVAC_Xt:
 324         {
 325             const bool el2_en = EL2Enabled(tc);
 326             if (el == EL0 && el2_en) {
 327
 328                 const bool in_host = hcr.e2h && hcr.tge;
 329                 const bool general_trap = el2_en && !in_host && hcr.tge &&
 330                                           !sctlr.uci;
 331                 const bool tpc_trap = el2_en && !in_host && hcr.tpc;
 332                 const bool host_trap = el2_en && in_host && !sctlr2.uci;
 333                 trap_to_hyp = general_trap || tpc_trap || host_trap;
 334             } else if (el == EL1 && el2_en) {
 335                 trap_to_hyp = hcr.tpc;
 336             }
 337         }
 338         break;
 339       case MISCREG_DC_ISW_Xt:
 340       case MISCREG_DC_CSW_Xt:
 341       case MISCREG_DC_CISW_Xt:
 342         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.tsw;
 343         break;
 344       case MISCREG_ACTLR_EL1:
 345         trap_to_hyp = EL2Enabled (tc) && (el == EL1) && hcr.tacr;
 346         break;
 347       case MISCREG_APDAKeyHi_EL1:
 348       case MISCREG_APDAKeyLo_EL1:
 349       case MISCREG_APDBKeyHi_EL1:
 350       case MISCREG_APDBKeyLo_EL1:
 351       case MISCREG_APGAKeyHi_EL1:
 352       case MISCREG_APGAKeyLo_EL1:
 353       case MISCREG_APIAKeyHi_EL1:
 354       case MISCREG_APIAKeyLo_EL1:
 355       case MISCREG_APIBKeyHi_EL1:
 356       case MISCREG_APIBKeyLo_EL1:
 357         trap_to_hyp = EL2Enabled(tc) && el == EL1 && !hcr.apk;
 358         break;
 359       case MISCREG_ID_PFR0_EL1:
 360       case MISCREG_ID_PFR1_EL1:
 361       //case MISCREG_ID_PFR2_EL1:
 362       case MISCREG_ID_DFR0_EL1:
 363       case MISCREG_ID_AFR0_EL1:
 364       case MISCREG_ID_MMFR0_EL1:
 365       case MISCREG_ID_MMFR1_EL1:
 366       case MISCREG_ID_MMFR2_EL1:
 367       case MISCREG_ID_MMFR3_EL1:
 368       case MISCREG_ID_MMFR4_EL1:
 369       case MISCREG_ID_ISAR0_EL1:
 370       case MISCREG_ID_ISAR1_EL1:
 371       case MISCREG_ID_ISAR2_EL1:
 372       case MISCREG_ID_ISAR3_EL1:
 373       case MISCREG_ID_ISAR4_EL1:
 374       case MISCREG_ID_ISAR5_EL1:
 375       case MISCREG_ID_ISAR6_EL1:
 376       case MISCREG_MVFR0_EL1:
 377       case MISCREG_MVFR1_EL1:
 378       case MISCREG_MVFR2_EL1:
 379       case MISCREG_ID_AA64PFR0_EL1:
 380       case MISCREG_ID_AA64PFR1_EL1:
 381       case MISCREG_ID_AA64DFR0_EL1:
 382       case MISCREG_ID_AA64DFR1_EL1:
 383       case MISCREG_ID_AA64ISAR0_EL1:
 384       case MISCREG_ID_AA64ISAR1_EL1:
 385       case MISCREG_ID_AA64MMFR0_EL1:
 386       case MISCREG_ID_AA64MMFR1_EL1:
 387       case MISCREG_ID_AA64MMFR2_EL1:
 388       case MISCREG_ID_AA64AFR0_EL1:
 389       case MISCREG_ID_AA64AFR1_EL1:
 390         trap_to_hyp =  EL2Enabled(tc) && el == EL1 && hcr.tid3;
 391         break;
 392       case MISCREG_CTR_EL0:
 393         {
 394             const bool el2_en = EL2Enabled(tc);
 395             if (el == EL0 && el2_en) {
 396                 const bool in_host = hcr.e2h && hcr.tge;
 397                 const bool general_trap = el2_en && !in_host && hcr.tge &&
 398                                           !sctlr.uct;
 399                 const bool tid_trap = el2_en && !in_host && hcr.tid2;
 400                 const bool host_trap = el2_en && in_host && !sctlr2.uct;
 401                 trap_to_hyp = general_trap || tid_trap || host_trap;
 402             } else if (el == EL1 && el2_en) {
 403                 trap_to_hyp = hcr.tid2;
 404             }
 405         }
 406         break;
 407       case MISCREG_CCSIDR_EL1:
 408 //      case MISCREG_CCSIDR2_EL1:
 409       case MISCREG_CLIDR_EL1:
 410       case MISCREG_CSSELR_EL1:
 411             trap_to_hyp =  EL2Enabled(tc) && (el == EL1) && hcr.tid2;
 412         break;
 413       case MISCREG_AIDR_EL1:
 414       case MISCREG_REVIDR_EL1:
 415         trap_to_hyp =  EL2Enabled(tc) && (el == EL1) && hcr.tid1;
 416         break;
 417        // Generic Timer
 418       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 419         trap_to_hyp = el <= EL1 &&
 420                       isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
 421         break;
 422       case MISCREG_DAIF:
 423         trap_to_hyp = EL2Enabled(tc) && el == EL0 &&
 424                      (hcr.tge && (hcr.e2h || !sctlr.uma));
 425         break;
 426       case MISCREG_SPSR_EL1:
 427       case MISCREG_ELR_EL1:
 428       case MISCREG_VBAR_EL1:
 429         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv1 && !hcr.nv2;
 430         break;
 431       case MISCREG_HCR_EL2:
 432       case MISCREG_HSTR_EL2:
 433       case MISCREG_SP_EL1:
 434       case MISCREG_TPIDR_EL2:
 435       case MISCREG_VTCR_EL2:
 436       case MISCREG_VTTBR_EL2:
 437         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv && !hcr.nv2;
 438         break;
 439 //      case MISCREG_AT_S1E1WP_Xt:
 440 //      case MISCREG_AT_S1E1RP_Xt:
 441       case MISCREG_AT_S1E1R_Xt:
 442       case MISCREG_AT_S1E1W_Xt:
 443       case MISCREG_AT_S1E0W_Xt:
 444       case MISCREG_AT_S1E0R_Xt:
 445         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.at;
 446         break;
 447       case MISCREG_ACTLR_EL2:
 448       case MISCREG_AFSR0_EL2:
 449       case MISCREG_AFSR1_EL2:
 450       case MISCREG_AMAIR_EL2:
 451       case MISCREG_CONTEXTIDR_EL2:
 452       case MISCREG_CPTR_EL2:
 453       case MISCREG_DACR32_EL2:
 454       case MISCREG_ESR_EL2:
 455       case MISCREG_FAR_EL2:
 456       case MISCREG_HACR_EL2:
 457       case MISCREG_HPFAR_EL2:
 458       case MISCREG_MAIR_EL2:
 459 //      case MISCREG_RMR_EL2:
 460       case MISCREG_SCTLR_EL2:
 461       case MISCREG_TCR_EL2:
 462       case MISCREG_TTBR0_EL2:
 463       case MISCREG_TTBR1_EL2:
 464       case MISCREG_VBAR_EL2:
 465       case MISCREG_VMPIDR_EL2:
 466       case MISCREG_VPIDR_EL2:
 467       case MISCREG_TLBI_ALLE1:
 468       case MISCREG_TLBI_ALLE1IS:
 469 //      case MISCREG_TLBI_ALLE1OS:
 470       case MISCREG_TLBI_ALLE2:
 471       case MISCREG_TLBI_ALLE2IS:
 472 //      case MISCREG_TLBI_ALLE2OS:
 473       case MISCREG_TLBI_IPAS2E1_Xt:
 474       case MISCREG_TLBI_IPAS2E1IS_Xt:
 475 //      case MISCREG_TLBI_IPAS2E1OS:
 476       case MISCREG_TLBI_IPAS2LE1_Xt:
 477       case MISCREG_TLBI_IPAS2LE1IS_Xt:
 478 //      case MISCREG_TLBI_IPAS2LE1OS:
 479 //      case MISCREG_TLBI_RIPAS2E1:
 480 //      case MISCREG_TLBI_RIPAS2E1IS:
 481 //      case MISCREG_TLBI_RIPAS2E1OS:
 482 //      case MISCREG_TLBI_RIPAS2LE1:
 483 //      case MISCREG_TLBI_RIPAS2LE1IS:
 484 //      case MISCREG_TLBI_RIPAS2LE1OS:
 485 //      case MISCREG_TLBI_RVAE2:
 486 //      case MISCREG_TLBI_RVAE2IS:
 487 //      case MISCREG_TLBI_RVAE2OS:
 488 //      case MISCREG_TLBI_RVALE2:
 489 //      case MISCREG_TLBI_RVALE2IS:
 490 //      case MISCREG_TLBI_RVALE2OS:
 491       case MISCREG_TLBI_VAE2_Xt:
 492       case MISCREG_TLBI_VAE2IS_Xt:
 493 //      case MISCREG_TLBI_VAE2OS:
 494       case MISCREG_TLBI_VALE2_Xt:
 495       case MISCREG_TLBI_VALE2IS_Xt:
 496 //      case MISCREG_TLBI_VALE2OS:
 497       case MISCREG_TLBI_VMALLS12E1:
 498       case MISCREG_TLBI_VMALLS12E1IS:
 499 //      case MISCREG_TLBI_VMALLS12E1OS:
 500       case MISCREG_AT_S1E2W_Xt:
 501       case MISCREG_AT_S1E2R_Xt:
 502       case MISCREG_AT_S12E1R_Xt:
 503       case MISCREG_AT_S12E1W_Xt:
 504       case MISCREG_AT_S12E0W_Xt:
 505       case MISCREG_AT_S12E0R_Xt:
 506       case MISCREG_SPSR_UND:
 507       case MISCREG_SPSR_IRQ:
 508       case MISCREG_SPSR_FIQ:
 509       case MISCREG_SPSR_ABT:
 510       case MISCREG_SPSR_EL2:
 511       case MISCREG_ELR_EL2:
 512       case MISCREG_IFSR32_EL2:
 513       case MISCREG_DBGVCR32_EL2:
 514       case MISCREG_MDCR_EL2:
 515         trap_to_hyp = EL2Enabled(tc) && (el == EL1) && hcr.nv;
 516         break;
 517 //      case MISCREG_VSTTBR_EL2:
 518 //      case MISCREG_VSTCR_EL2:
 519 //        trap_to_hyp = (el == EL1) && !scr.ns && scr.eel2 && ELIs64(tc,EL2)
 520 //              && !hcr.nv2 && hcr.nv && (!hcr.e2h|| (hcr.e2h && !hcr.tge));
 521 //        break;
 522
 523       //case MISCREG_LORC_EL1:
 524       //case MISCREG_LOREA_EL1:
 525       //case MISCREG_LORID_EL1:
 526       //case MISCREG_LORN_EL1:
 527       //case MISCREG_LORSA_EL1:
 528       //  trap_to_hyp = (el == EL1) && (scr.ns || scr.eel2) && ELIs64(tc,EL2)
 529       //      && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
 530       //  break;
 531
 532       case MISCREG_DC_ZVA_Xt:
 533         {
 534             const bool el2_en = EL2Enabled(tc);
 535             if (el == EL0 && el2_en) {
 536                 const bool in_host = hcr.e2h && hcr.tge;
 537                 const bool general_trap = el2_en && !in_host && hcr.tge &&
 538                                           !sctlr.dze;
 539                 const bool tdz_trap = el2_en && !in_host && hcr.tdz;
 540                 const bool host_trap = el2_en && in_host && !sctlr2.dze;
 541                 trap_to_hyp = general_trap || tdz_trap || host_trap;
 542             } else if (el == EL1 && el2_en) {
 543                 trap_to_hyp = hcr.tdz;
 544             }
 545         }
 546         break;
 547       case MISCREG_DBGBVR0_EL1:
 548       case MISCREG_DBGBVR1_EL1:
 549       case MISCREG_DBGBVR2_EL1:
 550       case MISCREG_DBGBVR3_EL1:
 551       case MISCREG_DBGBVR4_EL1:
 552       case MISCREG_DBGBVR5_EL1:
 553       case MISCREG_DBGBVR6_EL1:
 554       case MISCREG_DBGBVR7_EL1:
 555       case MISCREG_DBGBVR8_EL1:
 556       case MISCREG_DBGBVR9_EL1:
 557       case MISCREG_DBGBVR10_EL1:
 558       case MISCREG_DBGBVR11_EL1:
 559       case MISCREG_DBGBVR12_EL1:
 560       case MISCREG_DBGBVR13_EL1:
 561       case MISCREG_DBGBVR14_EL1:
 562       case MISCREG_DBGBVR15_EL1:
 563       case MISCREG_DBGBCR0_EL1:
 564       case MISCREG_DBGBCR1_EL1:
 565       case MISCREG_DBGBCR2_EL1:
 566       case MISCREG_DBGBCR3_EL1:
 567       case MISCREG_DBGBCR4_EL1:
 568       case MISCREG_DBGBCR5_EL1:
 569       case MISCREG_DBGBCR6_EL1:
 570       case MISCREG_DBGBCR7_EL1:
 571       case MISCREG_DBGBCR8_EL1:
 572       case MISCREG_DBGBCR9_EL1:
 573       case MISCREG_DBGBCR10_EL1:
 574       case MISCREG_DBGBCR11_EL1:
 575       case MISCREG_DBGBCR12_EL1:
 576       case MISCREG_DBGBCR13_EL1:
 577       case MISCREG_DBGBCR14_EL1:
 578       case MISCREG_DBGBCR15_EL1:
 579       case MISCREG_DBGWVR0_EL1:
 580       case MISCREG_DBGWVR1_EL1:
 581       case MISCREG_DBGWVR2_EL1:
 582       case MISCREG_DBGWVR3_EL1:
 583       case MISCREG_DBGWVR4_EL1:
 584       case MISCREG_DBGWVR5_EL1:
 585       case MISCREG_DBGWVR6_EL1:
 586       case MISCREG_DBGWVR7_EL1:
 587       case MISCREG_DBGWVR8_EL1:
 588       case MISCREG_DBGWVR9_EL1:
 589       case MISCREG_DBGWVR10_EL1:
 590       case MISCREG_DBGWVR11_EL1:
 591       case MISCREG_DBGWVR12_EL1:
 592       case MISCREG_DBGWVR13_EL1:
 593       case MISCREG_DBGWVR14_EL1:
 594       case MISCREG_DBGWVR15_EL1:
 595       case MISCREG_DBGWCR0_EL1:
 596       case MISCREG_DBGWCR1_EL1:
 597       case MISCREG_DBGWCR2_EL1:
 598       case MISCREG_DBGWCR3_EL1:
 599       case MISCREG_DBGWCR4_EL1:
 600       case MISCREG_DBGWCR5_EL1:
 601       case MISCREG_DBGWCR6_EL1:
 602       case MISCREG_DBGWCR7_EL1:
 603       case MISCREG_DBGWCR8_EL1:
 604       case MISCREG_DBGWCR9_EL1:
 605       case MISCREG_DBGWCR10_EL1:
 606       case MISCREG_DBGWCR11_EL1:
 607       case MISCREG_DBGWCR12_EL1:
 608       case MISCREG_DBGWCR13_EL1:
 609       case MISCREG_DBGWCR14_EL1:
 610       case MISCREG_DBGWCR15_EL1:
 611       case MISCREG_MDCCINT_EL1:
 612         trap_to_hyp =  EL2Enabled(tc) && (el == EL1) && mdcr.tda;
 613         break;
 614       case MISCREG_ZCR_EL1:
 615         {
 616             bool from_el1 = (el == EL1) && EL2Enabled(tc) &&
 617                 ELIs64(tc, EL2) && ((!hcr.e2h && cptr.tz) ||
 618                         (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
 619             bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
 620                     (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
 621             trap_to_hyp = from_el1 || from_el2;
 622         }
 623         ec = EC_TRAPPED_SVE;
 624         immediate = 0;
 625         break;
 626       case MISCREG_ZCR_EL2:
 627         {
 628             bool from_el1 = (el == EL1) && EL2Enabled(tc) && hcr.nv;
 629             bool from_el2 = (el == EL2) && ((!hcr.e2h && cptr.tz) ||
 630                     (hcr.e2h && ((cptr.zen & 0x1) == 0x0)));
 631             trap_to_hyp = from_el1 || from_el2;
 632             ec = from_el1 ? EC_TRAPPED_MSR_MRS_64: EC_TRAPPED_SVE;
 633         }
 634         immediate = 0;
 635         break;
 636       default:
 637         break;
 638     }
 639     return trap_to_hyp;
 640 }
 641
 642 bool
 643 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 644                           ExceptionLevel el, ExceptionClass &ec,
 645                           uint32_t &immediate) const
 646 {
 647     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
 648     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 649     const HDCR mdcr = tc->readMiscReg(MISCREG_MDCR_EL3);
 650     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 651     bool trap_to_mon = false;
 652
 653     switch (misc_reg) {
 654       // FP/SIMD regs
 655       case MISCREG_FPCR:
 656       case MISCREG_FPSR:
 657       case MISCREG_FPEXC32_EL2:
 658         trap_to_mon = cptr.tfp && ELIs64(tc, EL3);
 659         ec = EC_TRAPPED_SIMD_FP;
 660         immediate = 0x1E00000;
 661         break;
 662       // CPACR, CPTR
 663       case MISCREG_CPACR_EL12:
 664         trap_to_mon = ((el == EL2 && cptr.tcpac && ELIs64(tc, EL3)) ||
 665             (el == EL1 && cptr.tcpac && ELIs64(tc, EL3) &&
 666              (!hcr.nv2 || hcr.nv1 || !hcr.nv))) ;
 667         break;
 668       case MISCREG_CPACR_EL1:
 669         trap_to_mon = el <= EL2 && cptr.tcpac && ELIs64(tc, EL3);
 670         break;
 671       case MISCREG_CPTR_EL2:
 672         if (el == EL2) {
 673             trap_to_mon = cptr.tcpac;
 674         }
 675         break;
 676 //      case MISCREG_LORC_EL1:
 677 //      case MISCREG_LOREA_EL1:
 678 //      case MISCREG_LORID_EL1:
 679 //      case MISCREG_LORN_EL1:
 680 //      case MISCREG_LORSA_EL1:
 681 //        trap_to_mon = (el <= EL2) && scr.ns && ELIs64(tc,EL3)
 682 //            && hcr.tlor && (!hcr.e2h || (hcr.e2h && !hcr.tge));
 683 //        break;
 684        case MISCREG_MDCCSR_EL0:
 685          trap_to_mon = (el <= EL2) && ELIs64(tc, EL3) && mdcr.tda == 0x1;
 686          break;
 687       case MISCREG_APDAKeyHi_EL1:
 688       case MISCREG_APDAKeyLo_EL1:
 689       case MISCREG_APDBKeyHi_EL1:
 690       case MISCREG_APDBKeyLo_EL1:
 691       case MISCREG_APGAKeyHi_EL1:
 692       case MISCREG_APGAKeyLo_EL1:
 693       case MISCREG_APIAKeyHi_EL1:
 694       case MISCREG_APIAKeyLo_EL1:
 695       case MISCREG_APIBKeyHi_EL1:
 696       case MISCREG_APIBKeyLo_EL1:
 697         trap_to_mon = (el == EL1 || el == EL2) && scr.apk == 0 &&
 698                       ELIs64(tc, EL3);
 699         break;
 700       // Generic Timer
 701       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 702         trap_to_mon = el == EL1 &&
 703                       isGenericTimerSystemAccessTrapEL3(misc_reg, tc);
 704         break;
 705       case MISCREG_DBGBVR0_EL1:
 706       case MISCREG_DBGBVR1_EL1:
 707       case MISCREG_DBGBVR2_EL1:
 708       case MISCREG_DBGBVR3_EL1:
 709       case MISCREG_DBGBVR4_EL1:
 710       case MISCREG_DBGBVR5_EL1:
 711       case MISCREG_DBGBVR6_EL1:
 712       case MISCREG_DBGBVR7_EL1:
 713       case MISCREG_DBGBVR8_EL1:
 714       case MISCREG_DBGBVR9_EL1:
 715       case MISCREG_DBGBVR10_EL1:
 716       case MISCREG_DBGBVR11_EL1:
 717       case MISCREG_DBGBVR12_EL1:
 718       case MISCREG_DBGBVR13_EL1:
 719       case MISCREG_DBGBVR14_EL1:
 720       case MISCREG_DBGBVR15_EL1:
 721       case MISCREG_DBGBCR0_EL1:
 722       case MISCREG_DBGBCR1_EL1:
 723       case MISCREG_DBGBCR2_EL1:
 724       case MISCREG_DBGBCR3_EL1:
 725       case MISCREG_DBGBCR4_EL1:
 726       case MISCREG_DBGBCR5_EL1:
 727       case MISCREG_DBGBCR6_EL1:
 728       case MISCREG_DBGBCR7_EL1:
 729       case MISCREG_DBGBCR8_EL1:
 730       case MISCREG_DBGBCR9_EL1:
 731       case MISCREG_DBGBCR10_EL1:
 732       case MISCREG_DBGBCR11_EL1:
 733       case MISCREG_DBGBCR12_EL1:
 734       case MISCREG_DBGBCR13_EL1:
 735       case MISCREG_DBGBCR14_EL1:
 736       case MISCREG_DBGBCR15_EL1:
 737       case MISCREG_DBGVCR32_EL2:
 738       case MISCREG_DBGWVR0_EL1:
 739       case MISCREG_DBGWVR1_EL1:
 740       case MISCREG_DBGWVR2_EL1:
 741       case MISCREG_DBGWVR3_EL1:
 742       case MISCREG_DBGWVR4_EL1:
 743       case MISCREG_DBGWVR5_EL1:
 744       case MISCREG_DBGWVR6_EL1:
 745       case MISCREG_DBGWVR7_EL1:
 746       case MISCREG_DBGWVR8_EL1:
 747       case MISCREG_DBGWVR9_EL1:
 748       case MISCREG_DBGWVR10_EL1:
 749       case MISCREG_DBGWVR11_EL1:
 750       case MISCREG_DBGWVR12_EL1:
 751       case MISCREG_DBGWVR13_EL1:
 752       case MISCREG_DBGWVR14_EL1:
 753       case MISCREG_DBGWVR15_EL1:
 754       case MISCREG_DBGWCR0_EL1:
 755       case MISCREG_DBGWCR1_EL1:
 756       case MISCREG_DBGWCR2_EL1:
 757       case MISCREG_DBGWCR3_EL1:
 758       case MISCREG_DBGWCR4_EL1:
 759       case MISCREG_DBGWCR5_EL1:
 760       case MISCREG_DBGWCR6_EL1:
 761       case MISCREG_DBGWCR7_EL1:
 762       case MISCREG_DBGWCR8_EL1:
 763       case MISCREG_DBGWCR9_EL1:
 764       case MISCREG_DBGWCR10_EL1:
 765       case MISCREG_DBGWCR11_EL1:
 766       case MISCREG_DBGWCR12_EL1:
 767       case MISCREG_DBGWCR13_EL1:
 768       case MISCREG_DBGWCR14_EL1:
 769       case MISCREG_DBGWCR15_EL1:
 770       case MISCREG_MDCCINT_EL1:
 771       case MISCREG_MDCR_EL2:
 772         trap_to_mon = ELIs64(tc, EL3) && mdcr.tda && (el == EL2);
 773         break;
 774       case MISCREG_ZCR_EL1:
 775         trap_to_mon = !cptr.ez && ((el == EL3) ||
 776               ((el <= EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
 777         ec = EC_TRAPPED_SVE;
 778         immediate = 0;
 779         break;
 780       case MISCREG_ZCR_EL2:
 781         trap_to_mon = !cptr.ez && ((el == EL3) ||
 782               ((el == EL2) && ArmSystem::haveEL(tc,EL3) && ELIs64(tc, EL3)));
 783         ec = EC_TRAPPED_SVE;
 784         immediate = 0;
 785         break;
 786       case MISCREG_ZCR_EL3:
 787         trap_to_mon = !cptr.ez && (el == EL3);
 788         ec = EC_TRAPPED_SVE;
 789         immediate = 0;
 790         break;
 791       default:
 792         break;
 793     }
 794     return trap_to_mon;
 795 }
 796
 797 RegVal
 798 MiscRegImmOp64::miscRegImm() const
 799 {
 800     if (dest == MISCREG_SPSEL) {
 801         return imm & 0x1;
 802     } else if (dest == MISCREG_PAN) {
 803         return (imm & 0x1) << 22;
 804     } else {
 805         panic("Not a valid PSTATE field register\n");
 806     }
 807 }
 808
 809 std::string
 810 MiscRegImmOp64::generateDisassembly(
 811         Addr pc, const Loader::SymbolTable *symtab) const
 812 {
 813     std::stringstream ss;
 814     printMnemonic(ss);
 815     printMiscReg(ss, dest);
 816     ss << ", ";
 817     ccprintf(ss, "#0x%x", imm);
 818     return ss.str();
 819 }
 820
 821 std::string
 822 MiscRegRegImmOp64::generateDisassembly(
 823     Addr pc, const Loader::SymbolTable *symtab) const
 824 {
 825     std::stringstream ss;
 826     printMnemonic(ss);
 827     printMiscReg(ss, dest);
 828     ss << ", ";
 829     printIntReg(ss, op1);
 830     return ss.str();
 831 }
 832
 833 std::string
 834 RegMiscRegImmOp64::generateDisassembly(
 835     Addr pc, const Loader::SymbolTable *symtab) const
 836 {
 837     std::stringstream ss;
 838     printMnemonic(ss);
 839     printIntReg(ss, dest);
 840     ss << ", ";
 841     printMiscReg(ss, op1);
 842     return ss.str();
 843 }
 844
 845 Fault
 846 MiscRegImplDefined64::execute(ExecContext *xc,
 847                               Trace::InstRecord *traceData) const
 848 {
 849     auto tc = xc->tcBase();
 850     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 851     const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
 852
 853     Fault fault = trap(tc, miscReg, el, imm);
 854
 855     if (fault != NoFault) {
 856         return fault;
 857
 858     } else if (warning) {
 859         warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
 860         return NoFault;
 861
 862     } else {
 863         return std::make_shared<UndefinedInstruction>(machInst, false,
 864                                                       mnemonic);
 865     }
 866 }
 867
 868 std::string
 869 MiscRegImplDefined64::generateDisassembly(
 870         Addr pc, const Loader::SymbolTable *symtab) const
 871 {
 872     return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
 873 }
 874
 875 std::string
 876 RegNone::generateDisassembly(
 877     Addr pc, const Loader::SymbolTable *symtab) const
 878 {
 879     std::stringstream ss;
 880     printMnemonic(ss);
 881     printIntReg(ss, dest);
 882     return ss.str();
 883 }