src/arch/arm/insts/misc64.cc

   1 /*
   2  * Copyright (c) 2011-2013,2017-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/insts/misc64.hh"
  39 #include "arch/arm/isa.hh"
  40
  41 std::string
  42 ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
  43 {
  44     std::stringstream ss;
  45     printMnemonic(ss, "", false);
  46     ccprintf(ss, "#0x%x", imm);
  47     return ss.str();
  48 }
  49
  50 std::string
  51 RegRegImmImmOp64::generateDisassembly(
  52         Addr pc, const Loader::SymbolTable *symtab) const
  53 {
  54     std::stringstream ss;
  55     printMnemonic(ss, "", false);
  56     printIntReg(ss, dest);
  57     ss << ", ";
  58     printIntReg(ss, op1);
  59     ccprintf(ss, ", #%d, #%d", imm1, imm2);
  60     return ss.str();
  61 }
  62
  63 std::string
  64 RegRegRegImmOp64::generateDisassembly(
  65     Addr pc, const Loader::SymbolTable *symtab) const
  66 {
  67     std::stringstream ss;
  68     printMnemonic(ss, "", false);
  69     printIntReg(ss, dest);
  70     ss << ", ";
  71     printIntReg(ss, op1);
  72     ss << ", ";
  73     printIntReg(ss, op2);
  74     ccprintf(ss, ", #%d", imm);
  75     return ss.str();
  76 }
  77
  78 std::string
  79 UnknownOp64::generateDisassembly(
  80         Addr pc, const Loader::SymbolTable *symtab) const
  81 {
  82     return csprintf("%-10s (inst %#08x)", "unknown", encoding());
  83 }
  84
  85 Fault
  86 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg,
  87                   ExceptionLevel el, uint32_t immediate) const
  88 {
  89     ExceptionClass ec = EC_TRAPPED_MSR_MRS_64;
  90
  91     // Check for traps to supervisor (FP/SIMD regs)
  92     if (el <= EL1 && checkEL1Trap(tc, misc_reg, el, ec, immediate)) {
  93         return std::make_shared<SupervisorTrap>(machInst, immediate, ec);
  94     }
  95
  96     // Check for traps to hypervisor
  97     if ((ArmSystem::haveVirtualization(tc) && el <= EL2) &&
  98         checkEL2Trap(tc, misc_reg, el, ec, immediate)) {
  99         return std::make_shared<HypervisorTrap>(machInst, immediate, ec);
 100     }
 101
 102     // Check for traps to secure monitor
 103     if ((ArmSystem::haveSecurity(tc) && el <= EL3) &&
 104         checkEL3Trap(tc, misc_reg, el, ec, immediate)) {
 105         return std::make_shared<SecureMonitorTrap>(machInst, immediate, ec);
 106     }
 107
 108     return NoFault;
 109 }
 110
 111 bool
 112 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 113                           ExceptionLevel el, ExceptionClass &ec,
 114                           uint32_t &immediate) const
 115 {
 116     const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
 117     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 118     const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
 119     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 120
 121     bool trap_to_sup = false;
 122     switch (misc_reg) {
 123       case MISCREG_DAIF:
 124         trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
 125         trap_to_sup = trap_to_sup ||
 126             (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
 127         break;
 128       case MISCREG_DC_ZVA_Xt:
 129         // In syscall-emulation mode, this test is skipped and DCZVA is always
 130         // allowed at EL0
 131         trap_to_sup =  el == EL0 && !sctlr.dze && FullSystem;
 132         break;
 133       case MISCREG_DC_CIVAC_Xt:
 134       case MISCREG_DC_CVAC_Xt:
 135         trap_to_sup = el == EL0 && !sctlr.uci;
 136         break;
 137       case MISCREG_FPCR:
 138       case MISCREG_FPSR:
 139       case MISCREG_FPEXC32_EL2:
 140         if ((el == EL0 && cpacr.fpen != 0x3) ||
 141             (el == EL1 && !(cpacr.fpen & 0x1))) {
 142             trap_to_sup = true;
 143             ec = EC_TRAPPED_SIMD_FP;
 144             immediate = 0x1E00000;
 145         }
 146         break;
 147       case MISCREG_DC_CVAU_Xt:
 148         trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
 149             el == EL0;
 150         break;
 151       case MISCREG_CTR_EL0:
 152         trap_to_sup = el == EL0 && !sctlr.uct &&
 153             (!hcr.tge || (!scr.ns && !scr.eel2));
 154         break;
 155        case MISCREG_MDCCSR_EL0:
 156          {
 157              DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
 158              trap_to_sup = el == EL0 && mdscr.tdcc &&
 159                      (hcr.tge == 0x0 || ( scr.ns == 0x0));
 160          }
 161          break;
 162      case MISCREG_ZCR_EL1:
 163         trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
 164         break;
 165       // Generic Timer
 166       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 167         trap_to_sup = el == EL0 &&
 168                       isGenericTimerSystemAccessTrapEL1(misc_reg, tc);
 169         break;
 170       default:
 171         break;
 172     }
 173     return trap_to_sup;
 174 }
 175
 176 bool
 177 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 178                           ExceptionLevel el, ExceptionClass &ec,
 179                           uint32_t &immediate) const
 180 {
 181     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
 182     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
 183     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 184     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 185
 186     bool trap_to_hyp = false;
 187
 188     if (!inSecureState(scr, cpsr) && (el != EL2)) {
 189         switch (misc_reg) {
 190           // FP/SIMD regs
 191           case MISCREG_FPCR:
 192           case MISCREG_FPSR:
 193           case MISCREG_FPEXC32_EL2:
 194             trap_to_hyp = cptr.tfp;
 195             ec = EC_TRAPPED_SIMD_FP;
 196             immediate = 0x1E00000;
 197             break;
 198           // CPACR
 199           case MISCREG_CPACR_EL1:
 200             trap_to_hyp = cptr.tcpac && el == EL1;
 201             break;
 202           // Virtual memory control regs
 203           case MISCREG_SCTLR_EL1:
 204           case MISCREG_TTBR0_EL1:
 205           case MISCREG_TTBR1_EL1:
 206           case MISCREG_TCR_EL1:
 207           case MISCREG_ESR_EL1:
 208           case MISCREG_FAR_EL1:
 209           case MISCREG_AFSR0_EL1:
 210           case MISCREG_AFSR1_EL1:
 211           case MISCREG_MAIR_EL1:
 212           case MISCREG_AMAIR_EL1:
 213           case MISCREG_CONTEXTIDR_EL1:
 214             trap_to_hyp =
 215                 ((hcr.trvm && miscRead) || (hcr.tvm && !miscRead)) &&
 216                 el == EL1;
 217             break;
 218           // TLB maintenance instructions
 219           case MISCREG_TLBI_VMALLE1:
 220           case MISCREG_TLBI_VAE1_Xt:
 221           case MISCREG_TLBI_ASIDE1_Xt:
 222           case MISCREG_TLBI_VAAE1_Xt:
 223           case MISCREG_TLBI_VALE1_Xt:
 224           case MISCREG_TLBI_VAALE1_Xt:
 225           case MISCREG_TLBI_VMALLE1IS:
 226           case MISCREG_TLBI_VAE1IS_Xt:
 227           case MISCREG_TLBI_ASIDE1IS_Xt:
 228           case MISCREG_TLBI_VAAE1IS_Xt:
 229           case MISCREG_TLBI_VALE1IS_Xt:
 230           case MISCREG_TLBI_VAALE1IS_Xt:
 231             trap_to_hyp = hcr.ttlb && el == EL1;
 232             break;
 233           // Cache maintenance instructions to the point of unification
 234           case MISCREG_IC_IVAU_Xt:
 235           case MISCREG_ICIALLU:
 236           case MISCREG_ICIALLUIS:
 237           case MISCREG_DC_CVAU_Xt:
 238             trap_to_hyp = hcr.tpu && el <= EL1;
 239             break;
 240           // Data/Unified cache maintenance instructions to the
 241           // point of coherency
 242           case MISCREG_DC_IVAC_Xt:
 243           case MISCREG_DC_CIVAC_Xt:
 244           case MISCREG_DC_CVAC_Xt:
 245             trap_to_hyp = hcr.tpc && el <= EL1;
 246             break;
 247           // Data/Unified cache maintenance instructions by set/way
 248           case MISCREG_DC_ISW_Xt:
 249           case MISCREG_DC_CSW_Xt:
 250           case MISCREG_DC_CISW_Xt:
 251             trap_to_hyp = hcr.tsw && el == EL1;
 252             break;
 253           // ACTLR
 254           case MISCREG_ACTLR_EL1:
 255             trap_to_hyp = hcr.tacr && el == EL1;
 256             break;
 257
 258           case MISCREG_APDAKeyHi_EL1:
 259           case MISCREG_APDAKeyLo_EL1:
 260           case MISCREG_APDBKeyHi_EL1:
 261           case MISCREG_APDBKeyLo_EL1:
 262           case MISCREG_APGAKeyHi_EL1:
 263           case MISCREG_APGAKeyLo_EL1:
 264           case MISCREG_APIAKeyHi_EL1:
 265           case MISCREG_APIAKeyLo_EL1:
 266           case MISCREG_APIBKeyHi_EL1:
 267           case MISCREG_APIBKeyLo_EL1:
 268             trap_to_hyp = el==EL1 && hcr.apk == 0;
 269             break;
 270           // @todo: Trap implementation-dependent functionality based on
 271           // hcr.tidcp
 272
 273           // ID regs, group 3
 274           case MISCREG_ID_PFR0_EL1:
 275           case MISCREG_ID_PFR1_EL1:
 276           case MISCREG_ID_DFR0_EL1:
 277           case MISCREG_ID_AFR0_EL1:
 278           case MISCREG_ID_MMFR0_EL1:
 279           case MISCREG_ID_MMFR1_EL1:
 280           case MISCREG_ID_MMFR2_EL1:
 281           case MISCREG_ID_MMFR3_EL1:
 282           case MISCREG_ID_ISAR0_EL1:
 283           case MISCREG_ID_ISAR1_EL1:
 284           case MISCREG_ID_ISAR2_EL1:
 285           case MISCREG_ID_ISAR3_EL1:
 286           case MISCREG_ID_ISAR4_EL1:
 287           case MISCREG_ID_ISAR5_EL1:
 288           case MISCREG_MVFR0_EL1:
 289           case MISCREG_MVFR1_EL1:
 290           case MISCREG_MVFR2_EL1:
 291           case MISCREG_ID_AA64PFR0_EL1:
 292           case MISCREG_ID_AA64PFR1_EL1:
 293           case MISCREG_ID_AA64DFR0_EL1:
 294           case MISCREG_ID_AA64DFR1_EL1:
 295           case MISCREG_ID_AA64ISAR0_EL1:
 296           case MISCREG_ID_AA64ISAR1_EL1:
 297           case MISCREG_ID_AA64MMFR0_EL1:
 298           case MISCREG_ID_AA64MMFR1_EL1:
 299           case MISCREG_ID_AA64MMFR2_EL1:
 300           case MISCREG_ID_AA64AFR0_EL1:
 301           case MISCREG_ID_AA64AFR1_EL1:
 302             assert(miscRead);
 303             trap_to_hyp = hcr.tid3 && el == EL1;
 304             break;
 305           // ID regs, group 2
 306           case MISCREG_CTR_EL0:
 307           case MISCREG_CCSIDR_EL1:
 308           case MISCREG_CLIDR_EL1:
 309           case MISCREG_CSSELR_EL1:
 310             trap_to_hyp = hcr.tid2 && el <= EL1;
 311             break;
 312           // ID regs, group 1
 313           case MISCREG_AIDR_EL1:
 314           case MISCREG_REVIDR_EL1:
 315             assert(miscRead);
 316             trap_to_hyp = hcr.tid1 && el == EL1;
 317             break;
 318           case MISCREG_IMPDEF_UNIMPL:
 319             trap_to_hyp = hcr.tidcp && el == EL1;
 320             break;
 321           // GICv3 regs
 322           case MISCREG_ICC_SGI0R_EL1:
 323             {
 324                 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
 325                 if (isa->haveGICv3CpuIfc())
 326                     trap_to_hyp = hcr.fmo && el == EL1;
 327             }
 328             break;
 329           case MISCREG_ICC_SGI1R_EL1:
 330           case MISCREG_ICC_ASGI1R_EL1:
 331             {
 332                 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
 333                 if (isa->haveGICv3CpuIfc())
 334                     trap_to_hyp = hcr.imo && el == EL1;
 335             }
 336             break;
 337           // Generic Timer
 338           case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 339             trap_to_hyp = el <= EL1 &&
 340                           isGenericTimerSystemAccessTrapEL2(misc_reg, tc);
 341             break;
 342           default:
 343             break;
 344         }
 345     }
 346     return trap_to_hyp;
 347 }
 348
 349 bool
 350 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
 351                           ExceptionLevel el, ExceptionClass &ec,
 352                           uint32_t &immediate) const
 353 {
 354     const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
 355     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
 356     bool trap_to_mon = false;
 357
 358     switch (misc_reg) {
 359       // FP/SIMD regs
 360       case MISCREG_FPCR:
 361       case MISCREG_FPSR:
 362       case MISCREG_FPEXC32_EL2:
 363         trap_to_mon = cptr.tfp;
 364         ec = EC_TRAPPED_SIMD_FP;
 365         immediate = 0x1E00000;
 366         break;
 367       // CPACR, CPTR
 368       case MISCREG_CPACR_EL1:
 369         if (el == EL1 || el == EL2) {
 370            trap_to_mon = cptr.tcpac;
 371         }
 372         break;
 373       case MISCREG_CPTR_EL2:
 374         if (el == EL2) {
 375             trap_to_mon = cptr.tcpac;
 376         }
 377         break;
 378       case MISCREG_APDAKeyHi_EL1:
 379       case MISCREG_APDAKeyLo_EL1:
 380       case MISCREG_APDBKeyHi_EL1:
 381       case MISCREG_APDBKeyLo_EL1:
 382       case MISCREG_APGAKeyHi_EL1:
 383       case MISCREG_APGAKeyLo_EL1:
 384       case MISCREG_APIAKeyHi_EL1:
 385       case MISCREG_APIAKeyLo_EL1:
 386       case MISCREG_APIBKeyHi_EL1:
 387       case MISCREG_APIBKeyLo_EL1:
 388         trap_to_mon = (el==EL1 || el==EL2) && scr.apk==0 && ELIs64(tc, EL3);
 389         break;
 390       // Generic Timer
 391       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
 392         trap_to_mon = el == EL1 &&
 393                       isGenericTimerSystemAccessTrapEL3(misc_reg, tc);
 394         break;
 395       default:
 396         break;
 397     }
 398     return trap_to_mon;
 399 }
 400
 401 RegVal
 402 MiscRegImmOp64::miscRegImm() const
 403 {
 404     if (dest == MISCREG_SPSEL) {
 405         return imm & 0x1;
 406     } else if (dest == MISCREG_PAN) {
 407         return (imm & 0x1) << 22;
 408     } else {
 409         panic("Not a valid PSTATE field register\n");
 410     }
 411 }
 412
 413 std::string
 414 MiscRegImmOp64::generateDisassembly(
 415         Addr pc, const Loader::SymbolTable *symtab) const
 416 {
 417     std::stringstream ss;
 418     printMnemonic(ss);
 419     printMiscReg(ss, dest);
 420     ss << ", ";
 421     ccprintf(ss, "#0x%x", imm);
 422     return ss.str();
 423 }
 424
 425 std::string
 426 MiscRegRegImmOp64::generateDisassembly(
 427     Addr pc, const Loader::SymbolTable *symtab) const
 428 {
 429     std::stringstream ss;
 430     printMnemonic(ss);
 431     printMiscReg(ss, dest);
 432     ss << ", ";
 433     printIntReg(ss, op1);
 434     return ss.str();
 435 }
 436
 437 std::string
 438 RegMiscRegImmOp64::generateDisassembly(
 439     Addr pc, const Loader::SymbolTable *symtab) const
 440 {
 441     std::stringstream ss;
 442     printMnemonic(ss);
 443     printIntReg(ss, dest);
 444     ss << ", ";
 445     printMiscReg(ss, op1);
 446     return ss.str();
 447 }
 448
 449 Fault
 450 MiscRegImplDefined64::execute(ExecContext *xc,
 451                               Trace::InstRecord *traceData) const
 452 {
 453     auto tc = xc->tcBase();
 454     const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 455     const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
 456
 457     Fault fault = trap(tc, miscReg, el, imm);
 458
 459     if (fault != NoFault) {
 460         return fault;
 461
 462     } else if (warning) {
 463         warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str());
 464         return NoFault;
 465
 466     } else {
 467         return std::make_shared<UndefinedInstruction>(machInst, false,
 468                                                       mnemonic);
 469     }
 470 }
 471
 472 std::string
 473 MiscRegImplDefined64::generateDisassembly(
 474         Addr pc, const Loader::SymbolTable *symtab) const
 475 {
 476     return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
 477 }