src/arch/arm/insts/misc64.hh

   1 /*
   2  * Copyright (c) 2011-2013,2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
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  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
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  17  * notice, this list of conditions and the following disclaimer;
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  19  * notice, this list of conditions and the following disclaimer in the
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  23  * this software without specific prior written permission.
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  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __ARCH_ARM_INSTS_MISC64_HH__
  39 #define __ARCH_ARM_INSTS_MISC64_HH__
  40
  41 #include "arch/arm/insts/static_inst.hh"
  42
  43 class ImmOp64 : public ArmISA::ArmStaticInst
  44 {
  45   protected:
  46     uint64_t imm;
  47
  48     ImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
  49             OpClass __opClass, uint64_t _imm) :
  50         ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
  51     {}
  52
  53     std::string generateDisassembly(
  54             Addr pc, const Loader::SymbolTable *symtab) const override;
  55 };
  56
  57 class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
  58 {
  59   protected:
  60     ArmISA::IntRegIndex dest;
  61     ArmISA::IntRegIndex op1;
  62     uint64_t imm1;
  63     uint64_t imm2;
  64
  65     RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
  66                      OpClass __opClass, ArmISA::IntRegIndex _dest,
  67                      ArmISA::IntRegIndex _op1, uint64_t _imm1,
  68                      int64_t _imm2) :
  69         ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
  70         dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
  71     {}
  72
  73     std::string generateDisassembly(
  74             Addr pc, const Loader::SymbolTable *symtab) const override;
  75 };
  76
  77 class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
  78 {
  79   protected:
  80     ArmISA::IntRegIndex dest;
  81     ArmISA::IntRegIndex op1;
  82     ArmISA::IntRegIndex op2;
  83     uint64_t imm;
  84
  85     RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
  86                      OpClass __opClass, ArmISA::IntRegIndex _dest,
  87                      ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
  88                      uint64_t _imm) :
  89         ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
  90         dest(_dest), op1(_op1), op2(_op2), imm(_imm)
  91     {}
  92
  93     std::string generateDisassembly(
  94             Addr pc, const Loader::SymbolTable *symtab) const override;
  95 };
  96
  97 class UnknownOp64 : public ArmISA::ArmStaticInst
  98 {
  99   protected:
 100
 101     UnknownOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
 102             OpClass __opClass) :
 103         ArmISA::ArmStaticInst(mnem, _machInst, __opClass)
 104     {}
 105
 106     std::string generateDisassembly(
 107             Addr pc, const Loader::SymbolTable *symtab) const override;
 108 };
 109
 110 /**
 111  * This class is implementing the Base class for a generic AArch64
 112  * instruction which is making use of system registers (MiscReg), like
 113  * MSR,MRS,SYS.  The common denominator or those instruction is the
 114  * chance that the system register access is trapped to an upper
 115  * Exception level. MiscRegOp64 is providing that feature.  Other
 116  * "pseudo" instructions, like access to implementation defined
 117  * registers can inherit from this class to make use of the trapping
 118  * functionalities even if there is no data movement between GPRs and
 119  * system register.
 120  */
 121 class MiscRegOp64 : public ArmISA::ArmStaticInst
 122 {
 123   protected:
 124     bool miscRead;
 125
 126     MiscRegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
 127                 OpClass __opClass, bool misc_read) :
 128         ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
 129         miscRead(misc_read)
 130     {}
 131
 132     Fault trap(ThreadContext *tc, ArmISA::MiscRegIndex misc_reg,
 133                ArmISA::ExceptionLevel el, uint32_t immediate) const;
 134   private:
 135     bool checkEL1Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
 136                       ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
 137                       uint32_t &immediate) const;
 138
 139     bool checkEL2Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
 140                       ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
 141                       uint32_t &immediate) const;
 142
 143     bool checkEL3Trap(ThreadContext *tc, const ArmISA::MiscRegIndex misc_reg,
 144                       ArmISA::ExceptionLevel el, ArmISA::ExceptionClass &ec,
 145                       uint32_t &immediate) const;
 146
 147 };
 148
 149 class MiscRegImmOp64 : public MiscRegOp64
 150 {
 151   protected:
 152     ArmISA::MiscRegIndex dest;
 153     uint32_t imm;
 154
 155     MiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
 156                    OpClass __opClass, ArmISA::MiscRegIndex _dest,
 157                    uint32_t _imm) :
 158         MiscRegOp64(mnem, _machInst, __opClass, false),
 159         dest(_dest), imm(_imm)
 160     {}
 161
 162     /** Returns the "register view" of the immediate field.
 163      * as if it was a MSR PSTATE REG instruction.
 164      * This means basically shifting and masking depending on
 165      * which PSTATE field is being set/cleared.
 166      */
 167     RegVal miscRegImm() const;
 168
 169     std::string generateDisassembly(
 170             Addr pc, const Loader::SymbolTable *symtab) const override;
 171 };
 172
 173 class MiscRegRegImmOp64 : public MiscRegOp64
 174 {
 175   protected:
 176     ArmISA::MiscRegIndex dest;
 177     ArmISA::IntRegIndex op1;
 178     uint32_t imm;
 179
 180     MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
 181                       OpClass __opClass, ArmISA::MiscRegIndex _dest,
 182                       ArmISA::IntRegIndex _op1, uint32_t _imm) :
 183         MiscRegOp64(mnem, _machInst, __opClass, false),
 184         dest(_dest), op1(_op1), imm(_imm)
 185     {}
 186
 187     std::string generateDisassembly(
 188             Addr pc, const Loader::SymbolTable *symtab) const override;
 189 };
 190
 191 class RegMiscRegImmOp64 : public MiscRegOp64
 192 {
 193   protected:
 194     ArmISA::IntRegIndex dest;
 195     ArmISA::MiscRegIndex op1;
 196     uint32_t imm;
 197
 198     RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
 199                       OpClass __opClass, ArmISA::IntRegIndex _dest,
 200                       ArmISA::MiscRegIndex _op1, uint32_t _imm) :
 201         MiscRegOp64(mnem, _machInst, __opClass, true),
 202         dest(_dest), op1(_op1), imm(_imm)
 203     {}
 204
 205     std::string generateDisassembly(
 206             Addr pc, const Loader::SymbolTable *symtab) const override;
 207 };
 208
 209 class MiscRegImplDefined64 : public MiscRegOp64
 210 {
 211   protected:
 212     const std::string fullMnemonic;
 213     const ArmISA::MiscRegIndex miscReg;
 214     const uint32_t imm;
 215     const bool warning;
 216
 217   public:
 218     MiscRegImplDefined64(const char *mnem, ArmISA::ExtMachInst _machInst,
 219                          ArmISA::MiscRegIndex misc_reg, bool misc_read,
 220                          uint32_t _imm, const std::string full_mnem,
 221                          bool _warning) :
 222         MiscRegOp64(mnem, _machInst, No_OpClass, misc_read),
 223         fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm),
 224         warning(_warning)
 225     {
 226         assert(miscReg == ArmISA::MISCREG_IMPDEF_UNIMPL);
 227     }
 228
 229   protected:
 230     Fault execute(ExecContext *xc,
 231                   Trace::InstRecord *traceData) const override;
 232
 233     std::string generateDisassembly(
 234             Addr pc, const Loader::SymbolTable *symtab) const override;
 235 };
 236
 237 class RegNone : public ArmStaticInst
 238 {
 239   protected:
 240     IntRegIndex dest;
 241
 242     RegNone(const char *mnem, ExtMachInst _machInst,
 243                      OpClass __opClass, IntRegIndex _dest) :
 244         ArmStaticInst(mnem, _machInst, __opClass),
 245         dest(_dest)
 246     {}
 247
 248     std::string generateDisassembly(
 249         Addr pc, const Loader::SymbolTable *symtab) const;
 250 };
 251
 252 #endif