src/arch/arm/insts/neon64_mem.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
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   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
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   8  * to a hardware implementation of the functionality of the software
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  10  * terms below provided that you ensure that this notice is replicated
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  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
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  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Mbou Eyole
  38  *          Giacomo Gabrielli
  39  */
  40
  41 /// @file
  42 /// Utility functions and datatypes used by AArch64 NEON memory instructions.
  43
  44 #ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__
  45 #define __ARCH_ARM_INSTS_NEON64_MEM_HH__
  46
  47 namespace ArmISA
  48 {
  49
  50 typedef uint64_t XReg;
  51
  52 /// 128-bit NEON vector register.
  53 struct VReg {
  54     XReg hi;
  55     XReg lo;
  56 };
  57
  58 /// Write a single NEON vector element leaving the others untouched.
  59 inline void
  60 writeVecElem(VReg *dest, XReg src, int index, int eSize)
  61 {
  62     // eSize must be less than 4:
  63     // 0 -> 8-bit elems,
  64     // 1 -> 16-bit elems,
  65     // 2 -> 32-bit elems,
  66     // 3 -> 64-bit elems
  67     assert(eSize <= 3);
  68
  69     int eBits = 8 << eSize;
  70     int lsbPos = index * eBits;
  71     assert(lsbPos < 128);
  72     int shiftAmt = lsbPos % 64;
  73
  74     XReg maskBits = -1;
  75     if (eBits == 64) {
  76         maskBits = 0;
  77     } else {
  78         maskBits = maskBits << eBits;
  79     }
  80     maskBits = ~maskBits;
  81
  82     XReg sMask = maskBits;
  83     maskBits = sMask << shiftAmt;
  84
  85     if (lsbPos < 64) {
  86         dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt);
  87     } else {
  88         dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt);
  89     }
  90 }
  91
  92 /// Read a single NEON vector element.
  93 inline XReg
  94 readVecElem(VReg src, int index, int eSize)
  95 {
  96     // eSize must be less than 4:
  97     // 0 -> 8-bit elems,
  98     // 1 -> 16-bit elems,
  99     // 2 -> 32-bit elems,
 100     // 3 -> 64-bit elems
 101     assert(eSize <= 3);
 102
 103     XReg data;
 104
 105     int eBits = 8 << eSize;
 106     int lsbPos = index * eBits;
 107     assert(lsbPos < 128);
 108     int shiftAmt = lsbPos % 64;
 109
 110     XReg maskBits = -1;
 111     if (eBits == 64) {
 112         maskBits = 0;
 113     } else {
 114         maskBits = maskBits << eBits;
 115     }
 116     maskBits = ~maskBits;
 117
 118     if (lsbPos < 64) {
 119         data = (src.lo >> shiftAmt) & maskBits;
 120     } else {
 121         data = (src.hi >> shiftAmt) & maskBits;
 122     }
 123     return data;
 124 }
 125
 126 }  // namespace ArmISA
 127
 128 #endif  // __ARCH_ARM_INSTS_NEON64_MEM_HH__