src/arch/arm/insts/pred_inst.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "arch/arm/insts/pred_inst.hh"
  42
  43 namespace ArmISA
  44 {
  45 std::string
  46 PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  47 {
  48     std::stringstream ss;
  49     unsigned rotate = machInst.rotate * 2;
  50     uint32_t imm = machInst.imm;
  51     imm = (imm << (32 - rotate)) | (imm >> rotate);
  52     printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField,
  53             (IntRegIndex)(uint32_t)machInst.rd,
  54             (IntRegIndex)(uint32_t)machInst.rn,
  55             (IntRegIndex)(uint32_t)machInst.rm,
  56             (IntRegIndex)(uint32_t)machInst.rs,
  57             machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
  58             imm);
  59     return ss.str();
  60 }
  61
  62 std::string
  63 PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  64 {
  65     std::stringstream ss;
  66     printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
  67             (IntRegIndex)(uint32_t)machInst.rd,
  68             (IntRegIndex)(uint32_t)machInst.rn,
  69             (IntRegIndex)(uint32_t)machInst.rm,
  70             (IntRegIndex)(uint32_t)machInst.rs,
  71             machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
  72             imm);
  73     return ss.str();
  74 }
  75
  76 std::string
  77 DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  78 {
  79     std::stringstream ss;
  80     printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
  81                   INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
  82     return ss.str();
  83 }
  84
  85 std::string
  86 DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  87 {
  88     std::stringstream ss;
  89     printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
  90                   op2, INTREG_ZERO, shiftAmt, shiftType, 0);
  91     return ss.str();
  92 }
  93
  94 std::string
  95 DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  96 {
  97     std::stringstream ss;
  98     printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
  99                   op2, shift, 0, shiftType, 0);
 100     return ss.str();
 101 }
 102
 103 std::string
 104 PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 105 {
 106     std::stringstream ss;
 107
 108     ccprintf(ss, "%-10s ", mnemonic);
 109
 110     return ss.str();
 111 }
 112 }