2 * Copyright (c) 2010, 2012-2013 ARM Limited
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14 * Copyright (c) 2007-2008 The Florida State University
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26 * this software without specific prior written permission.
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34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Stephen Hines
42 #ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43 #define __ARCH_ARM_INSTS_PREDINST_HH__
45 #include "arch/arm/insts/static_inst.hh"
46 #include "base/trace.hh"
50 static inline uint32_t
51 rotate_imm(uint32_t immValue, uint32_t rotateValue)
54 return rotateValue == 0 ? immValue :
55 (immValue >> rotateValue) | (immValue << (32 - rotateValue));
58 static inline uint32_t
59 modified_imm(uint8_t ctrlImm, uint8_t dataImm)
61 uint32_t bigData = dataImm;
62 uint32_t bigCtrl = ctrlImm;
68 return bigData | (bigData << 16);
70 return (bigData << 8) | (bigData << 24);
72 return (bigData << 0) | (bigData << 8) |
73 (bigData << 16) | (bigData << 24);
76 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
78 return bigData << (32 - bigCtrl);
81 static inline uint64_t
82 simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
83 bool isAarch64 = false)
85 uint64_t bigData = data;
90 bigData = (bigData << 0) | (bigData << 32);
94 bigData = (bigData << 8) | (bigData << 40);
98 bigData = (bigData << 16) | (bigData << 48);
102 bigData = (bigData << 24) | (bigData << 56);
106 bigData = (bigData << 0) | (bigData << 16) |
107 (bigData << 32) | (bigData << 48);
111 bigData = (bigData << 8) | (bigData << 24) |
112 (bigData << 40) | (bigData << 56);
115 bigData = (0xffULL << 0) | (bigData << 8) |
116 (0xffULL << 32) | (bigData << 40);
119 bigData = (0xffffULL << 0) | (bigData << 16) |
120 (0xffffULL << 32) | (bigData << 48);
125 for (int i = 7; i >= 0; i--) {
127 bigData |= (ULL(0xFF) << (i * 8));
131 bigData = (bigData << 0) | (bigData << 8) |
132 (bigData << 16) | (bigData << 24) |
133 (bigData << 32) | (bigData << 40) |
134 (bigData << 48) | (bigData << 56);
141 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
142 bigData = (bits(bigData, 5, 0) << 19) |
143 (bVal << 25) | (bits(bigData, 7) << 31);
144 bigData |= (bigData << 32);
146 } else if (isAarch64) {
147 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
148 bigData = (bits(bigData, 5, 0) << 48) |
149 (bVal << 54) | (bits(bigData, 7) << 63);
153 // Fall through, immediate encoding is invalid.
161 static inline uint64_t
162 vfp_modified_imm(uint8_t data, bool wide)
164 uint64_t bigData = data;
167 repData = bits(data, 6) ? 0xFF : 0;
168 bigData = (bits(bigData, 5, 0) << 48) |
169 (repData << 54) | (bits(~bigData, 6) << 62) |
170 (bits(bigData, 7) << 63);
172 repData = bits(data, 6) ? 0x1F : 0;
173 bigData = (bits(bigData, 5, 0) << 19) |
174 (repData << 25) | (bits(~bigData, 6) << 30) |
175 (bits(bigData, 7) << 31);
182 * Base class for predicated integer operations.
184 class PredOp : public ArmStaticInst
188 ConditionCode condCode;
191 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
192 ArmStaticInst(mnem, _machInst, __opClass)
194 if (machInst.aarch64)
196 else if (machInst.itstateMask)
197 condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
199 condCode = (ConditionCode)(unsigned)machInst.condCode;
204 * Base class for predicated immediate operations.
206 class PredImmOp : public PredOp
211 uint32_t rotated_imm;
212 uint32_t rotated_carry;
216 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
217 PredOp(mnem, _machInst, __opClass),
218 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
219 rotate(machInst.rotate << 1)
221 rotated_imm = rotate_imm(imm, rotate);
223 rotated_carry = bits(rotated_imm, 31);
226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
230 * Base class for predicated integer operations.
232 class PredIntOp : public PredOp
240 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
241 PredOp(mnem, _machInst, __opClass),
242 shift_size(machInst.shiftSize), shift(machInst.shift)
246 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
249 class DataImmOp : public PredOp
252 IntRegIndex dest, op1;
254 // Whether the carry flag should be modified if that's an option for
258 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
259 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
260 PredOp(mnem, _machInst, __opClass),
261 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
264 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
267 class DataRegOp : public PredOp
270 IntRegIndex dest, op1, op2;
272 ArmShiftType shiftType;
274 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
275 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
276 int32_t _shiftAmt, ArmShiftType _shiftType) :
277 PredOp(mnem, _machInst, __opClass),
278 dest(_dest), op1(_op1), op2(_op2),
279 shiftAmt(_shiftAmt), shiftType(_shiftType)
282 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
285 class DataRegRegOp : public PredOp
288 IntRegIndex dest, op1, op2, shift;
289 ArmShiftType shiftType;
291 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
292 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
293 IntRegIndex _shift, ArmShiftType _shiftType) :
294 PredOp(mnem, _machInst, __opClass),
295 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
296 shiftType(_shiftType)
299 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
303 * Base class for predicated macro-operations.
305 class PredMacroOp : public PredOp
309 uint32_t numMicroops;
310 StaticInstPtr * microOps;
313 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
314 PredOp(mnem, _machInst, __opClass),
315 numMicroops(0), microOps(nullptr)
317 // We rely on the subclasses of this object to handle the
318 // initialization of the micro-operations, since they are
319 // all of variable length
320 flags[IsMacroop] = true;
330 fetchMicroop(MicroPC microPC) const
332 assert(microPC < numMicroops);
333 return microOps[microPC];
336 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
340 * Base class for predicated micro-operations.
342 class PredMicroop : public PredOp
345 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
346 PredOp(mnem, _machInst, __opClass)
348 flags[IsMicroop] = true;
352 advancePC(PCState &pcState) const
354 if (flags[IsLastMicroop])
362 #endif //__ARCH_ARM_INSTS_PREDINST_HH__