src/arch/arm/insts/static_inst.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Stephen Hines
  41  */
  42 #ifndef __ARCH_ARM_INSTS_STATICINST_HH__
  43 #define __ARCH_ARM_INSTS_STATICINST_HH__
  44
  45 #include "base/trace.hh"
  46 #include "cpu/static_inst.hh"
  47
  48 namespace ArmISA
  49 {
  50 class ArmStaticInst : public StaticInst
  51 {
  52   protected:
  53     int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
  54                          uint32_t type, uint32_t cfval) const;
  55     int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
  56                         uint32_t type, uint32_t cfval) const;
  57
  58     bool shift_carry_imm(uint32_t base, uint32_t shamt,
  59                          uint32_t type, uint32_t cfval) const;
  60     bool shift_carry_rs(uint32_t base, uint32_t shamt,
  61                         uint32_t type, uint32_t cfval) const;
  62
  63     // Constructor
  64     ArmStaticInst(const char *mnem, ExtMachInst _machInst,
  65                   OpClass __opClass)
  66         : StaticInst(mnem, _machInst, __opClass)
  67     {
  68     }
  69
  70     inline static std::string
  71     inst2string(MachInst machInst)
  72     {
  73         std::string str = "";
  74         uint32_t mask = (1 << 31);
  75
  76         while (mask) {
  77             str += ((machInst & mask) ? "1" : "0");
  78             mask = mask >> 1;
  79         }
  80
  81         return str;
  82     }
  83
  84     /// Print a register name for disassembly given the unique
  85     /// dependence tag number (FP or int).
  86     void printReg(std::ostream &os, int reg) const;
  87     void printMnemonic(std::ostream &os,
  88                        const std::string &suffix = "",
  89                        bool withPred = true) const;
  90     void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
  91                         const std::string &prefix, const Addr addr,
  92                         const std::string &suffix) const;
  93     void printShiftOperand(std::ostream &os, IntRegIndex rm,
  94                            bool immShift, uint32_t shiftAmt,
  95                            IntRegIndex rs, ArmShiftType type) const;
  96
  97
  98     void printDataInst(std::ostream &os, bool withImm) const;
  99     void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
 100                        IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
 101                        IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
 102                        uint32_t imm) const;
 103
 104     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 105
 106     static uint32_t
 107     cpsrWriteByInstr(CPSR cpsr, uint32_t val,
 108             uint8_t byteMask, bool affectState)
 109     {
 110         bool privileged = (cpsr.mode != MODE_USER);
 111
 112         uint32_t bitMask = 0;
 113
 114         if (bits(byteMask, 3)) {
 115             unsigned lowIdx = affectState ? 24 : 27;
 116             bitMask = bitMask | mask(31, lowIdx);
 117         }
 118         if (bits(byteMask, 2)) {
 119             bitMask = bitMask | mask(19, 16);
 120         }
 121         if (bits(byteMask, 1)) {
 122             unsigned highIdx = affectState ? 15 : 9;
 123             unsigned lowIdx = privileged ? 8 : 9;
 124             bitMask = bitMask | mask(highIdx, lowIdx);
 125         }
 126         if (bits(byteMask, 0)) {
 127             if (privileged) {
 128                 bitMask = bitMask | mask(7, 6);
 129                 bitMask = bitMask | mask(5);
 130             }
 131             if (affectState)
 132                 bitMask = bitMask | (1 << 5);
 133         }
 134
 135         return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
 136     }
 137
 138     static uint32_t
 139     spsrWriteByInstr(uint32_t spsr, uint32_t val,
 140             uint8_t byteMask, bool affectState)
 141     {
 142         uint32_t bitMask = 0;
 143
 144         if (bits(byteMask, 3))
 145             bitMask = bitMask | mask(31, 24);
 146         if (bits(byteMask, 2))
 147             bitMask = bitMask | mask(19, 16);
 148         if (bits(byteMask, 1))
 149             bitMask = bitMask | mask(15, 8);
 150         if (bits(byteMask, 0))
 151             bitMask = bitMask | mask(7, 0);
 152
 153         return ((spsr & ~bitMask) | (val & bitMask));
 154     }
 155
 156     template<class XC>
 157     static Addr
 158     readPC(XC *xc)
 159     {
 160         Addr pc = xc->readPC();
 161         Addr tBit = pc & (ULL(1) << PcTBitShift);
 162         if (tBit)
 163             return pc + 4;
 164         else
 165             return pc + 8;
 166     }
 167
 168     // Perform an regular branch.
 169     template<class XC>
 170     static void
 171     setNextPC(XC *xc, Addr val)
 172     {
 173         xc->setNextPC((xc->readNextPC() & PcModeMask) |
 174                       (val & ~PcModeMask));
 175     }
 176
 177     // Perform an interworking branch.
 178     template<class XC>
 179     static void
 180     setIWNextPC(XC *xc, Addr val)
 181     {
 182         Addr stateBits = xc->readPC() & PcModeMask;
 183         Addr jBit = (ULL(1) << PcJBitShift);
 184         Addr tBit = (ULL(1) << PcTBitShift);
 185         bool thumbEE = (stateBits == (tBit | jBit));
 186
 187         Addr newPc = (val & ~PcModeMask);
 188         if (thumbEE) {
 189             if (bits(newPc, 0)) {
 190                 warn("Bad thumbEE interworking branch address %#x.\n", newPc);
 191             } else {
 192                 newPc = newPc & ~mask(1);
 193             }
 194         } else {
 195             if (bits(newPc, 0)) {
 196                 stateBits = tBit;
 197                 newPc = newPc & ~mask(1);
 198             } else if (!bits(newPc, 1)) {
 199                 stateBits = 0;
 200             } else {
 201                 warn("Bad interworking branch address %#x.\n", newPc);
 202             }
 203         }
 204         newPc = newPc | stateBits;
 205         xc->setNextPC(newPc);
 206     }
 207
 208     // Perform an interworking branch in ARM mode, a regular branch
 209     // otherwise.
 210     template<class XC>
 211     static void
 212     setAIWNextPC(XC *xc, Addr val)
 213     {
 214         Addr stateBits = xc->readPC() & PcModeMask;
 215         Addr jBit = (ULL(1) << PcJBitShift);
 216         Addr tBit = (ULL(1) << PcTBitShift);
 217         if (!jBit && !tBit) {
 218             setIWNextPC(xc, val);
 219         } else {
 220             setNextPC(xc, val);
 221         }
 222     }
 223 };
 224 }
 225
 226 #endif //__ARCH_ARM_INSTS_STATICINST_HH__