src/arch/arm/insts/sve_mem.cc

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Giacomo Gabrielli
  38  */
  39
  40 #include "arch/arm/insts/sve_mem.hh"
  41
  42 namespace ArmISA
  43 {
  44
  45 std::string
  46 SveMemVecFillSpill::generateDisassembly(Addr pc,
  47                                         const SymbolTable *symtab) const
  48 {
  49     std::stringstream ss;
  50     printMnemonic(ss, "", false);
  51     printVecReg(ss, dest, true);
  52     ccprintf(ss, ", [");
  53     printIntReg(ss, base);
  54     if (imm != 0) {
  55         ccprintf(ss, ", #%d, mul vl", imm);
  56     }
  57     ccprintf(ss, "]");
  58     return ss.str();
  59 }
  60
  61 std::string
  62 SveMemPredFillSpill::generateDisassembly(Addr pc,
  63                                          const SymbolTable *symtab) const
  64 {
  65     std::stringstream ss;
  66     printMnemonic(ss, "", false);
  67     printVecPredReg(ss, dest);
  68     ccprintf(ss, ", [");
  69     printIntReg(ss, base);
  70     if (imm != 0) {
  71         ccprintf(ss, ", #%d, mul vl", imm);
  72     }
  73     ccprintf(ss, "]");
  74     return ss.str();
  75 }
  76
  77 std::string
  78 SveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  79 {
  80     // TODO: add suffix to transfer register and scaling factor (LSL #<x>)
  81     std::stringstream ss;
  82     printMnemonic(ss, "", false);
  83     ccprintf(ss, "{");
  84     printVecReg(ss, dest, true);
  85     ccprintf(ss, "}, ");
  86     printVecPredReg(ss, gp);
  87     ccprintf(ss, "/z, ");
  88     ccprintf(ss, ", [");
  89     printIntReg(ss, base);
  90     ccprintf(ss, ", ");
  91     printIntReg(ss, offset);
  92     ccprintf(ss, "]");
  93     return ss.str();
  94 }
  95
  96 std::string
  97 SveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const
  98 {
  99     // TODO: add suffix to transfer register
 100     std::stringstream ss;
 101     printMnemonic(ss, "", false);
 102     ccprintf(ss, "{");
 103     printVecReg(ss, dest, true);
 104     ccprintf(ss, "}, ");
 105     printVecPredReg(ss, gp);
 106     ccprintf(ss, "/z, ");
 107     ccprintf(ss, ", [");
 108     printIntReg(ss, base);
 109     if (imm != 0) {
 110         ccprintf(ss, ", #%d, mul vl", imm);
 111     }
 112     ccprintf(ss, "]");
 113     return ss.str();
 114 }
 115
 116 }  // namespace ArmISA