src/arch/arm/insts/sve_mem.hh

   1 /*
   2  * Copyright (c) 2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __ARCH_ARM_SVE_MEM_HH__
  39 #define __ARCH_ARM_SVE_MEM_HH__
  40
  41 #include "arch/arm/insts/static_inst.hh"
  42 #include "arch/arm/tlb.hh"
  43
  44 namespace ArmISA
  45 {
  46
  47 class SveMemVecFillSpill : public ArmStaticInst
  48 {
  49   protected:
  50     IntRegIndex dest;
  51     IntRegIndex base;
  52     uint64_t imm;
  53
  54     /// True if the base register is SP (used for SP alignment checking).
  55     bool baseIsSP;
  56
  57     unsigned memAccessFlags;
  58
  59     SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
  60                        OpClass __opClass, IntRegIndex _dest,
  61                        IntRegIndex _base, uint64_t _imm)
  62         : ArmStaticInst(mnem, _machInst, __opClass),
  63           dest(_dest), base(_base), imm(_imm),
  64           memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
  65     {
  66         baseIsSP = isSP(_base);
  67     }
  68
  69     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  70 };
  71
  72 class SveMemPredFillSpill : public ArmStaticInst
  73 {
  74   protected:
  75     IntRegIndex dest;
  76     IntRegIndex base;
  77     uint64_t imm;
  78
  79     /// True if the base register is SP (used for SP alignment checking).
  80     bool baseIsSP;
  81
  82     unsigned memAccessFlags;
  83
  84     SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
  85                         OpClass __opClass, IntRegIndex _dest,
  86                         IntRegIndex _base, uint64_t _imm)
  87         : ArmStaticInst(mnem, _machInst, __opClass),
  88           dest(_dest), base(_base), imm(_imm),
  89           memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
  90     {
  91         baseIsSP = isSP(_base);
  92     }
  93
  94     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
  95 };
  96
  97 class SveContigMemSS : public ArmStaticInst
  98 {
  99   protected:
 100     IntRegIndex dest;
 101     IntRegIndex gp;
 102     IntRegIndex base;
 103     IntRegIndex offset;
 104
 105     /// True if the base register is SP (used for SP alignment checking).
 106     bool baseIsSP;
 107
 108     unsigned memAccessFlags;
 109
 110     SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 111                    IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
 112                    IntRegIndex _offset)
 113         : ArmStaticInst(mnem, _machInst, __opClass),
 114           dest(_dest), gp(_gp), base(_base), offset(_offset),
 115           memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
 116     {
 117         baseIsSP = isSP(_base);
 118     }
 119
 120     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 121 };
 122
 123 class SveContigMemSI : public ArmStaticInst
 124 {
 125   protected:
 126     IntRegIndex dest;
 127     IntRegIndex gp;
 128     IntRegIndex base;
 129     uint64_t imm;
 130
 131     /// True if the base register is SP (used for SP alignment checking).
 132     bool baseIsSP;
 133
 134     unsigned memAccessFlags;
 135
 136     SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
 137                    IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
 138                    uint64_t _imm)
 139         : ArmStaticInst(mnem, _machInst, __opClass),
 140           dest(_dest), gp(_gp), base(_base), imm(_imm),
 141           memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
 142     {
 143         baseIsSP = isSP(_base);
 144     }
 145
 146     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 147 };
 148
 149 }  // namespace ArmISA
 150
 151 #endif  // __ARCH_ARM_SVE_MEM_HH__