src/arch/arm/insts/tme64.cc

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38  #include "arch/arm/insts/tme64.hh"
  39  #include "debug/ArmTme.hh"
  40
  41  #include <sstream>
  42
  43 using namespace ArmISA;
  44
  45 namespace ArmISAInst {
  46
  47 std::string
  48 TmeImmOp64::generateDisassembly(
  49     Addr pc, const Loader::SymbolTable *symtab) const
  50 {
  51     std::stringstream ss;
  52     printMnemonic(ss, "", false);
  53     ccprintf(ss, "#0x%x", imm);
  54     return ss.str();
  55 }
  56
  57 std::string
  58 TmeRegNone64::generateDisassembly(
  59     Addr pc, const Loader::SymbolTable *symtab) const
  60 {
  61     std::stringstream ss;
  62     printMnemonic(ss);
  63     printIntReg(ss, dest);
  64     return ss.str();
  65 }
  66
  67 std::string
  68 MicroTmeBasic64::generateDisassembly(
  69     Addr pc, const Loader::SymbolTable *symtab) const
  70 {
  71     std::stringstream ss;
  72     printMnemonic(ss);
  73     return ss.str();
  74 }
  75
  76 MicroTfence64::MicroTfence64(ExtMachInst machInst)
  77     : MicroTmeBasic64("utfence", machInst, MemReadOp)
  78 {
  79     _numSrcRegs = 0;
  80     _numDestRegs = 0;
  81     _numFPDestRegs = 0;
  82     _numVecDestRegs = 0;
  83     _numVecElemDestRegs = 0;
  84     _numIntDestRegs = 0;
  85     _numCCDestRegs = 0;
  86     flags[IsMicroop] = true;
  87     flags[IsReadBarrier] = true;
  88     flags[IsWriteBarrier] = true;
  89 }
  90
  91 Fault
  92 MicroTfence64::execute(
  93     ExecContext *xc, Trace::InstRecord *traceData) const
  94 {
  95     return NoFault;
  96 }
  97
  98 Fault
  99 MicroTfence64::initiateAcc(ExecContext *xc,
 100                            Trace::InstRecord *traceData) const
 101 {
 102     panic("tfence should not have memory semantics");
 103
 104     return NoFault;
 105 }
 106
 107 Fault
 108 MicroTfence64::completeAcc(PacketPtr pkt, ExecContext *xc,
 109                            Trace::InstRecord *traceData) const
 110 {
 111     panic("tfence should not have memory semantics");
 112
 113     return NoFault;
 114 }
 115
 116 Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
 117     : TmeRegNone64("tstart", machInst, MemReadOp, _dest)
 118 {
 119     _numSrcRegs = 0;
 120     _numDestRegs = 0;
 121     _numFPDestRegs = 0;
 122     _numVecDestRegs = 0;
 123     _numVecElemDestRegs = 0;
 124     _numIntDestRegs = 0;
 125     _numCCDestRegs = 0;
 126     setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
 127     _numIntDestRegs++;
 128     flags[IsHtmStart] = true;
 129     flags[IsInteger] = true;
 130     flags[IsLoad] = true;
 131     flags[IsMicroop] = true;
 132     flags[IsNonSpeculative] = true;
 133 }
 134
 135 Fault
 136 Tstart64::execute(
 137     ExecContext *xc, Trace::InstRecord *traceData) const
 138 {
 139     panic("TME is not supported with atomic memory");
 140
 141     return NoFault;
 142 }
 143
 144 Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
 145     : TmeRegNone64("ttest", machInst, MemReadOp, _dest)
 146 {
 147     _numSrcRegs = 0;
 148     _numDestRegs = 0;
 149     _numFPDestRegs = 0;
 150     _numVecDestRegs = 0;
 151     _numVecElemDestRegs = 0;
 152     _numIntDestRegs = 0;
 153     _numCCDestRegs = 0;
 154     setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
 155     _numIntDestRegs++;
 156     flags[IsInteger] = true;
 157     flags[IsMicroop] = true;
 158 }
 159
 160 Tcancel64::Tcancel64(ExtMachInst machInst, uint64_t _imm)
 161     : TmeImmOp64("tcancel", machInst, MemReadOp, _imm)
 162 {
 163     _numSrcRegs = 0;
 164     _numDestRegs = 0;
 165     _numFPDestRegs = 0;
 166     _numVecDestRegs = 0;
 167     _numVecElemDestRegs = 0;
 168     _numIntDestRegs = 0;
 169     _numCCDestRegs = 0;
 170     flags[IsLoad] = true;
 171     flags[IsMicroop] = true;
 172     flags[IsNonSpeculative] = true;
 173     flags[IsHtmCancel] = true;
 174 }
 175
 176 Fault
 177 Tcancel64::execute(
 178     ExecContext *xc, Trace::InstRecord *traceData) const
 179 {
 180     panic("TME is not supported with atomic memory");
 181
 182     return NoFault;
 183 }
 184
 185 MacroTmeOp::MacroTmeOp(const char *mnem,
 186                        ExtMachInst _machInst,
 187                        OpClass __opClass) :
 188   PredMacroOp(mnem, machInst, __opClass) {
 189     _numSrcRegs = 0;
 190     _numDestRegs = 0;
 191     _numFPDestRegs = 0;
 192     _numVecDestRegs = 0;
 193     _numVecElemDestRegs = 0;
 194     _numIntDestRegs = 0;
 195     _numCCDestRegs = 0;
 196
 197     numMicroops = 0;
 198     microOps = nullptr;
 199 }
 200
 201 MicroTcommit64::MicroTcommit64(ExtMachInst machInst)
 202     : MicroTmeBasic64("utcommit", machInst, MemReadOp)
 203 {
 204     _numSrcRegs = 0;
 205     _numDestRegs = 0;
 206     _numFPDestRegs = 0;
 207     _numVecDestRegs = 0;
 208     _numVecElemDestRegs = 0;
 209     _numIntDestRegs = 0;
 210     _numCCDestRegs = 0;
 211     flags[IsHtmStop] = true;
 212     flags[IsLoad] = true;
 213     flags[IsMicroop] = true;
 214     flags[IsNonSpeculative] = true;
 215 }
 216
 217 Fault
 218 MicroTcommit64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 219 {
 220     panic("TME is not supported with atomic memory");
 221
 222     return NoFault;
 223 }
 224
 225 Tcommit64::Tcommit64(ExtMachInst _machInst) :
 226                      MacroTmeOp("tcommit", machInst, MemReadOp)
 227 {
 228     numMicroops = 2;
 229     microOps = new StaticInstPtr[numMicroops];
 230
 231     microOps[0] = new ArmISAInst::MicroTfence64(_machInst);
 232     microOps[0]->setDelayedCommit();
 233     microOps[0]->setFirstMicroop();
 234
 235     microOps[1] = new ArmISAInst::MicroTcommit64(_machInst);
 236     microOps[1]->setDelayedCommit();
 237     microOps[1]->setLastMicroop();
 238 }
 239
 240 } // namespace