src/arch/arm/interrupts.cc

   1 /*
   2  * Copyright (c) 2009, 2012-2013, 2016, 2019 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/interrupts.hh"
  39
  40 #include "arch/arm/system.hh"
  41
  42 ArmISA::Interrupts *
  43 ArmInterruptsParams::create()
  44 {
  45     return new ArmISA::Interrupts(this);
  46 }
  47
  48 bool
  49 ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
  50 {
  51     // Table G1-17~19 of ARM V8 ARM
  52     InterruptMask mask;
  53     bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
  54
  55     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
  56     SCR scr;
  57     HCR hcr;
  58     hcr = tc->readMiscReg(MISCREG_HCR);
  59     ExceptionLevel el = currEL(tc);
  60     bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
  61
  62     if (!highest_el_is_64)
  63         scr = tc->readMiscReg(MISCREG_SCR);
  64     else
  65         scr = tc->readMiscReg(MISCREG_SCR_EL3);
  66
  67     bool is_secure = inSecureState(tc);
  68
  69     switch(int_type) {
  70       case INT_FIQ:
  71         cpsr_mask_bit = cpsr.f;
  72         scr_routing_bit = scr.fiq;
  73         scr_fwaw_bit = scr.fw;
  74         hcr_mask_override_bit = hcr.fmo;
  75         break;
  76       case INT_IRQ:
  77         cpsr_mask_bit = cpsr.i;
  78         scr_routing_bit = scr.irq;
  79         scr_fwaw_bit = 1;
  80         hcr_mask_override_bit = hcr.imo;
  81         break;
  82       case INT_ABT:
  83         cpsr_mask_bit = cpsr.a;
  84         scr_routing_bit = scr.ea;
  85         scr_fwaw_bit = scr.aw;
  86         hcr_mask_override_bit = hcr.amo;
  87         break;
  88       default:
  89         panic("Unhandled interrupt type!");
  90     }
  91
  92     if (hcr.tge)
  93         hcr_mask_override_bit = 1;
  94
  95     if (!highest_el_is_64) {
  96         // AArch32
  97         if (!scr_routing_bit) {
  98             // SCR IRQ == 0
  99             if (!hcr_mask_override_bit)
 100                 mask = INT_MASK_M;
 101             else {
 102                 if (!is_secure && (el == EL0 || el == EL1))
 103                     mask = INT_MASK_T;
 104                 else
 105                     mask = INT_MASK_M;
 106             }
 107         } else {
 108             // SCR IRQ == 1
 109             if ((!is_secure) &&
 110                 (hcr_mask_override_bit ||
 111                     (!scr_fwaw_bit && !hcr_mask_override_bit)))
 112                 mask = INT_MASK_T;
 113             else
 114                 mask = INT_MASK_M;
 115         }
 116     } else {
 117         // AArch64
 118         if (!scr_routing_bit) {
 119             // SCR IRQ == 0
 120             if (!scr.rw) {
 121                 // SCR RW == 0
 122                 if (!hcr_mask_override_bit) {
 123                     if (el == EL3)
 124                         mask = INT_MASK_P;
 125                     else
 126                         mask = INT_MASK_M;
 127                 } else {
 128                     if (el == EL3)
 129                         mask = INT_MASK_T;
 130                     else if (is_secure || el == EL2)
 131                         mask = INT_MASK_M;
 132                     else
 133                         mask = INT_MASK_T;
 134                 }
 135             } else {
 136                 // SCR RW == 1
 137                 if (!hcr_mask_override_bit) {
 138                     if (el == EL3 || el == EL2)
 139                         mask = INT_MASK_P;
 140                     else
 141                         mask = INT_MASK_M;
 142                 } else {
 143                     if (el == EL3)
 144                         mask = INT_MASK_P;
 145                     else if (is_secure || el == EL2)
 146                         mask = INT_MASK_M;
 147                     else
 148                         mask = INT_MASK_T;
 149                 }
 150             }
 151         } else {
 152             // SCR IRQ == 1
 153             if (el == EL3)
 154                 mask = INT_MASK_M;
 155             else
 156                 mask = INT_MASK_T;
 157         }
 158     }
 159
 160     return ((mask == INT_MASK_T) ||
 161             ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
 162             (mask != INT_MASK_P);
 163 }
 164