src/arch/arm/interrupts.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #ifndef __ARCH_ARM_INTERRUPT_HH__
  44 #define __ARCH_ARM_INTERRUPT_HH__
  45
  46 #include "arch/arm/faults.hh"
  47 #include "arch/arm/isa_traits.hh"
  48 #include "arch/arm/miscregs.hh"
  49 #include "arch/arm/registers.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "params/ArmInterrupts.hh"
  52 #include "sim/sim_object.hh"
  53
  54 namespace ArmISA
  55 {
  56
  57 class Interrupts : public SimObject
  58 {
  59   private:
  60     BaseCPU * cpu;
  61
  62     bool interrupts[NumInterruptTypes];
  63     uint64_t intStatus;
  64
  65   public:
  66
  67     void
  68     setCPU(BaseCPU * _cpu)
  69     {
  70         cpu = _cpu;
  71     }
  72
  73     typedef ArmInterruptsParams Params;
  74
  75     const Params *
  76     params() const
  77     {
  78         return dynamic_cast<const Params *>(_params);
  79     }
  80
  81     Interrupts(Params * p) : SimObject(p), cpu(NULL)
  82     {
  83         clearAll();
  84     }
  85
  86
  87     void
  88     post(int int_num, int index)
  89     {
  90         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
  91
  92         if (int_num < 0 || int_num >= NumInterruptTypes)
  93             panic("int_num out of bounds\n");
  94
  95         if (index != 0)
  96             panic("No support for other interrupt indexes\n");
  97
  98         interrupts[int_num] = true;
  99         intStatus |= ULL(1) << int_num;
 100     }
 101
 102     void
 103     clear(int int_num, int index)
 104     {
 105         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 106
 107         if (int_num < 0 || int_num >= NumInterruptTypes)
 108             panic("int_num out of bounds\n");
 109
 110         if (index != 0)
 111             panic("No support for other interrupt indexes\n");
 112
 113         interrupts[int_num] = false;
 114         intStatus &= ~(ULL(1) << int_num);
 115
 116     }
 117
 118     void
 119     clearAll()
 120     {
 121         DPRINTF(Interrupt, "Interrupts all cleared\n");
 122         intStatus = 0;
 123         memset(interrupts, 0, sizeof(interrupts));
 124     }
 125
 126     bool
 127     checkInterrupts(ThreadContext *tc) const
 128     {
 129         if (!intStatus)
 130             return false;
 131
 132         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 133
 134         return ((interrupts[INT_IRQ] && !cpsr.i) ||
 135                 (interrupts[INT_FIQ] && !cpsr.f) ||
 136                 (interrupts[INT_ABT] && !cpsr.a) ||
 137                 (interrupts[INT_RST]));
 138     }
 139
 140     Fault
 141     getInterrupt(ThreadContext *tc)
 142     {
 143         if (!intStatus)
 144             return NoFault;
 145
 146         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 147
 148         if (interrupts[INT_IRQ] && !cpsr.i)
 149             return new Interrupt;
 150         if (interrupts[INT_FIQ] && !cpsr.f)
 151             return new FastInterrupt;
 152         if (interrupts[INT_ABT] && !cpsr.a)
 153             return new DataAbort(0, false, 0,
 154                     ArmFault::AsynchronousExternalAbort);
 155         if (interrupts[INT_RST])
 156            return new Reset;
 157
 158         panic("intStatus and interrupts not in sync\n");
 159     }
 160
 161     void
 162     updateIntrInfo(ThreadContext *tc)
 163     {
 164         ; // nothing to do
 165     }
 166
 167     void
 168     serialize(std::ostream &os)
 169     {
 170         SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
 171         SERIALIZE_SCALAR(intStatus);
 172     }
 173
 174     void
 175     unserialize(Checkpoint *cp, const std::string &section)
 176     {
 177         UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
 178         UNSERIALIZE_SCALAR(intStatus);
 179     }
 180 };
 181 } // namespace ARM_ISA
 182
 183 #endif // __ARCH_ARM_INTERRUPT_HH__