2 * Copyright (c) 2010,2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #ifndef __ARCH_ARM_INTERRUPT_HH__
44 #define __ARCH_ARM_INTERRUPT_HH__
46 #include "arch/arm/faults.hh"
47 #include "arch/arm/isa_traits.hh"
48 #include "arch/arm/miscregs.hh"
49 #include "arch/arm/registers.hh"
50 #include "cpu/thread_context.hh"
51 #include "debug/Interrupt.hh"
52 #include "params/ArmInterrupts.hh"
53 #include "sim/sim_object.hh"
58 class Interrupts : public SimObject
63 bool interrupts[NumInterruptTypes];
69 setCPU(BaseCPU * _cpu)
74 typedef ArmInterruptsParams Params;
79 return dynamic_cast<const Params *>(_params);
82 Interrupts(Params * p) : SimObject(p), cpu(NULL)
89 post(int int_num, int index)
91 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
93 if (int_num < 0 || int_num >= NumInterruptTypes)
94 panic("int_num out of bounds\n");
97 panic("No support for other interrupt indexes\n");
99 interrupts[int_num] = true;
100 intStatus |= ULL(1) << int_num;
104 clear(int int_num, int index)
106 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
108 if (int_num < 0 || int_num >= NumInterruptTypes)
109 panic("int_num out of bounds\n");
112 panic("No support for other interrupt indexes\n");
114 interrupts[int_num] = false;
115 intStatus &= ~(ULL(1) << int_num);
121 DPRINTF(Interrupt, "Interrupts all cleared\n");
123 memset(interrupts, 0, sizeof(interrupts));
127 checkInterrupts(ThreadContext *tc) const
132 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
134 return ((interrupts[INT_IRQ] && !cpsr.i) ||
135 (interrupts[INT_FIQ] && !cpsr.f) ||
136 (interrupts[INT_ABT] && !cpsr.a) ||
137 (interrupts[INT_RST]) ||
138 (interrupts[INT_SEV]));
142 * Check the raw interrupt state.
143 * This function is used to check if a wfi operation should sleep. If there
144 * is an interrupt pending, even if it's masked, wfi doesn't sleep.
145 * @return any interrupts pending
154 * Check the state of a particular interrupt, ignoring CPSR masks.
156 * This method is primarily used when running the target CPU in a
157 * hardware VM (e.g., KVM) to check if interrupts should be
158 * delivered upon guest entry.
160 * @param interrupt Interrupt type to check the state of.
161 * @return true if the interrupt is asserted, false otherwise.
164 checkRaw(InterruptTypes interrupt) const
166 if (interrupt >= NumInterruptTypes)
167 panic("Interrupt number out of range.\n");
169 return interrupts[interrupt];
173 getInterrupt(ThreadContext *tc)
178 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
180 if (interrupts[INT_IRQ] && !cpsr.i)
181 return new Interrupt;
182 if (interrupts[INT_FIQ] && !cpsr.f)
183 return new FastInterrupt;
184 if (interrupts[INT_ABT] && !cpsr.a)
185 return new DataAbort(0, false, 0,
186 ArmFault::AsynchronousExternalAbort);
187 if (interrupts[INT_RST])
189 if (interrupts[INT_SEV])
192 panic("intStatus and interrupts not in sync\n");
196 updateIntrInfo(ThreadContext *tc)
202 serialize(std::ostream &os)
204 SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
205 SERIALIZE_SCALAR(intStatus);
209 unserialize(Checkpoint *cp, const std::string §ion)
211 UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
212 UNSERIALIZE_SCALAR(intStatus);
215 } // namespace ARM_ISA
217 #endif // __ARCH_ARM_INTERRUPT_HH__