src/arch/arm/interrupts.hh

   1 /*
   2  * Copyright (c) 2010,2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #ifndef __ARCH_ARM_INTERRUPT_HH__
  44 #define __ARCH_ARM_INTERRUPT_HH__
  45
  46 #include "arch/arm/faults.hh"
  47 #include "arch/arm/isa_traits.hh"
  48 #include "arch/arm/miscregs.hh"
  49 #include "arch/arm/registers.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "debug/Interrupt.hh"
  52 #include "params/ArmInterrupts.hh"
  53 #include "sim/sim_object.hh"
  54
  55 namespace ArmISA
  56 {
  57
  58 class Interrupts : public SimObject
  59 {
  60   private:
  61     BaseCPU * cpu;
  62
  63     bool interrupts[NumInterruptTypes];
  64     uint64_t intStatus;
  65
  66   public:
  67
  68     void
  69     setCPU(BaseCPU * _cpu)
  70     {
  71         cpu = _cpu;
  72     }
  73
  74     typedef ArmInterruptsParams Params;
  75
  76     const Params *
  77     params() const
  78     {
  79         return dynamic_cast<const Params *>(_params);
  80     }
  81
  82     Interrupts(Params * p) : SimObject(p), cpu(NULL)
  83     {
  84         clearAll();
  85     }
  86
  87
  88     void
  89     post(int int_num, int index)
  90     {
  91         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
  92
  93         if (int_num < 0 || int_num >= NumInterruptTypes)
  94             panic("int_num out of bounds\n");
  95
  96         if (index != 0)
  97             panic("No support for other interrupt indexes\n");
  98
  99         interrupts[int_num] = true;
 100         intStatus |= ULL(1) << int_num;
 101     }
 102
 103     void
 104     clear(int int_num, int index)
 105     {
 106         DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 107
 108         if (int_num < 0 || int_num >= NumInterruptTypes)
 109             panic("int_num out of bounds\n");
 110
 111         if (index != 0)
 112             panic("No support for other interrupt indexes\n");
 113
 114         interrupts[int_num] = false;
 115         intStatus &= ~(ULL(1) << int_num);
 116     }
 117
 118     void
 119     clearAll()
 120     {
 121         DPRINTF(Interrupt, "Interrupts all cleared\n");
 122         intStatus = 0;
 123         memset(interrupts, 0, sizeof(interrupts));
 124     }
 125
 126     bool
 127     checkInterrupts(ThreadContext *tc) const
 128     {
 129         if (!intStatus)
 130             return false;
 131
 132         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 133
 134         return ((interrupts[INT_IRQ] && !cpsr.i) ||
 135                 (interrupts[INT_FIQ] && !cpsr.f) ||
 136                 (interrupts[INT_ABT] && !cpsr.a) ||
 137                 (interrupts[INT_RST]) ||
 138                 (interrupts[INT_SEV]));
 139     }
 140
 141     /**
 142      * Check the raw interrupt state.
 143      * This function is used to check if a wfi operation should sleep. If there
 144      * is an interrupt pending, even if it's masked, wfi doesn't sleep.
 145      * @return any interrupts pending
 146      */
 147     bool
 148     checkRaw() const
 149     {
 150         return intStatus;
 151     }
 152
 153     /**
 154      * Check the state of a particular interrupt, ignoring CPSR masks.
 155      *
 156      * This method is primarily used when running the target CPU in a
 157      * hardware VM (e.g., KVM) to check if interrupts should be
 158      * delivered upon guest entry.
 159      *
 160      * @param interrupt Interrupt type to check the state of.
 161      * @return true if the interrupt is asserted, false otherwise.
 162      */
 163     bool
 164     checkRaw(InterruptTypes interrupt) const
 165     {
 166         if (interrupt >= NumInterruptTypes)
 167             panic("Interrupt number out of range.\n");
 168
 169         return interrupts[interrupt];
 170     }
 171
 172     Fault
 173     getInterrupt(ThreadContext *tc)
 174     {
 175         if (!intStatus)
 176             return NoFault;
 177
 178         CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 179
 180         if (interrupts[INT_IRQ] && !cpsr.i)
 181             return new Interrupt;
 182         if (interrupts[INT_FIQ] && !cpsr.f)
 183             return new FastInterrupt;
 184         if (interrupts[INT_ABT] && !cpsr.a)
 185             return new DataAbort(0, false, 0,
 186                     ArmFault::AsynchronousExternalAbort);
 187         if (interrupts[INT_RST])
 188            return new Reset;
 189         if (interrupts[INT_SEV])
 190            return new ArmSev;
 191
 192         panic("intStatus and interrupts not in sync\n");
 193     }
 194
 195     void
 196     updateIntrInfo(ThreadContext *tc)
 197     {
 198         ; // nothing to do
 199     }
 200
 201     void
 202     serialize(std::ostream &os)
 203     {
 204         SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
 205         SERIALIZE_SCALAR(intStatus);
 206     }
 207
 208     void
 209     unserialize(Checkpoint *cp, const std::string &section)
 210     {
 211         UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
 212         UNSERIALIZE_SCALAR(intStatus);
 213     }
 214 };
 215 } // namespace ARM_ISA
 216
 217 #endif // __ARCH_ARM_INTERRUPT_HH__