src/arch/arm/interrupts.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2009 ARM Limited
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_ARM_INTERRUPT_HH__
  33 #define __ARCH_ARM_INTERRUPT_HH__
  34
  35 #include "arch/arm/faults.hh"
  36 #include "arch/arm/isa_traits.hh"
  37 #include "arch/arm/registers.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "params/ArmInterrupts.hh"
  40 #include "sim/sim_object.hh"
  41
  42 namespace ArmISA
  43 {
  44
  45 class Interrupts : public SimObject
  46 {
  47   private:
  48     BaseCPU * cpu;
  49
  50     uint64_t intStatus;
  51
  52   public:
  53
  54     void
  55     setCPU(BaseCPU * _cpu)
  56     {
  57         cpu = _cpu;
  58     }
  59
  60     typedef ArmInterruptsParams Params;
  61
  62     const Params *
  63     params() const
  64     {
  65         return dynamic_cast<const Params *>(_params);
  66     }
  67
  68     Interrupts(Params * p) : SimObject(p), cpu(NULL)
  69     {
  70         clearAll();
  71     }
  72
  73
  74     void
  75     post(int int_num, int index)
  76     {
  77     }
  78
  79     void
  80     clear(int int_num, int index)
  81     {
  82     }
  83
  84     void
  85     clearAll()
  86     {
  87         intStatus = 0;
  88     }
  89
  90     bool
  91     checkInterrupts(ThreadContext *tc) const
  92     {
  93         return intStatus;
  94     }
  95
  96     Fault
  97     getInterrupt(ThreadContext *tc)
  98     {
  99         warn_once("ARM  Interrupts not handled\n");
 100         return NoFault;
 101     }
 102
 103     void
 104     updateIntrInfo(ThreadContext *tc)
 105     {
 106
 107     }
 108
 109     void
 110     serialize(std::ostream &os)
 111     {
 112     }
 113
 114     void
 115     unserialize(Checkpoint *cp, const std::string &section)
 116     {
 117     }
 118 };
 119 } // namespace ARM_ISA
 120
 121 #endif // __ARCH_ARM_INTERRUPT_HH__