src/arch/arm/intregs.hh

   1 /*
   2  * Copyright (c) 2010-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include <cassert>
  42
  43 #ifndef __ARCH_ARM_INTREGS_HH__
  44 #define __ARCH_ARM_INTREGS_HH__
  45
  46 #include "arch/arm/types.hh"
  47
  48 namespace ArmISA
  49 {
  50
  51 enum IntRegIndex
  52 {
  53     /* All the unique register indices. */
  54     INTREG_R0,
  55     INTREG_R1,
  56     INTREG_R2,
  57     INTREG_R3,
  58     INTREG_R4,
  59     INTREG_R5,
  60     INTREG_R6,
  61     INTREG_R7,
  62     INTREG_R8,
  63     INTREG_R9,
  64     INTREG_R10,
  65     INTREG_R11,
  66     INTREG_R12,
  67     INTREG_R13,
  68     INTREG_SP = INTREG_R13,
  69     INTREG_R14,
  70     INTREG_LR = INTREG_R14,
  71     INTREG_R15,
  72     INTREG_PC = INTREG_R15,
  73
  74     INTREG_R13_SVC,
  75     INTREG_SP_SVC = INTREG_R13_SVC,
  76     INTREG_R14_SVC,
  77     INTREG_LR_SVC = INTREG_R14_SVC,
  78
  79     INTREG_R13_MON,
  80     INTREG_SP_MON = INTREG_R13_MON,
  81     INTREG_R14_MON,
  82     INTREG_LR_MON = INTREG_R14_MON,
  83
  84     INTREG_R13_HYP,
  85     INTREG_SP_HYP = INTREG_R13_HYP,
  86
  87     INTREG_R13_ABT,
  88     INTREG_SP_ABT = INTREG_R13_ABT,
  89     INTREG_R14_ABT,
  90     INTREG_LR_ABT = INTREG_R14_ABT,
  91
  92     INTREG_R13_UND,
  93     INTREG_SP_UND = INTREG_R13_UND,
  94     INTREG_R14_UND,
  95     INTREG_LR_UND = INTREG_R14_UND,
  96
  97     INTREG_R13_IRQ,
  98     INTREG_SP_IRQ = INTREG_R13_IRQ,
  99     INTREG_R14_IRQ,
 100     INTREG_LR_IRQ = INTREG_R14_IRQ,
 101
 102     INTREG_R8_FIQ,
 103     INTREG_R9_FIQ,
 104     INTREG_R10_FIQ,
 105     INTREG_R11_FIQ,
 106     INTREG_R12_FIQ,
 107     INTREG_R13_FIQ,
 108     INTREG_SP_FIQ = INTREG_R13_FIQ,
 109     INTREG_R14_FIQ,
 110     INTREG_LR_FIQ = INTREG_R14_FIQ,
 111
 112     INTREG_ZERO,
 113     INTREG_UREG0,
 114     INTREG_UREG1,
 115     INTREG_UREG2,
 116     INTREG_DUMMY, // Dummy reg used to throw away int reg results
 117
 118     INTREG_SP0,
 119     INTREG_SP1,
 120     INTREG_SP2,
 121     INTREG_SP3,
 122
 123     NUM_INTREGS,
 124     NUM_ARCH_INTREGS = 32,
 125
 126     /* AArch64 registers */
 127     INTREG_X0 = 0,
 128     INTREG_X1,
 129     INTREG_X2,
 130     INTREG_X3,
 131     INTREG_X4,
 132     INTREG_X5,
 133     INTREG_X6,
 134     INTREG_X7,
 135     INTREG_X8,
 136     INTREG_X9,
 137     INTREG_X10,
 138     INTREG_X11,
 139     INTREG_X12,
 140     INTREG_X13,
 141     INTREG_X14,
 142     INTREG_X15,
 143     INTREG_X16,
 144     INTREG_X17,
 145     INTREG_X18,
 146     INTREG_X19,
 147     INTREG_X20,
 148     INTREG_X21,
 149     INTREG_X22,
 150     INTREG_X23,
 151     INTREG_X24,
 152     INTREG_X25,
 153     INTREG_X26,
 154     INTREG_X27,
 155     INTREG_X28,
 156     INTREG_X29,
 157     INTREG_X30,
 158     INTREG_X31,
 159
 160     INTREG_SPX = NUM_INTREGS,
 161
 162     /* All the aliased indexes. */
 163
 164     /* USR mode */
 165     INTREG_R0_USR = INTREG_R0,
 166     INTREG_R1_USR = INTREG_R1,
 167     INTREG_R2_USR = INTREG_R2,
 168     INTREG_R3_USR = INTREG_R3,
 169     INTREG_R4_USR = INTREG_R4,
 170     INTREG_R5_USR = INTREG_R5,
 171     INTREG_R6_USR = INTREG_R6,
 172     INTREG_R7_USR = INTREG_R7,
 173     INTREG_R8_USR = INTREG_R8,
 174     INTREG_R9_USR = INTREG_R9,
 175     INTREG_R10_USR = INTREG_R10,
 176     INTREG_R11_USR = INTREG_R11,
 177     INTREG_R12_USR = INTREG_R12,
 178     INTREG_R13_USR = INTREG_R13,
 179     INTREG_SP_USR = INTREG_SP,
 180     INTREG_R14_USR = INTREG_R14,
 181     INTREG_LR_USR = INTREG_LR,
 182     INTREG_R15_USR = INTREG_R15,
 183     INTREG_PC_USR = INTREG_PC,
 184
 185     /* SVC mode */
 186     INTREG_R0_SVC = INTREG_R0,
 187     INTREG_R1_SVC = INTREG_R1,
 188     INTREG_R2_SVC = INTREG_R2,
 189     INTREG_R3_SVC = INTREG_R3,
 190     INTREG_R4_SVC = INTREG_R4,
 191     INTREG_R5_SVC = INTREG_R5,
 192     INTREG_R6_SVC = INTREG_R6,
 193     INTREG_R7_SVC = INTREG_R7,
 194     INTREG_R8_SVC = INTREG_R8,
 195     INTREG_R9_SVC = INTREG_R9,
 196     INTREG_R10_SVC = INTREG_R10,
 197     INTREG_R11_SVC = INTREG_R11,
 198     INTREG_R12_SVC = INTREG_R12,
 199     INTREG_PC_SVC = INTREG_PC,
 200     INTREG_R15_SVC = INTREG_R15,
 201
 202     /* MON mode */
 203     INTREG_R0_MON = INTREG_R0,
 204     INTREG_R1_MON = INTREG_R1,
 205     INTREG_R2_MON = INTREG_R2,
 206     INTREG_R3_MON = INTREG_R3,
 207     INTREG_R4_MON = INTREG_R4,
 208     INTREG_R5_MON = INTREG_R5,
 209     INTREG_R6_MON = INTREG_R6,
 210     INTREG_R7_MON = INTREG_R7,
 211     INTREG_R8_MON = INTREG_R8,
 212     INTREG_R9_MON = INTREG_R9,
 213     INTREG_R10_MON = INTREG_R10,
 214     INTREG_R11_MON = INTREG_R11,
 215     INTREG_R12_MON = INTREG_R12,
 216     INTREG_PC_MON = INTREG_PC,
 217     INTREG_R15_MON = INTREG_R15,
 218
 219     /* ABT mode */
 220     INTREG_R0_ABT = INTREG_R0,
 221     INTREG_R1_ABT = INTREG_R1,
 222     INTREG_R2_ABT = INTREG_R2,
 223     INTREG_R3_ABT = INTREG_R3,
 224     INTREG_R4_ABT = INTREG_R4,
 225     INTREG_R5_ABT = INTREG_R5,
 226     INTREG_R6_ABT = INTREG_R6,
 227     INTREG_R7_ABT = INTREG_R7,
 228     INTREG_R8_ABT = INTREG_R8,
 229     INTREG_R9_ABT = INTREG_R9,
 230     INTREG_R10_ABT = INTREG_R10,
 231     INTREG_R11_ABT = INTREG_R11,
 232     INTREG_R12_ABT = INTREG_R12,
 233     INTREG_PC_ABT = INTREG_PC,
 234     INTREG_R15_ABT = INTREG_R15,
 235
 236     /* HYP mode */
 237     INTREG_R0_HYP = INTREG_R0,
 238     INTREG_R1_HYP = INTREG_R1,
 239     INTREG_R2_HYP = INTREG_R2,
 240     INTREG_R3_HYP = INTREG_R3,
 241     INTREG_R4_HYP = INTREG_R4,
 242     INTREG_R5_HYP = INTREG_R5,
 243     INTREG_R6_HYP = INTREG_R6,
 244     INTREG_R7_HYP = INTREG_R7,
 245     INTREG_R8_HYP = INTREG_R8,
 246     INTREG_R9_HYP = INTREG_R9,
 247     INTREG_R10_HYP = INTREG_R10,
 248     INTREG_R11_HYP = INTREG_R11,
 249     INTREG_R12_HYP = INTREG_R12,
 250     INTREG_LR_HYP = INTREG_LR,
 251     INTREG_R14_HYP = INTREG_R14,
 252     INTREG_PC_HYP = INTREG_PC,
 253     INTREG_R15_HYP = INTREG_R15,
 254
 255     /* UND mode */
 256     INTREG_R0_UND = INTREG_R0,
 257     INTREG_R1_UND = INTREG_R1,
 258     INTREG_R2_UND = INTREG_R2,
 259     INTREG_R3_UND = INTREG_R3,
 260     INTREG_R4_UND = INTREG_R4,
 261     INTREG_R5_UND = INTREG_R5,
 262     INTREG_R6_UND = INTREG_R6,
 263     INTREG_R7_UND = INTREG_R7,
 264     INTREG_R8_UND = INTREG_R8,
 265     INTREG_R9_UND = INTREG_R9,
 266     INTREG_R10_UND = INTREG_R10,
 267     INTREG_R11_UND = INTREG_R11,
 268     INTREG_R12_UND = INTREG_R12,
 269     INTREG_PC_UND = INTREG_PC,
 270     INTREG_R15_UND = INTREG_R15,
 271
 272     /* IRQ mode */
 273     INTREG_R0_IRQ = INTREG_R0,
 274     INTREG_R1_IRQ = INTREG_R1,
 275     INTREG_R2_IRQ = INTREG_R2,
 276     INTREG_R3_IRQ = INTREG_R3,
 277     INTREG_R4_IRQ = INTREG_R4,
 278     INTREG_R5_IRQ = INTREG_R5,
 279     INTREG_R6_IRQ = INTREG_R6,
 280     INTREG_R7_IRQ = INTREG_R7,
 281     INTREG_R8_IRQ = INTREG_R8,
 282     INTREG_R9_IRQ = INTREG_R9,
 283     INTREG_R10_IRQ = INTREG_R10,
 284     INTREG_R11_IRQ = INTREG_R11,
 285     INTREG_R12_IRQ = INTREG_R12,
 286     INTREG_PC_IRQ = INTREG_PC,
 287     INTREG_R15_IRQ = INTREG_R15,
 288
 289     /* FIQ mode */
 290     INTREG_R0_FIQ = INTREG_R0,
 291     INTREG_R1_FIQ = INTREG_R1,
 292     INTREG_R2_FIQ = INTREG_R2,
 293     INTREG_R3_FIQ = INTREG_R3,
 294     INTREG_R4_FIQ = INTREG_R4,
 295     INTREG_R5_FIQ = INTREG_R5,
 296     INTREG_R6_FIQ = INTREG_R6,
 297     INTREG_R7_FIQ = INTREG_R7,
 298     INTREG_PC_FIQ = INTREG_PC,
 299     INTREG_R15_FIQ = INTREG_R15
 300 };
 301
 302 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
 303
 304 const IntRegMap IntReg64Map = {
 305     INTREG_R0,      INTREG_R1,      INTREG_R2,      INTREG_R3,
 306     INTREG_R4,      INTREG_R5,      INTREG_R6,      INTREG_R7,
 307     INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
 308     INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
 309     INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
 310     INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
 311     INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
 312     INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
 313 };
 314
 315 const IntRegMap IntRegUsrMap = {
 316     INTREG_R0_USR,  INTREG_R1_USR,  INTREG_R2_USR,  INTREG_R3_USR,
 317     INTREG_R4_USR,  INTREG_R5_USR,  INTREG_R6_USR,  INTREG_R7_USR,
 318     INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
 319     INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
 320     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 321     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 322     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 323     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 324 };
 325
 326 static inline IntRegIndex
 327 INTREG_USR(unsigned index)
 328 {
 329     assert(index < NUM_ARCH_INTREGS);
 330     return IntRegUsrMap[index];
 331 }
 332
 333 const IntRegMap IntRegHypMap = {
 334     INTREG_R0_HYP,  INTREG_R1_HYP,  INTREG_R2_HYP,  INTREG_R3_HYP,
 335     INTREG_R4_HYP,  INTREG_R5_HYP,  INTREG_R6_HYP,  INTREG_R7_HYP,
 336     INTREG_R8_HYP,  INTREG_R9_HYP,  INTREG_R10_HYP, INTREG_R11_HYP,
 337     INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
 338     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 339     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 340     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 341     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 342 };
 343
 344 static inline IntRegIndex
 345 INTREG_HYP(unsigned index)
 346 {
 347     assert(index < NUM_ARCH_INTREGS);
 348     return IntRegHypMap[index];
 349 }
 350
 351 const IntRegMap IntRegSvcMap = {
 352     INTREG_R0_SVC,  INTREG_R1_SVC,  INTREG_R2_SVC,  INTREG_R3_SVC,
 353     INTREG_R4_SVC,  INTREG_R5_SVC,  INTREG_R6_SVC,  INTREG_R7_SVC,
 354     INTREG_R8_SVC,  INTREG_R9_SVC,  INTREG_R10_SVC, INTREG_R11_SVC,
 355     INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
 356     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 357     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 358     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 359     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 360 };
 361
 362 static inline IntRegIndex
 363 INTREG_SVC(unsigned index)
 364 {
 365     assert(index < NUM_ARCH_INTREGS);
 366     return IntRegSvcMap[index];
 367 }
 368
 369 const IntRegMap IntRegMonMap = {
 370     INTREG_R0_MON,  INTREG_R1_MON,  INTREG_R2_MON,  INTREG_R3_MON,
 371     INTREG_R4_MON,  INTREG_R5_MON,  INTREG_R6_MON,  INTREG_R7_MON,
 372     INTREG_R8_MON,  INTREG_R9_MON,  INTREG_R10_MON, INTREG_R11_MON,
 373     INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
 374     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 375     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 376     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 377     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 378 };
 379
 380 static inline IntRegIndex
 381 INTREG_MON(unsigned index)
 382 {
 383     assert(index < NUM_ARCH_INTREGS);
 384     return IntRegMonMap[index];
 385 }
 386
 387 const IntRegMap IntRegAbtMap = {
 388     INTREG_R0_ABT,  INTREG_R1_ABT,  INTREG_R2_ABT,  INTREG_R3_ABT,
 389     INTREG_R4_ABT,  INTREG_R5_ABT,  INTREG_R6_ABT,  INTREG_R7_ABT,
 390     INTREG_R8_ABT,  INTREG_R9_ABT,  INTREG_R10_ABT, INTREG_R11_ABT,
 391     INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
 392     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 393     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 394     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 395     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 396 };
 397
 398 static inline IntRegIndex
 399 INTREG_ABT(unsigned index)
 400 {
 401     assert(index < NUM_ARCH_INTREGS);
 402     return IntRegAbtMap[index];
 403 }
 404
 405 const IntRegMap IntRegUndMap = {
 406     INTREG_R0_UND,  INTREG_R1_UND,  INTREG_R2_UND,  INTREG_R3_UND,
 407     INTREG_R4_UND,  INTREG_R5_UND,  INTREG_R6_UND,  INTREG_R7_UND,
 408     INTREG_R8_UND,  INTREG_R9_UND,  INTREG_R10_UND, INTREG_R11_UND,
 409     INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
 410     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 411     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 412     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 413     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 414 };
 415
 416 static inline IntRegIndex
 417 INTREG_UND(unsigned index)
 418 {
 419     assert(index < NUM_ARCH_INTREGS);
 420     return IntRegUndMap[index];
 421 }
 422
 423 const IntRegMap IntRegIrqMap = {
 424     INTREG_R0_IRQ,  INTREG_R1_IRQ,  INTREG_R2_IRQ,  INTREG_R3_IRQ,
 425     INTREG_R4_IRQ,  INTREG_R5_IRQ,  INTREG_R6_IRQ,  INTREG_R7_IRQ,
 426     INTREG_R8_IRQ,  INTREG_R9_IRQ,  INTREG_R10_IRQ, INTREG_R11_IRQ,
 427     INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
 428     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 429     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 430     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 431     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 432 };
 433
 434 static inline IntRegIndex
 435 INTREG_IRQ(unsigned index)
 436 {
 437     assert(index < NUM_ARCH_INTREGS);
 438     return IntRegIrqMap[index];
 439 }
 440
 441 const IntRegMap IntRegFiqMap = {
 442     INTREG_R0_FIQ,  INTREG_R1_FIQ,  INTREG_R2_FIQ,  INTREG_R3_FIQ,
 443     INTREG_R4_FIQ,  INTREG_R5_FIQ,  INTREG_R6_FIQ,  INTREG_R7_FIQ,
 444     INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
 445     INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
 446     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 447     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 448     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
 449     INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
 450 };
 451
 452 static inline IntRegIndex
 453 INTREG_FIQ(unsigned index)
 454 {
 455     assert(index < NUM_ARCH_INTREGS);
 456     return IntRegFiqMap[index];
 457 }
 458
 459 static const unsigned intRegsPerMode = NUM_INTREGS;
 460
 461 static inline int
 462 intRegInMode(OperatingMode mode, int reg)
 463 {
 464     assert(reg < NUM_ARCH_INTREGS);
 465     return mode * intRegsPerMode + reg;
 466 }
 467
 468 static inline int
 469 flattenIntRegModeIndex(int reg)
 470 {
 471     int mode = reg / intRegsPerMode;
 472     reg = reg % intRegsPerMode;
 473     switch (mode) {
 474       case MODE_USER:
 475       case MODE_SYSTEM:
 476         return INTREG_USR(reg);
 477       case MODE_FIQ:
 478         return INTREG_FIQ(reg);
 479       case MODE_IRQ:
 480         return INTREG_IRQ(reg);
 481       case MODE_SVC:
 482         return INTREG_SVC(reg);
 483       case MODE_MON:
 484         return INTREG_MON(reg);
 485       case MODE_ABORT:
 486         return INTREG_ABT(reg);
 487       case MODE_HYP:
 488         return INTREG_HYP(reg);
 489       case MODE_UNDEFINED:
 490         return INTREG_UND(reg);
 491       default:
 492         panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
 493                 curTick(), reg, mode);
 494     }
 495 }
 496
 497
 498 static inline IntRegIndex
 499 makeSP(IntRegIndex reg)
 500 {
 501     if (reg == INTREG_X31)
 502         reg = INTREG_SPX;
 503     return reg;
 504 }
 505
 506 static inline IntRegIndex
 507 makeZero(IntRegIndex reg)
 508 {
 509     if (reg == INTREG_X31)
 510         reg = INTREG_ZERO;
 511     return reg;
 512 }
 513
 514 static inline bool
 515 isSP(IntRegIndex reg)
 516 {
 517     return reg == INTREG_SPX;
 518 }
 519
 520 }
 521
 522 #endif