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45 #ifndef __ARCH_ARM_INTREGS_HH__
46 #define __ARCH_ARM_INTREGS_HH__
48 #include "arch/arm/types.hh"
55 /* All the unique register indices. */
70 INTREG_SP = INTREG_R13,
72 INTREG_LR = INTREG_R14,
74 INTREG_PC = INTREG_R15,
77 INTREG_SP_SVC = INTREG_R13_SVC,
79 INTREG_LR_SVC = INTREG_R14_SVC,
82 INTREG_SP_MON = INTREG_R13_MON,
84 INTREG_LR_MON = INTREG_R14_MON,
87 INTREG_SP_HYP = INTREG_R13_HYP,
90 INTREG_SP_ABT = INTREG_R13_ABT,
92 INTREG_LR_ABT = INTREG_R14_ABT,
95 INTREG_SP_UND = INTREG_R13_UND,
97 INTREG_LR_UND = INTREG_R14_UND,
100 INTREG_SP_IRQ = INTREG_R13_IRQ,
102 INTREG_LR_IRQ = INTREG_R14_IRQ,
110 INTREG_SP_FIQ = INTREG_R13_FIQ,
112 INTREG_LR_FIQ = INTREG_R14_FIQ,
123 INTREG_DUMMY, // Dummy reg used to throw away int reg results
131 NUM_ARCH_INTREGS = 32,
133 /* AArch64 registers */
167 INTREG_SPX = NUM_INTREGS,
169 /* All the aliased indexes. */
172 INTREG_R0_USR = INTREG_R0,
173 INTREG_R1_USR = INTREG_R1,
174 INTREG_R2_USR = INTREG_R2,
175 INTREG_R3_USR = INTREG_R3,
176 INTREG_R4_USR = INTREG_R4,
177 INTREG_R5_USR = INTREG_R5,
178 INTREG_R6_USR = INTREG_R6,
179 INTREG_R7_USR = INTREG_R7,
180 INTREG_R8_USR = INTREG_R8,
181 INTREG_R9_USR = INTREG_R9,
182 INTREG_R10_USR = INTREG_R10,
183 INTREG_R11_USR = INTREG_R11,
184 INTREG_R12_USR = INTREG_R12,
185 INTREG_R13_USR = INTREG_R13,
186 INTREG_SP_USR = INTREG_SP,
187 INTREG_R14_USR = INTREG_R14,
188 INTREG_LR_USR = INTREG_LR,
189 INTREG_R15_USR = INTREG_R15,
190 INTREG_PC_USR = INTREG_PC,
193 INTREG_R0_SVC = INTREG_R0,
194 INTREG_R1_SVC = INTREG_R1,
195 INTREG_R2_SVC = INTREG_R2,
196 INTREG_R3_SVC = INTREG_R3,
197 INTREG_R4_SVC = INTREG_R4,
198 INTREG_R5_SVC = INTREG_R5,
199 INTREG_R6_SVC = INTREG_R6,
200 INTREG_R7_SVC = INTREG_R7,
201 INTREG_R8_SVC = INTREG_R8,
202 INTREG_R9_SVC = INTREG_R9,
203 INTREG_R10_SVC = INTREG_R10,
204 INTREG_R11_SVC = INTREG_R11,
205 INTREG_R12_SVC = INTREG_R12,
206 INTREG_PC_SVC = INTREG_PC,
207 INTREG_R15_SVC = INTREG_R15,
210 INTREG_R0_MON = INTREG_R0,
211 INTREG_R1_MON = INTREG_R1,
212 INTREG_R2_MON = INTREG_R2,
213 INTREG_R3_MON = INTREG_R3,
214 INTREG_R4_MON = INTREG_R4,
215 INTREG_R5_MON = INTREG_R5,
216 INTREG_R6_MON = INTREG_R6,
217 INTREG_R7_MON = INTREG_R7,
218 INTREG_R8_MON = INTREG_R8,
219 INTREG_R9_MON = INTREG_R9,
220 INTREG_R10_MON = INTREG_R10,
221 INTREG_R11_MON = INTREG_R11,
222 INTREG_R12_MON = INTREG_R12,
223 INTREG_PC_MON = INTREG_PC,
224 INTREG_R15_MON = INTREG_R15,
227 INTREG_R0_ABT = INTREG_R0,
228 INTREG_R1_ABT = INTREG_R1,
229 INTREG_R2_ABT = INTREG_R2,
230 INTREG_R3_ABT = INTREG_R3,
231 INTREG_R4_ABT = INTREG_R4,
232 INTREG_R5_ABT = INTREG_R5,
233 INTREG_R6_ABT = INTREG_R6,
234 INTREG_R7_ABT = INTREG_R7,
235 INTREG_R8_ABT = INTREG_R8,
236 INTREG_R9_ABT = INTREG_R9,
237 INTREG_R10_ABT = INTREG_R10,
238 INTREG_R11_ABT = INTREG_R11,
239 INTREG_R12_ABT = INTREG_R12,
240 INTREG_PC_ABT = INTREG_PC,
241 INTREG_R15_ABT = INTREG_R15,
244 INTREG_R0_HYP = INTREG_R0,
245 INTREG_R1_HYP = INTREG_R1,
246 INTREG_R2_HYP = INTREG_R2,
247 INTREG_R3_HYP = INTREG_R3,
248 INTREG_R4_HYP = INTREG_R4,
249 INTREG_R5_HYP = INTREG_R5,
250 INTREG_R6_HYP = INTREG_R6,
251 INTREG_R7_HYP = INTREG_R7,
252 INTREG_R8_HYP = INTREG_R8,
253 INTREG_R9_HYP = INTREG_R9,
254 INTREG_R10_HYP = INTREG_R10,
255 INTREG_R11_HYP = INTREG_R11,
256 INTREG_R12_HYP = INTREG_R12,
257 INTREG_LR_HYP = INTREG_LR,
258 INTREG_R14_HYP = INTREG_R14,
259 INTREG_PC_HYP = INTREG_PC,
260 INTREG_R15_HYP = INTREG_R15,
263 INTREG_R0_UND = INTREG_R0,
264 INTREG_R1_UND = INTREG_R1,
265 INTREG_R2_UND = INTREG_R2,
266 INTREG_R3_UND = INTREG_R3,
267 INTREG_R4_UND = INTREG_R4,
268 INTREG_R5_UND = INTREG_R5,
269 INTREG_R6_UND = INTREG_R6,
270 INTREG_R7_UND = INTREG_R7,
271 INTREG_R8_UND = INTREG_R8,
272 INTREG_R9_UND = INTREG_R9,
273 INTREG_R10_UND = INTREG_R10,
274 INTREG_R11_UND = INTREG_R11,
275 INTREG_R12_UND = INTREG_R12,
276 INTREG_PC_UND = INTREG_PC,
277 INTREG_R15_UND = INTREG_R15,
280 INTREG_R0_IRQ = INTREG_R0,
281 INTREG_R1_IRQ = INTREG_R1,
282 INTREG_R2_IRQ = INTREG_R2,
283 INTREG_R3_IRQ = INTREG_R3,
284 INTREG_R4_IRQ = INTREG_R4,
285 INTREG_R5_IRQ = INTREG_R5,
286 INTREG_R6_IRQ = INTREG_R6,
287 INTREG_R7_IRQ = INTREG_R7,
288 INTREG_R8_IRQ = INTREG_R8,
289 INTREG_R9_IRQ = INTREG_R9,
290 INTREG_R10_IRQ = INTREG_R10,
291 INTREG_R11_IRQ = INTREG_R11,
292 INTREG_R12_IRQ = INTREG_R12,
293 INTREG_PC_IRQ = INTREG_PC,
294 INTREG_R15_IRQ = INTREG_R15,
297 INTREG_R0_FIQ = INTREG_R0,
298 INTREG_R1_FIQ = INTREG_R1,
299 INTREG_R2_FIQ = INTREG_R2,
300 INTREG_R3_FIQ = INTREG_R3,
301 INTREG_R4_FIQ = INTREG_R4,
302 INTREG_R5_FIQ = INTREG_R5,
303 INTREG_R6_FIQ = INTREG_R6,
304 INTREG_R7_FIQ = INTREG_R7,
305 INTREG_PC_FIQ = INTREG_PC,
306 INTREG_R15_FIQ = INTREG_R15
309 typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
311 const IntRegMap IntReg64Map = {
312 INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
313 INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
314 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
315 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
316 INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
317 INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
318 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
319 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
322 const IntRegMap IntRegUsrMap = {
323 INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
324 INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
325 INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
326 INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
327 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
328 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
329 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
330 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
333 static inline IntRegIndex
334 INTREG_USR(unsigned index)
336 assert(index < NUM_ARCH_INTREGS);
337 return IntRegUsrMap[index];
340 const IntRegMap IntRegHypMap = {
341 INTREG_R0_HYP, INTREG_R1_HYP, INTREG_R2_HYP, INTREG_R3_HYP,
342 INTREG_R4_HYP, INTREG_R5_HYP, INTREG_R6_HYP, INTREG_R7_HYP,
343 INTREG_R8_HYP, INTREG_R9_HYP, INTREG_R10_HYP, INTREG_R11_HYP,
344 INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
345 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
346 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
347 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
348 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
351 static inline IntRegIndex
352 INTREG_HYP(unsigned index)
354 assert(index < NUM_ARCH_INTREGS);
355 return IntRegHypMap[index];
358 const IntRegMap IntRegSvcMap = {
359 INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
360 INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
361 INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
362 INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
363 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
364 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
365 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
366 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
369 static inline IntRegIndex
370 INTREG_SVC(unsigned index)
372 assert(index < NUM_ARCH_INTREGS);
373 return IntRegSvcMap[index];
376 const IntRegMap IntRegMonMap = {
377 INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
378 INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
379 INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
380 INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
381 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
382 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
383 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
384 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
387 static inline IntRegIndex
388 INTREG_MON(unsigned index)
390 assert(index < NUM_ARCH_INTREGS);
391 return IntRegMonMap[index];
394 const IntRegMap IntRegAbtMap = {
395 INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
396 INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
397 INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
398 INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
399 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
400 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
401 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
402 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
405 static inline IntRegIndex
406 INTREG_ABT(unsigned index)
408 assert(index < NUM_ARCH_INTREGS);
409 return IntRegAbtMap[index];
412 const IntRegMap IntRegUndMap = {
413 INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
414 INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
415 INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
416 INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
417 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
418 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
419 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
420 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
423 static inline IntRegIndex
424 INTREG_UND(unsigned index)
426 assert(index < NUM_ARCH_INTREGS);
427 return IntRegUndMap[index];
430 const IntRegMap IntRegIrqMap = {
431 INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
432 INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
433 INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
434 INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
435 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
436 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
437 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
438 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
441 static inline IntRegIndex
442 INTREG_IRQ(unsigned index)
444 assert(index < NUM_ARCH_INTREGS);
445 return IntRegIrqMap[index];
448 const IntRegMap IntRegFiqMap = {
449 INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
450 INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
451 INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
452 INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
453 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
454 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
455 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
456 INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
459 static inline IntRegIndex
460 INTREG_FIQ(unsigned index)
462 assert(index < NUM_ARCH_INTREGS);
463 return IntRegFiqMap[index];
466 static const unsigned intRegsPerMode = NUM_INTREGS;
469 intRegInMode(OperatingMode mode, int reg)
471 assert(reg < NUM_ARCH_INTREGS);
472 return mode * intRegsPerMode + reg;
476 flattenIntRegModeIndex(int reg)
478 int mode = reg / intRegsPerMode;
479 reg = reg % intRegsPerMode;
483 return INTREG_USR(reg);
485 return INTREG_FIQ(reg);
487 return INTREG_IRQ(reg);
489 return INTREG_SVC(reg);
491 return INTREG_MON(reg);
493 return INTREG_ABT(reg);
495 return INTREG_HYP(reg);
497 return INTREG_UND(reg);
499 panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
500 curTick(), reg, mode);
505 static inline IntRegIndex
506 makeSP(IntRegIndex reg)
508 if (reg == INTREG_X31)
515 isSP(IntRegIndex reg)
517 return reg == INTREG_SPX;