ARM: Make DataOps select from a set of ways to set the c and v flags.
[gem5.git] / src / arch / arm / isa / bitfields.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2007-2008 The Florida State University
4 // All rights reserved.
5 //
6 // Redistribution and use in source and binary forms, with or without
7 // modification, are permitted provided that the following conditions are
8 // met: redistributions of source code must retain the above copyright
9 // notice, this list of conditions and the following disclaimer;
10 // redistributions in binary form must reproduce the above copyright
11 // notice, this list of conditions and the following disclaimer in the
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14 // contributors may be used to endorse or promote products derived from
15 // this software without specific prior written permission.
16 //
17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 //
29 // Authors: Stephen Hines
30
31 ////////////////////////////////////////////////////////////////////
32 //
33 // Bitfield definitions.
34 //
35
36 // Opcode fields
37 def bitfield ENCODING encoding;
38 def bitfield OPCODE opcode;
39 def bitfield MEDIA_OPCODE mediaOpcode;
40 def bitfield MEDIA_OPCODE2 mediaOpcode2;
41 def bitfield OPCODE_24 opcode24;
42 def bitfield OPCODE_23_20 opcode23_20;
43 def bitfield OPCODE_23_21 opcode23_21;
44 def bitfield OPCODE_22 opcode22;
45 def bitfield OPCODE_19 opcode19;
46 def bitfield OPCODE_15_12 opcode15_12;
47 def bitfield OPCODE_15 opcode15;
48 def bitfield MISC_OPCODE miscOpcode;
49 def bitfield OPCODE_7 opcode7;
50 def bitfield OPCODE_4 opcode4;
51
52 def bitfield IS_MISC isMisc;
53 def bitfield SEVEN_AND_FOUR sevenAndFour;
54
55 // Other
56 def bitfield COND_CODE condCode;
57 def bitfield S_FIELD sField;
58 def bitfield RN rn;
59 def bitfield RD rd;
60 def bitfield SHIFT_SIZE shiftSize;
61 def bitfield SHIFT shift;
62 def bitfield RM rm;
63
64 def bitfield RS rs;
65
66 def bitfield PUSWL puswl;
67 def bitfield PREPOST puswl.prepost;
68 def bitfield UP puswl.up;
69 def bitfield PSRUSER puswl.psruser;
70 def bitfield WRITEBACK puswl.writeback;
71 def bitfield LOADOP puswl.loadOp;
72
73 def bitfield PUBWL pubwl;
74
75 def bitfield IMM imm;
76
77 def bitfield IMMED_11_0 immed11_0;
78
79 def bitfield IMMED_HI_11_8 immedHi11_8;
80 def bitfield IMMED_LO_3_0 immedLo3_0;
81
82 def bitfield IMMED_23_0 immed23_0;
83
84 def bitfield CPNUM cpNum;
85 // Note that FP Regs are only 3 bits
86 def bitfield FN fn;
87 def bitfield FD fd;
88 def bitfield FPREGIMM fpRegImm;
89 // We can just use 3:0 for FM since the hard-wired FP regs are handled in
90 // float_regfile.hh
91 def bitfield FM fm;
92 def bitfield FPIMM fpImm;
93 def bitfield PUNWL punwl;
94
95 // M5 instructions
96 def bitfield M5FUNC m5Func;
97