src/arch/arm/isa/formats/data.isa

   1 // Copyright (c) 2010 ARM Limited
   2 // All rights reserved
   3 //
   4 // The license below extends only to copyright in the software and shall
   5 // not be construed as granting a license to any other intellectual
   6 // property including but not limited to intellectual property relating
   7 // to a hardware implementation of the functionality of the software
   8 // licensed hereunder.  You may use the software subject to the license
   9 // terms below provided that you ensure that this notice is replicated
  10 // unmodified and in its entirety in all distributions of the software,
  11 // modified or unmodified, in source code or in binary form.
  12 //
  13 // Redistribution and use in source and binary forms, with or without
  14 // modification, are permitted provided that the following conditions are
  15 // met: redistributions of source code must retain the above copyright
  16 // notice, this list of conditions and the following disclaimer;
  17 // redistributions in binary form must reproduce the above copyright
  18 // notice, this list of conditions and the following disclaimer in the
  19 // documentation and/or other materials provided with the distribution;
  20 // neither the name of the copyright holders nor the names of its
  21 // contributors may be used to endorse or promote products derived from
  22 // this software without specific prior written permission.
  23 //
  24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 //
  36 // Authors: Gabe Black
  37
  38 def format ArmDataProcReg() {{
  39     instDecode = '''
  40           case %(opcode)#x:
  41             if (immShift) {
  42                 if (setCc) {
  43                     return new %(className)sRegCc(machInst, %(dest)s, %(op1)s,
  44                                                    rm, imm5, type);
  45                 } else {
  46                     return new %(className)sReg(machInst, %(dest)s, %(op1)s,
  47                                                  rm, imm5, type);
  48                 }
  49             } else {
  50                 if (setCc) {
  51                     return new %(className)sRegRegCc(machInst, %(dest)s,
  52                                                       %(op1)s, rm, rs, type);
  53                 } else {
  54                     return new %(className)sRegReg(machInst, %(dest)s,
  55                                                     %(op1)s, rm, rs, type);
  56                 }
  57             }
  58             break;
  59     '''
  60
  61     def instCode(opcode, mnem, dest="rd", op1="rn"):
  62         global instDecode
  63         return instDecode % { "className": mnem.capitalize(),
  64                               "opcode": opcode,
  65                               "dest": dest,
  66                               "op1": op1 }
  67
  68     decode_block = '''
  69     {
  70         const bool immShift = (bits(machInst, 4) == 0);
  71         const bool setCc = (bits(machInst, 20) == 1);
  72         const uint32_t imm5 = bits(machInst, 11, 7);
  73         const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
  74         const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
  75         const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
  76         const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
  77         const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
  78         switch (OPCODE) {
  79     '''
  80     decode_block += instCode(0x0, "and")
  81     decode_block += instCode(0x1, "eor")
  82     decode_block += instCode(0x2, "sub")
  83     decode_block += instCode(0x3, "rsb")
  84     decode_block += instCode(0x4, "add")
  85     decode_block += instCode(0x5, "adc")
  86     decode_block += instCode(0x6, "sbc")
  87     decode_block += instCode(0x7, "rsc")
  88     decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
  89     decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
  90     decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
  91     decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
  92     decode_block += instCode(0xc, "orr")
  93     decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
  94     decode_block += instCode(0xe, "bic")
  95     decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
  96     decode_block += '''
  97           default:
  98             return new Unknown(machInst);
  99         }
 100     }
 101     '''
 102 }};
 103
 104 def format ArmDataProcImm() {{
 105     instDecode = '''
 106           case %(opcode)#x:
 107             if (setCc) {
 108                 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
 109                                                imm, rotC);
 110             } else {
 111                 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
 112                                              imm, rotC);
 113             }
 114             break;
 115     '''
 116
 117     def instCode(opcode, mnem, dest="rd", op1="rn"):
 118         global instDecode
 119         return instDecode % { "className": mnem.capitalize(),
 120                               "opcode": opcode,
 121                               "dest": dest,
 122                               "op1": op1 }
 123
 124     decode_block = '''
 125     {
 126         const bool setCc = (bits(machInst, 20) == 1);
 127         const uint32_t unrotated = bits(machInst, 7, 0);
 128         const uint32_t rotation = (bits(machInst, 11, 8) << 1);
 129         const bool rotC = (rotation != 0);
 130         const uint32_t imm = rotate_imm(unrotated, rotation);
 131         const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
 132         const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
 133         switch (OPCODE) {
 134     '''
 135     decode_block += instCode(0x0, "and")
 136     decode_block += instCode(0x1, "eor")
 137     decode_block += instCode(0x2, "sub")
 138     decode_block += instCode(0x3, "rsb")
 139     decode_block += instCode(0x4, "add")
 140     decode_block += instCode(0x5, "adc")
 141     decode_block += instCode(0x6, "sbc")
 142     decode_block += instCode(0x7, "rsc")
 143     decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
 144     decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
 145     decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
 146     decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
 147     decode_block += instCode(0xc, "orr")
 148     decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
 149     decode_block += instCode(0xe, "bic")
 150     decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
 151     decode_block += '''
 152           default:
 153             return new Unknown(machInst);
 154         }
 155     }
 156     '''
 157 }};
 158
 159 def format Thumb16ShiftAddSubMoveCmp() {{
 160     decode_block = '''
 161     {
 162         const uint32_t imm5 = bits(machInst, 10, 6);
 163         const uint32_t imm3 = bits(machInst, 8, 6);
 164         const uint32_t imm8 = bits(machInst, 7, 0);
 165         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
 166         const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
 167         const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
 168         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
 169         switch (bits(machInst, 13, 11)) {
 170           case 0x0: // lsl
 171             return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
 172           case 0x1: // lsr
 173             return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
 174           case 0x2: // asr
 175             return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
 176           case 0x3:
 177             switch (bits(machInst, 10, 9)) {
 178               case 0x0:
 179                 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
 180               case 0x1:
 181                 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
 182               case 0x2:
 183                 return new AddImmCc(machInst, rd, rn, imm3, true);
 184               case 0x3:
 185                 return new SubImmCc(machInst, rd, rn, imm3, true);
 186             }
 187           case 0x4:
 188             return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
 189           case 0x5:
 190             return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
 191           case 0x6:
 192             return new AddImmCc(machInst, rd8, rd8, imm8, true);
 193           case 0x7:
 194             return new SubImmCc(machInst, rd8, rd8, imm8, true);
 195         }
 196     }
 197     '''
 198 }};
 199
 200 def format Thumb16DataProcessing() {{
 201     decode_block = '''
 202     {
 203         const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
 204         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
 205         switch (bits(machInst, 9, 6)) {
 206           case 0x0:
 207             return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
 208           case 0x1:
 209             return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
 210           case 0x2: //lsl
 211             return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
 212           case 0x3: //lsr
 213             return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
 214           case 0x4: //asr
 215             return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
 216           case 0x5:
 217             return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
 218           case 0x6:
 219             return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
 220           case 0x7: // ror
 221             return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
 222           case 0x8:
 223             return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
 224           case 0x9:
 225             return new RsbImmCc(machInst, rdn, rm, 0, true);
 226           case 0xa:
 227             return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
 228           case 0xb:
 229             return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
 230           case 0xc:
 231             return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
 232           case 0xd:
 233             return new MulCc(machInst, rdn, rm, rdn);
 234           case 0xe:
 235             return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
 236           case 0xf:
 237             return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
 238         }
 239     }
 240     '''
 241 }};
 242
 243 def format Thumb16SpecDataAndBx() {{
 244     decode_block = '''
 245     {
 246         const IntRegIndex rdn =
 247             (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
 248                                     (bits(machInst, 7) << 3));
 249         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
 250         switch (bits(machInst, 9, 8)) {
 251           case 0x0:
 252             return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
 253           case 0x1:
 254             return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
 255           case 0x2:
 256             return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
 257           case 0x3:
 258             if (bits(machInst, 7) == 0) {
 259                 return new BxReg(machInst,
 260                                  (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
 261                                  COND_UC);
 262             } else {
 263                 return new BlxReg(machInst,
 264                                   (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
 265                                   COND_UC);
 266             }
 267         }
 268     }
 269     '''
 270 }};
 271
 272 def format Thumb16Adr() {{
 273     decode_block = '''
 274     {
 275         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
 276         const uint32_t imm8 = bits(machInst, 7, 0) << 2;
 277         return new AddImm(machInst, rd, INTREG_PC, imm8, true);
 278     }
 279     '''
 280 }};
 281
 282 def format Thumb16AddSp() {{
 283     decode_block = '''
 284     {
 285         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
 286         const uint32_t imm8 = bits(machInst, 7, 0) << 2;
 287         return new AddImm(machInst, rd, INTREG_SP, imm8, true);
 288     }
 289     '''
 290 }};
 291
 292 def format Thumb16Misc() {{
 293     decode_block = '''
 294     {
 295         switch (bits(machInst, 11, 8)) {
 296           case 0x0:
 297             if (bits(machInst, 7)) {
 298                 return new SubImm(machInst, INTREG_SP, INTREG_SP,
 299                                    bits(machInst, 6, 0) << 2, true);
 300             } else {
 301                 return new AddImm(machInst, INTREG_SP, INTREG_SP,
 302                                    bits(machInst, 6, 0) << 2, true);
 303             }
 304           case 0x1:
 305             return new Cbz(machInst,
 306                            (bits(machInst, 9) << 6) |
 307                            (bits(machInst, 7, 3) << 1),
 308                            (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
 309           case 0x2:
 310             switch (bits(machInst, 7, 6)) {
 311               case 0x0:
 312                 return new WarnUnimplemented("sxth", machInst);
 313               case 0x1:
 314                 return new WarnUnimplemented("sxtb", machInst);
 315               case 0x2:
 316                 return new WarnUnimplemented("uxth", machInst);
 317               case 0x3:
 318                 return new WarnUnimplemented("uxtb", machInst);
 319             }
 320           case 0x3:
 321             return new Cbz(machInst,
 322                            (bits(machInst, 9) << 6) |
 323                            (bits(machInst, 7, 3) << 1),
 324                            (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
 325           case 0x4:
 326           case 0x5:
 327             return new WarnUnimplemented("push", machInst);
 328           case 0x6:
 329             {
 330                 const uint32_t opBits = bits(machInst, 7, 5);
 331                 if (opBits == 2) {
 332                     return new WarnUnimplemented("setend", machInst);
 333                 } else if (opBits == 3) {
 334                     return new WarnUnimplemented("cps", machInst);
 335                 }
 336             }
 337           case 0x9:
 338             return new Cbnz(machInst,
 339                             (bits(machInst, 9) << 6) |
 340                             (bits(machInst, 7, 3) << 1),
 341                             (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
 342           case 0xa:
 343             switch (bits(machInst, 7, 5)) {
 344               case 0x0:
 345                 return new WarnUnimplemented("rev", machInst);
 346               case 0x1:
 347                 return new WarnUnimplemented("rev16", machInst);
 348               case 0x3:
 349                 return new WarnUnimplemented("revsh", machInst);
 350               default:
 351                 break;
 352             }
 353             break;
 354           case 0xb:
 355             return new Cbnz(machInst,
 356                             (bits(machInst, 9) << 6) |
 357                             (bits(machInst, 7, 3) << 1),
 358                             (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
 359           case 0xc:
 360           case 0xd:
 361             return new WarnUnimplemented("pop", machInst);
 362           case 0xe:
 363             return new WarnUnimplemented("bkpt", machInst);
 364           case 0xf:
 365             if (bits(machInst, 3, 0) != 0)
 366                 return new WarnUnimplemented("it", machInst);
 367             switch (bits(machInst, 7, 4)) {
 368               case 0x0:
 369                 return new WarnUnimplemented("nop", machInst);
 370               case 0x1:
 371                 return new WarnUnimplemented("yield", machInst);
 372               case 0x2:
 373                 return new WarnUnimplemented("wfe", machInst);
 374               case 0x3:
 375                 return new WarnUnimplemented("wfi", machInst);
 376               case 0x4:
 377                 return new WarnUnimplemented("sev", machInst);
 378               default:
 379                 return new WarnUnimplemented("unallocated_hint", machInst);
 380             }
 381           default:
 382             break;
 383         }
 384         return new Unknown(machInst);
 385     }
 386     '''
 387 }};
 388
 389 def format Thumb32DataProcModImm() {{
 390
 391     def decInst(mnem, dest="rd", op1="rn"):
 392         return '''
 393             if (s) {
 394                 return new %(mnem)sImmCc(machInst, %(dest)s,
 395                                           %(op1)s, imm, rotC);
 396             } else {
 397                 return new %(mnem)sImm(machInst, %(dest)s,
 398                                         %(op1)s, imm, rotC);
 399             }
 400         ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
 401
 402     decode_block = '''
 403     {
 404         const uint32_t op = bits(machInst, 24, 21);
 405         const bool s = (bits(machInst, 20) == 1);
 406         const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
 407         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
 408         const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
 409                                  bits(machInst, 14, 12);
 410         const bool rotC = ctrlImm > 3;
 411         const uint32_t dataImm = bits(machInst, 7, 0);
 412         const uint32_t imm = modified_imm(ctrlImm, dataImm);
 413         switch (op) {
 414           case 0x0:
 415             if (rd == INTREG_PC) {
 416                 %(tst)s
 417             } else {
 418                 %(and)s
 419             }
 420           case 0x1:
 421             %(bic)s
 422           case 0x2:
 423             if (rn == INTREG_PC) {
 424                 %(mov)s
 425             } else {
 426                 %(orr)s
 427             }
 428           case 0x3:
 429             if (rn == INTREG_PC) {
 430                 %(mvn)s
 431             } else {
 432                 %(orn)s
 433             }
 434           case 0x4:
 435             if (rd == INTREG_PC) {
 436                 %(teq)s
 437             } else {
 438                 %(eor)s
 439             }
 440           case 0x8:
 441             if (rd == INTREG_PC) {
 442                 %(cmn)s
 443             } else {
 444                 %(add)s
 445             }
 446           case 0xa:
 447             %(adc)s
 448           case 0xb:
 449             %(sbc)s
 450           case 0xd:
 451             if (rd == INTREG_PC) {
 452                 %(cmp)s
 453             } else {
 454                 %(sub)s
 455             }
 456           case 0xe:
 457             %(rsb)s
 458           default:
 459             return new Unknown(machInst);
 460         }
 461     }
 462     ''' % {
 463         "tst" : decInst("Tst", "INTREG_ZERO"),
 464         "and" : decInst("And"),
 465         "bic" : decInst("Bic"),
 466         "mov" : decInst("Mov", op1="INTREG_ZERO"),
 467         "orr" : decInst("Orr"),
 468         "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
 469         "orn" : decInst("Orn"),
 470         "teq" : decInst("Teq", dest="INTREG_ZERO"),
 471         "eor" : decInst("Eor"),
 472         "cmn" : decInst("Cmn", dest="INTREG_ZERO"),
 473         "add" : decInst("Add"),
 474         "adc" : decInst("Adc"),
 475         "sbc" : decInst("Sbc"),
 476         "cmp" : decInst("Cmp", dest="INTREG_ZERO"),
 477         "sub" : decInst("Sub"),
 478         "rsb" : decInst("Rsb")
 479     }
 480 }};
 481
 482 def format Thumb32DataProcPlainBin() {{
 483     decode_block = '''
 484     {
 485         const uint32_t op = bits(machInst, 24, 20);
 486         const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
 487         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
 488         switch (op) {
 489           case 0x0:
 490             {
 491                 const uint32_t imm = bits(machInst, 7, 0) |
 492                                      (bits(machInst, 14, 12) << 8) |
 493                                      (bits(machInst, 26) << 11);
 494                 return new AddImm(machInst, rd, rn, imm, true);
 495             }
 496           case 0x4:
 497             {
 498                 const uint32_t imm = bits(machInst, 7, 0) |
 499                                      (bits(machInst, 14, 12) << 8) |
 500                                      (bits(machInst, 26) << 11) |
 501                                      (bits(machInst, 19, 16) << 12);
 502                 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
 503             }
 504           case 0xa:
 505             {
 506                 const uint32_t imm = bits(machInst, 7, 0) |
 507                                      (bits(machInst, 14, 12) << 8) |
 508                                      (bits(machInst, 26) << 11);
 509                 return new SubImm(machInst, rd, rn, imm, true);
 510             }
 511           case 0xc:
 512             {
 513                 const uint32_t imm = bits(machInst, 7, 0) |
 514                                      (bits(machInst, 14, 12) << 8) |
 515                                      (bits(machInst, 26) << 11) |
 516                                      (bits(machInst, 19, 16) << 12);
 517                 return new MovtImm(machInst, rd, rd, imm, true);
 518             }
 519           case 0x12:
 520             if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
 521                 return new WarnUnimplemented("ssat16", machInst);
 522             }
 523             // Fall through on purpose...
 524           case 0x10:
 525             return new WarnUnimplemented("ssat", machInst);
 526           case 0x14:
 527             return new WarnUnimplemented("sbfx", machInst);
 528           case 0x16:
 529             if (rn == 0xf) {
 530                 return new WarnUnimplemented("bfc", machInst);
 531             } else {
 532                 return new WarnUnimplemented("bfi", machInst);
 533             }
 534           case 0x1a:
 535             if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
 536                 return new WarnUnimplemented("usat16", machInst);
 537             }
 538             // Fall through on purpose...
 539           case 0x18:
 540             return new WarnUnimplemented("usat", machInst);
 541           case 0x1c:
 542             return new WarnUnimplemented("ubfx", machInst);
 543           default:
 544             return new Unknown(machInst);
 545         }
 546     }
 547     '''
 548 }};
 549
 550 def format Thumb32DataProcShiftReg() {{
 551
 552     def decInst(mnem, dest="rd", op1="rn"):
 553         return '''
 554             if (s) {
 555                 return new %(mnem)sRegCc(machInst, %(dest)s,
 556                                           %(op1)s, rm, amt, type);
 557             } else {
 558                 return new %(mnem)sReg(machInst, %(dest)s,
 559                                         %(op1)s, rm, amt, type);
 560             }
 561         ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
 562
 563     decode_block = '''
 564     {
 565         const uint32_t op = bits(machInst, 24, 21);
 566         const bool s = (bits(machInst, 20) == 1);
 567         const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
 568         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
 569         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
 570         const uint32_t amt = (bits(machInst, 14, 12) << 2) |
 571                               bits(machInst, 7, 6);
 572         const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
 573         switch (op) {
 574           case 0x0:
 575             if (rd == INTREG_PC) {
 576                 %(tst)s
 577             } else {
 578                 %(and)s
 579             }
 580           case 0x1:
 581             %(bic)s
 582           case 0x2:
 583             if (rn == INTREG_PC) {
 584                 %(mov)s
 585             } else {
 586                 %(orr)s
 587             }
 588           case 0x3:
 589             if (rn == INTREG_PC) {
 590                 %(mvn)s
 591             } else {
 592                 %(orn)s
 593             }
 594           case 0x4:
 595             if (rd == INTREG_PC) {
 596                 %(teq)s
 597             } else {
 598                 %(eor)s
 599             }
 600           case 0x6:
 601             return new WarnUnimplemented("pkh", machInst);
 602           case 0x8:
 603             if (rd == INTREG_PC) {
 604                 %(cmn)s
 605             } else {
 606                 %(add)s
 607             }
 608           case 0xa:
 609             %(adc)s
 610           case 0xb:
 611             %(sbc)s
 612           case 0xd:
 613             if (rd == INTREG_PC) {
 614                 %(cmp)s
 615             } else {
 616                 %(sub)s
 617             }
 618           case 0xe:
 619             %(rsb)s
 620           default:
 621             return new Unknown(machInst);
 622         }
 623     }
 624     ''' % {
 625         "tst" : decInst("Tst", "INTREG_ZERO"),
 626         "and" : decInst("And"),
 627         "bic" : decInst("Bic"),
 628         "mov" : decInst("Mov", op1="INTREG_ZERO"),
 629         "orr" : decInst("Orr"),
 630         "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
 631         "orn" : decInst("Orn"),
 632         "teq" : decInst("Teq", "INTREG_ZERO"),
 633         "eor" : decInst("Eor"),
 634         "cmn" : decInst("Cmn", "INTREG_ZERO"),
 635         "add" : decInst("Add"),
 636         "adc" : decInst("Adc"),
 637         "sbc" : decInst("Sbc"),
 638         "cmp" : decInst("Cmp", "INTREG_ZERO"),
 639         "sub" : decInst("Sub"),
 640         "rsb" : decInst("Rsb")
 641     }
 642 }};