1 // Copyright (c) 2010 ARM Limited
4 // The license below extends only to copyright in the software and shall
5 // not be construed as granting a license to any other intellectual
6 // property including but not limited to intellectual property relating
7 // to a hardware implementation of the functionality of the software
8 // licensed hereunder. You may use the software subject to the license
9 // terms below provided that you ensure that this notice is replicated
10 // unmodified and in its entirety in all distributions of the software,
11 // modified or unmodified, in source code or in binary form.
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions are
15 // met: redistributions of source code must retain the above copyright
16 // notice, this list of conditions and the following disclaimer;
17 // redistributions in binary form must reproduce the above copyright
18 // notice, this list of conditions and the following disclaimer in the
19 // documentation and/or other materials provided with the distribution;
20 // neither the name of the copyright holders nor the names of its
21 // contributors may be used to endorse or promote products derived from
22 // this software without specific prior written permission.
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 // Authors: Gabe Black
38 def format ArmDataProcReg() {{
40 return new %(className)ssRegPclr(machInst, %(dest)s,
48 if (%(dest)s == INTREG_PC) {
51 return new %(className)sRegCc(machInst, %(dest)s,
52 %(op1)s, rm, imm5, type);
55 return new %(className)sReg(machInst, %(dest)s, %(op1)s,
60 return new %(className)sRegRegCc(machInst, %(dest)s,
61 %(op1)s, rm, rs, type);
63 return new %(className)sRegReg(machInst, %(dest)s,
64 %(op1)s, rm, rs, type);
70 def instCode(opcode, mnem, useDest = True, useOp1 = True):
80 global instDecode, pclrCode
81 substDict = { "className": mnem.capitalize(),
86 substDict["pclr"] = pclr % substDict
88 substDict["pclr"] = ""
89 return instDecode % substDict
93 const bool immShift = (bits(machInst, 4) == 0);
94 const bool setCc = (bits(machInst, 20) == 1);
95 const uint32_t imm5 = bits(machInst, 11, 7);
96 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
97 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
98 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
99 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
100 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
103 decode_block += instCode(0x0, "and")
104 decode_block += instCode(0x1, "eor")
105 decode_block += instCode(0x2, "sub")
106 decode_block += instCode(0x3, "rsb")
107 decode_block += instCode(0x4, "add")
108 decode_block += instCode(0x5, "adc")
109 decode_block += instCode(0x6, "sbc")
110 decode_block += instCode(0x7, "rsc")
111 decode_block += instCode(0x8, "tst", useDest = False)
112 decode_block += instCode(0x9, "teq", useDest = False)
113 decode_block += instCode(0xa, "cmp", useDest = False)
114 decode_block += instCode(0xb, "cmn", useDest = False)
115 decode_block += instCode(0xc, "orr")
116 decode_block += instCode(0xd, "mov", useOp1 = False)
117 decode_block += instCode(0xe, "bic")
118 decode_block += instCode(0xf, "mvn", useOp1 = False)
121 return new Unknown(machInst);
127 def format ArmParallelAddSubtract() {{
130 const uint32_t op1 = bits(machInst, 21, 20);
131 const uint32_t op2 = bits(machInst, 7, 5);
132 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
133 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
134 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
135 if (bits(machInst, 22) == 0) {
140 return new WarnUnimplemented("sadd16", machInst);
142 return new WarnUnimplemented("sasx", machInst);
144 return new WarnUnimplemented("ssax", machInst);
146 return new WarnUnimplemented("ssub16", machInst);
148 return new WarnUnimplemented("sadd8", machInst);
150 return new WarnUnimplemented("ssub8", machInst);
156 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
158 return new QasxReg(machInst, rd, rn, rm, 0, LSL);
160 return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
162 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
164 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
166 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
172 return new WarnUnimplemented("shadd16", machInst);
174 return new WarnUnimplemented("shasx", machInst);
176 return new WarnUnimplemented("shsax", machInst);
178 return new WarnUnimplemented("shsub16", machInst);
180 return new WarnUnimplemented("shadd8", machInst);
182 return new WarnUnimplemented("shsub8", machInst);
191 return new WarnUnimplemented("uadd16", machInst);
193 return new WarnUnimplemented("uasx", machInst);
195 return new WarnUnimplemented("usax", machInst);
197 return new WarnUnimplemented("usub16", machInst);
199 return new WarnUnimplemented("uadd8", machInst);
201 return new WarnUnimplemented("usub8", machInst);
207 return new WarnUnimplemented("uqadd16", machInst);
209 return new WarnUnimplemented("uqasx", machInst);
211 return new WarnUnimplemented("uqsax", machInst);
213 return new WarnUnimplemented("uqsub16", machInst);
215 return new WarnUnimplemented("uqadd8", machInst);
217 return new WarnUnimplemented("uqsub8", machInst);
223 return new WarnUnimplemented("uhadd16", machInst);
225 return new WarnUnimplemented("uhasx", machInst);
227 return new WarnUnimplemented("uhsax", machInst);
229 return new WarnUnimplemented("uhsub16", machInst);
231 return new WarnUnimplemented("uhadd8", machInst);
233 return new WarnUnimplemented("uhsub8", machInst);
238 return new Unknown(machInst);
243 def format ArmDataProcImm() {{
245 return new %(className)ssImmPclr(machInst, %(dest)s,
246 %(op1)s, imm, false);
249 return new AdrImm(machInst, %(dest)s, %(add)s,
255 if (%(pclrInst)s && %(dest)s == INTREG_PC) {
258 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s,
262 if (%(adrInst)s && %(op1)s == INTREG_PC) {
265 return new %(className)sImm(machInst, %(dest)s, %(op1)s,
272 def instCode(opcode, mnem, useDest = True, useOp1 = True):
273 global instDecode, pclr, adr
282 substDict = { "className": mnem.capitalize(),
289 substDict["pclrInst"] = "true"
290 substDict["pclr"] = pclr % substDict
292 substDict["pclrInst"] = "false"
293 substDict["pclr"] = ""
294 return instDecode % substDict
296 def adrCode(opcode, mnem, add="1"):
297 global instDecode, pclr, adr
298 substDict = { "className": mnem.capitalize(),
305 substDict["pclr"] = pclr % substDict
306 substDict["adr"] = adr % substDict
307 return instDecode % substDict
311 const bool setCc = (bits(machInst, 20) == 1);
312 const uint32_t unrotated = bits(machInst, 7, 0);
313 const uint32_t rotation = (bits(machInst, 11, 8) << 1);
314 const bool rotC = (rotation != 0);
315 const uint32_t imm = rotate_imm(unrotated, rotation);
316 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
317 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
320 decode_block += instCode(0x0, "and")
321 decode_block += instCode(0x1, "eor")
322 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0")
323 decode_block += instCode(0x3, "rsb")
324 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1")
325 decode_block += instCode(0x5, "adc")
326 decode_block += instCode(0x6, "sbc")
327 decode_block += instCode(0x7, "rsc")
328 decode_block += instCode(0x8, "tst", useDest = False)
329 decode_block += instCode(0x9, "teq", useDest = False)
330 decode_block += instCode(0xa, "cmp", useDest = False)
331 decode_block += instCode(0xb, "cmn", useDest = False)
332 decode_block += instCode(0xc, "orr")
333 decode_block += instCode(0xd, "mov", useOp1 = False)
334 decode_block += instCode(0xe, "bic")
335 decode_block += instCode(0xf, "mvn", useOp1 = False)
338 return new Unknown(machInst);
344 def format ArmSatAddSub() {{
347 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
348 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
349 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
352 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
354 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
356 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
358 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
360 return new Unknown(machInst);
366 def format Thumb16ShiftAddSubMoveCmp() {{
369 const uint32_t imm5 = bits(machInst, 10, 6);
370 const uint32_t imm3 = bits(machInst, 8, 6);
371 const uint32_t imm8 = bits(machInst, 7, 0);
372 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
373 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
374 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
375 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
376 switch (bits(machInst, 13, 11)) {
378 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
380 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
382 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
384 switch (bits(machInst, 10, 9)) {
386 return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
388 return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
390 return new AddImmCc(machInst, rd, rn, imm3, true);
392 return new SubImmCc(machInst, rd, rn, imm3, true);
395 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
397 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
399 return new AddImmCc(machInst, rd8, rd8, imm8, true);
401 return new SubImmCc(machInst, rd8, rd8, imm8, true);
407 def format Thumb16DataProcessing() {{
410 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
411 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
412 switch (bits(machInst, 9, 6)) {
414 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
416 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
418 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
420 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
422 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
424 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
426 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
428 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
430 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
432 return new RsbImmCc(machInst, rdn, rm, 0, true);
434 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
436 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
438 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
440 return new MulCc(machInst, rdn, rm, rdn);
442 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
444 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
450 def format Thumb16SpecDataAndBx() {{
453 const IntRegIndex rdn =
454 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
455 (bits(machInst, 7) << 3));
456 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
457 switch (bits(machInst, 9, 8)) {
459 return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
461 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
463 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
465 if (bits(machInst, 7) == 0) {
466 return new BxReg(machInst,
467 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
470 return new BlxReg(machInst,
471 (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
479 def format Thumb16Adr() {{
482 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
483 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
484 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false);
489 def format Thumb16AddSp() {{
492 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
493 const uint32_t imm8 = bits(machInst, 7, 0) << 2;
494 return new AddImm(machInst, rd, INTREG_SP, imm8, true);
499 def format Thumb16Misc() {{
502 switch (bits(machInst, 11, 8)) {
504 if (bits(machInst, 7)) {
505 return new SubImm(machInst, INTREG_SP, INTREG_SP,
506 bits(machInst, 6, 0) << 2, true);
508 return new AddImm(machInst, INTREG_SP, INTREG_SP,
509 bits(machInst, 6, 0) << 2, true);
512 return new Cbz(machInst,
513 (bits(machInst, 9) << 6) |
514 (bits(machInst, 7, 3) << 1),
515 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
517 switch (bits(machInst, 7, 6)) {
519 return new WarnUnimplemented("sxth", machInst);
521 return new WarnUnimplemented("sxtb", machInst);
523 return new WarnUnimplemented("uxth", machInst);
525 return new WarnUnimplemented("uxtb", machInst);
528 return new Cbz(machInst,
529 (bits(machInst, 9) << 6) |
530 (bits(machInst, 7, 3) << 1),
531 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
534 return new WarnUnimplemented("push", machInst);
537 const uint32_t opBits = bits(machInst, 7, 5);
539 return new WarnUnimplemented("setend", machInst);
540 } else if (opBits == 3) {
541 return new WarnUnimplemented("cps", machInst);
545 return new Cbnz(machInst,
546 (bits(machInst, 9) << 6) |
547 (bits(machInst, 7, 3) << 1),
548 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
550 switch (bits(machInst, 7, 5)) {
552 return new WarnUnimplemented("rev", machInst);
554 return new WarnUnimplemented("rev16", machInst);
556 return new WarnUnimplemented("revsh", machInst);
562 return new Cbnz(machInst,
563 (bits(machInst, 9) << 6) |
564 (bits(machInst, 7, 3) << 1),
565 (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
568 return new WarnUnimplemented("pop", machInst);
570 return new WarnUnimplemented("bkpt", machInst);
572 if (bits(machInst, 3, 0) != 0)
573 return new WarnUnimplemented("it", machInst);
574 switch (bits(machInst, 7, 4)) {
576 return new WarnUnimplemented("nop", machInst);
578 return new WarnUnimplemented("yield", machInst);
580 return new WarnUnimplemented("wfe", machInst);
582 return new WarnUnimplemented("wfi", machInst);
584 return new WarnUnimplemented("sev", machInst);
586 return new WarnUnimplemented("unallocated_hint", machInst);
591 return new Unknown(machInst);
596 def format Thumb32DataProcModImm() {{
598 def decInst(mnem, dest="rd", op1="rn"):
601 return new %(mnem)sImmCc(machInst, %(dest)s,
604 return new %(mnem)sImm(machInst, %(dest)s,
607 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
611 const uint32_t op = bits(machInst, 24, 21);
612 const bool s = (bits(machInst, 20) == 1);
613 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
614 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
615 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
616 bits(machInst, 14, 12);
617 const bool rotC = ctrlImm > 3;
618 const uint32_t dataImm = bits(machInst, 7, 0);
619 const uint32_t imm = modified_imm(ctrlImm, dataImm);
622 if (rd == INTREG_PC) {
630 if (rn == INTREG_PC) {
636 if (rn == INTREG_PC) {
642 if (rd == INTREG_PC) {
648 if (rd == INTREG_PC) {
658 if (rd == INTREG_PC) {
666 return new Unknown(machInst);
670 "tst" : decInst("Tst", "INTREG_ZERO"),
671 "and" : decInst("And"),
672 "bic" : decInst("Bic"),
673 "mov" : decInst("Mov", op1="INTREG_ZERO"),
674 "orr" : decInst("Orr"),
675 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
676 "orn" : decInst("Orn"),
677 "teq" : decInst("Teq", dest="INTREG_ZERO"),
678 "eor" : decInst("Eor"),
679 "cmn" : decInst("Cmn", dest="INTREG_ZERO"),
680 "add" : decInst("Add"),
681 "adc" : decInst("Adc"),
682 "sbc" : decInst("Sbc"),
683 "cmp" : decInst("Cmp", dest="INTREG_ZERO"),
684 "sub" : decInst("Sub"),
685 "rsb" : decInst("Rsb")
689 def format Thumb32DataProcPlainBin() {{
692 const uint32_t op = bits(machInst, 24, 20);
693 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
694 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
698 const uint32_t imm = bits(machInst, 7, 0) |
699 (bits(machInst, 14, 12) << 8) |
700 (bits(machInst, 26) << 11);
702 return new AdrImm(machInst, rd, (IntRegIndex)1,
705 return new AddImm(machInst, rd, rn, imm, true);
710 const uint32_t imm = bits(machInst, 7, 0) |
711 (bits(machInst, 14, 12) << 8) |
712 (bits(machInst, 26) << 11) |
713 (bits(machInst, 19, 16) << 12);
714 return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
718 const uint32_t imm = bits(machInst, 7, 0) |
719 (bits(machInst, 14, 12) << 8) |
720 (bits(machInst, 26) << 11);
722 return new AdrImm(machInst, rd, (IntRegIndex)0,
725 return new SubImm(machInst, rd, rn, imm, true);
730 const uint32_t imm = bits(machInst, 7, 0) |
731 (bits(machInst, 14, 12) << 8) |
732 (bits(machInst, 26) << 11) |
733 (bits(machInst, 19, 16) << 12);
734 return new MovtImm(machInst, rd, rd, imm, true);
737 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
738 return new WarnUnimplemented("ssat16", machInst);
740 // Fall through on purpose...
742 return new WarnUnimplemented("ssat", machInst);
744 return new WarnUnimplemented("sbfx", machInst);
747 return new WarnUnimplemented("bfc", machInst);
749 return new WarnUnimplemented("bfi", machInst);
752 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) {
753 return new WarnUnimplemented("usat16", machInst);
755 // Fall through on purpose...
757 return new WarnUnimplemented("usat", machInst);
759 return new WarnUnimplemented("ubfx", machInst);
761 return new Unknown(machInst);
767 def format Thumb32DataProcShiftReg() {{
769 def decInst(mnem, dest="rd", op1="rn"):
772 return new %(mnem)sRegCc(machInst, %(dest)s,
773 %(op1)s, rm, amt, type);
775 return new %(mnem)sReg(machInst, %(dest)s,
776 %(op1)s, rm, amt, type);
778 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
782 const uint32_t op = bits(machInst, 24, 21);
783 const bool s = (bits(machInst, 20) == 1);
784 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
785 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
786 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
787 const uint32_t amt = (bits(machInst, 14, 12) << 2) |
788 bits(machInst, 7, 6);
789 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
792 if (rd == INTREG_PC) {
800 if (rn == INTREG_PC) {
806 if (rn == INTREG_PC) {
812 if (rd == INTREG_PC) {
818 return new WarnUnimplemented("pkh", machInst);
820 if (rd == INTREG_PC) {
830 if (rd == INTREG_PC) {
838 return new Unknown(machInst);
842 "tst" : decInst("Tst", "INTREG_ZERO"),
843 "and" : decInst("And"),
844 "bic" : decInst("Bic"),
845 "mov" : decInst("Mov", op1="INTREG_ZERO"),
846 "orr" : decInst("Orr"),
847 "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
848 "orn" : decInst("Orn"),
849 "teq" : decInst("Teq", "INTREG_ZERO"),
850 "eor" : decInst("Eor"),
851 "cmn" : decInst("Cmn", "INTREG_ZERO"),
852 "add" : decInst("Add"),
853 "adc" : decInst("Adc"),
854 "sbc" : decInst("Sbc"),
855 "cmp" : decInst("Cmp", "INTREG_ZERO"),
856 "sub" : decInst("Sub"),
857 "rsb" : decInst("Rsb")