1 // Copyright (c) 2010-2012 ARM Limited
4 // The license below extends only to copyright in the software and shall
5 // not be construed as granting a license to any other intellectual
6 // property including but not limited to intellectual property relating
7 // to a hardware implementation of the functionality of the software
8 // licensed hereunder. You may use the software subject to the license
9 // terms below provided that you ensure that this notice is replicated
10 // unmodified and in its entirety in all distributions of the software,
11 // modified or unmodified, in source code or in binary form.
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions are
15 // met: redistributions of source code must retain the above copyright
16 // notice, this list of conditions and the following disclaimer;
17 // redistributions in binary form must reproduce the above copyright
18 // notice, this list of conditions and the following disclaimer in the
19 // documentation and/or other materials provided with the distribution;
20 // neither the name of the copyright holders nor the names of its
21 // contributors may be used to endorse or promote products derived from
22 // this software without specific prior written permission.
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 // Authors: Gabe Black
38 def format ArmUnconditional() {{
41 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
42 const uint32_t op1 = bits(machInst, 27, 20);
43 if (bits(op1, 7) == 0) {
44 const uint32_t op2 = bits(machInst, 7, 4);
46 if (bits((uint32_t)rn, 0) == 1 && op2 == 0) {
47 return new Setend(machInst, bits(machInst, 9));
48 } else if (bits((uint32_t)rn, 0) == 0 && bits(op2, 1) == 0) {
49 const bool enable = bits(machInst, 19, 18) == 0x2;
50 const uint32_t mods = bits(machInst, 4, 0) |
51 (bits(machInst, 8, 6) << 5) |
52 (bits(machInst, 17) << 8) |
53 ((enable ? 1 : 0) << 9);
54 return new Cps(machInst, mods);
56 } else if (bits(op1, 6, 5) == 0x1) {
57 return decodeNeonData(machInst);
58 } else if (bits(op1, 6, 4) == 0x4) {
59 if (bits(op1, 0) == 0) {
60 return decodeNeonMem(machInst);
61 } else if (bits(op1, 2, 0) == 1) {
62 // Unallocated memory hint
63 return new NopInst(machInst);
64 } else if (bits(op1, 2, 0) == 5) {
65 const bool add = bits(machInst, 23);
66 const uint32_t imm12 = bits(machInst, 11, 0);
68 return new %(pli_iadd)s(machInst, INTREG_ZERO,
71 return new %(pli_isub)s(machInst, INTREG_ZERO,
75 } else if (bits(op1, 6, 4) == 0x5) {
76 if (bits(op1, 1, 0) == 0x1) {
77 const bool add = bits(machInst, 23);
78 const bool pldw = bits(machInst, 22);
79 const uint32_t imm12 = bits(machInst, 11, 0);
82 return new %(pldw_iadd)s(machInst, INTREG_ZERO,
85 return new %(pldw_isub)s(machInst, INTREG_ZERO,
90 return new %(pld_iadd)s(machInst, INTREG_ZERO,
93 return new %(pld_isub)s(machInst, INTREG_ZERO,
97 } else if (op1 == 0x57) {
100 return new Clrex(machInst);
102 return new Dsb(machInst);
104 return new Dmb(machInst);
106 return new Isb(machInst);
109 } else if (bits(op2, 0) == 0) {
110 switch (op1 & 0xf7) {
112 // Unallocated memory hint
113 return new NopInst(machInst);
116 const uint32_t imm5 = bits(machInst, 11, 7);
117 const uint32_t type = bits(machInst, 6, 5);
118 const bool add = bits(machInst, 23);
119 const IntRegIndex rm =
120 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
122 return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
123 add, imm5, type, rm);
125 return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
126 add, imm5, type, rm);
132 const uint32_t imm5 = bits(machInst, 11, 7);
133 const uint32_t type = bits(machInst, 6, 5);
134 const bool add = bits(machInst, 23);
135 const bool pldw = bits(machInst, 22);
136 const IntRegIndex rm =
137 (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
140 return new %(pldw_radd)s(machInst, INTREG_ZERO,
144 return new %(pldw_rsub)s(machInst, INTREG_ZERO,
150 return new %(pld_radd)s(machInst, INTREG_ZERO,
154 return new %(pld_rsub)s(machInst, INTREG_ZERO,
163 switch (bits(machInst, 26, 25)) {
166 const uint32_t val = ((machInst >> 20) & 0x5);
168 const uint32_t mode = bits(machInst, 4, 0);
169 if (badMode((OperatingMode)mode))
170 return new Unknown(machInst);
171 switch (bits(machInst, 24, 21)) {
173 return new %(srs)s(machInst, mode,
174 SrsOp::DecrementAfter, false);
176 return new %(srs_w)s(machInst, mode,
177 SrsOp::DecrementAfter, true);
179 return new %(srs_u)s(machInst, mode,
180 SrsOp::IncrementAfter, false);
182 return new %(srs_uw)s(machInst, mode,
183 SrsOp::IncrementAfter, true);
185 return new %(srs_p)s(machInst, mode,
186 SrsOp::DecrementBefore, false);
188 return new %(srs_pw)s(machInst, mode,
189 SrsOp::DecrementBefore, true);
191 return new %(srs_pu)s(machInst, mode,
192 SrsOp::IncrementBefore, false);
194 return new %(srs_puw)s(machInst, mode,
195 SrsOp::IncrementBefore, true);
197 return new Unknown(machInst);
198 } else if (val == 0x1) {
199 switch (bits(machInst, 24, 21)) {
201 return new %(rfe)s(machInst, rn,
202 RfeOp::DecrementAfter, false);
204 return new %(rfe_w)s(machInst, rn,
205 RfeOp::DecrementAfter, true);
207 return new %(rfe_u)s(machInst, rn,
208 RfeOp::IncrementAfter, false);
210 return new %(rfe_uw)s(machInst, rn,
211 RfeOp::IncrementAfter, true);
213 return new %(rfe_p)s(machInst, rn,
214 RfeOp::DecrementBefore, false);
216 return new %(rfe_pw)s(machInst, rn,
217 RfeOp::DecrementBefore, true);
219 return new %(rfe_pu)s(machInst, rn,
220 RfeOp::IncrementBefore, false);
222 return new %(rfe_puw)s(machInst, rn,
223 RfeOp::IncrementBefore, true);
225 return new Unknown(machInst);
232 (sext<26>(bits(machInst, 23, 0) << 2)) |
233 (bits(machInst, 24) << 1);
234 return new BlxImm(machInst, imm, COND_UC);
237 if (bits(op1, 4, 0) != 0) {
238 if (CPNUM == 0xa || CPNUM == 0xb) {
239 return decodeExtensionRegLoadStore(machInst);
241 if (bits(op1, 0) == 1) {
242 if (rn == INTREG_PC) {
243 if (bits(op1, 4, 3) != 0x0) {
244 return new WarnUnimplemented(
245 "ldc, ldc2 (literal)", machInst);
248 if (op1 == 0xC3 || op1 == 0xC7) {
249 return new WarnUnimplemented(
250 "ldc, ldc2 (immediate)", machInst);
254 return new WarnUnimplemented(
255 "mrrc, mrrc2", machInst);
258 if (bits(op1, 4, 3) != 0 || bits(op1, 1) == 1) {
259 return new WarnUnimplemented(
260 "stc, stc2", machInst);
261 } else if (op1 == 0xC4) {
262 return new WarnUnimplemented(
263 "mcrr, mcrrc", machInst);
269 if (bits(op1, 4) == 0) {
270 if (CPNUM == 0xa || CPNUM == 0xb) {
271 return decodeShortFpTransfer(machInst);
272 } else if (CPNUM == 0xe) {
273 return decodeMcrMrc14(machInst);
274 } else if (CPNUM == 0xf) {
275 return decodeMcrMrc15(machInst);
277 const bool op = bits(machInst, 4);
280 return new WarnUnimplemented(
281 "mrc, mrc2", machInst);
283 return new WarnUnimplemented(
284 "mcr, mcr2", machInst);
287 return new WarnUnimplemented("cdp, cdp2", machInst);
293 return new Unknown(machInst);
296 "pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
297 "pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
298 "pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
299 "pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
300 "pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
301 "pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
302 "pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
303 "pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
304 "pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
305 "pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
306 "pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
307 "pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1),
308 "rfe" : "RFE_" + loadImmClassName(True, False, False, 8),
309 "rfe_w" : "RFE_" + loadImmClassName(True, False, True, 8),
310 "rfe_u" : "RFE_" + loadImmClassName(True, True, False, 8),
311 "rfe_uw" : "RFE_" + loadImmClassName(True, True, True, 8),
312 "rfe_p" : "RFE_" + loadImmClassName(False, False, False, 8),
313 "rfe_pw" : "RFE_" + loadImmClassName(False, False, True, 8),
314 "rfe_pu" : "RFE_" + loadImmClassName(False, True, False, 8),
315 "rfe_puw" : "RFE_" + loadImmClassName(False, True, True, 8),
316 "srs" : "SRS_" + storeImmClassName(True, False, False, 8),
317 "srs_w" : "SRS_" + storeImmClassName(True, False, True, 8),
318 "srs_u" : "SRS_" + storeImmClassName(True, True, False, 8),
319 "srs_uw" : "SRS_" + storeImmClassName(True, True, True, 8),
320 "srs_p" : "SRS_" + storeImmClassName(False, False, False, 8),
321 "srs_pw" : "SRS_" + storeImmClassName(False, False, True, 8),
322 "srs_pu" : "SRS_" + storeImmClassName(False, True, False, 8),
323 "srs_puw" : "SRS_" + storeImmClassName(False, True, True, 8)