3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are
17 // met: redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer;
19 // redistributions in binary form must reproduce the above copyright
20 // notice, this list of conditions and the following disclaimer in the
21 // documentation and/or other materials provided with the distribution;
22 // neither the name of the copyright holders nor the names of its
23 // contributors may be used to endorse or promote products derived from
24 // this software without specific prior written permission.
26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 // Authors: Gabe Black
47 CondCodes = CondCodes | ((resTemp & 1) << 27);
51 uint16_t _ic, _iv, _iz, _in;
52 _in = (resTemp >> %(negBit)d) & 1;
54 _iv = %(ivValue)s & 1;
55 _ic = %(icValue)s & 1;
57 CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
58 (CondCodes & 0x0FFFFFFF);
60 DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
64 # Dict of code to set the carry flag. (imm, reg, reg-reg)
65 oldC = 'CondCodes<29:>'
66 oldV = 'CondCodes<28:>'
68 "none": (oldC, oldC, oldC),
69 "llbit": (oldC, oldC, oldC),
70 "saturate": ('0', '0', '0'),
71 "overflow": ('0', '0', '0'),
72 "add": ('findCarry(32, resTemp, Op1, secondOp)',
73 'findCarry(32, resTemp, Op1, secondOp)',
74 'findCarry(32, resTemp, Op1, secondOp)'),
75 "sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
76 'findCarry(32, resTemp, Op1, ~secondOp)',
77 'findCarry(32, resTemp, Op1, ~secondOp)'),
78 "rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
79 'findCarry(32, resTemp, secondOp, ~Op1)',
80 'findCarry(32, resTemp, secondOp, ~Op1)'),
81 "logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
82 'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
83 'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
85 # Dict of code to set the overflow flag.
91 "add": 'findOverflow(32, resTemp, Op1, secondOp)',
92 "sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
93 "rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
97 secondOpRe = re.compile("secondOp")
99 regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
100 regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
102 def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
103 buildCc = True, buildNonCc = True):
104 cCode = carryCode[flagType]
105 vCode = overflowCode[flagType]
107 if flagType == "llbit":
109 if flagType == "saturate":
110 immCcCode = calcQCode
112 immCcCode = calcCcCode % {
113 "icValue": secondOpRe.sub(immOp2, cCode[0]),
114 "ivValue": secondOpRe.sub(immOp2, vCode),
117 immCode = secondOpRe.sub(immOp2, code)
118 immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
120 "predicate_test": predicateTest})
121 immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
123 {"code" : immCode + immCcCode,
124 "predicate_test": predicateTest})
127 global header_output, decoder_output, exec_output
128 header_output += DataImmDeclare.subst(iop)
129 decoder_output += DataImmConstructor.subst(iop)
130 exec_output += PredOpExecute.subst(iop)
137 def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
138 buildCc = True, buildNonCc = True):
139 cCode = carryCode[flagType]
140 vCode = overflowCode[flagType]
142 if flagType == "llbit":
144 if flagType == "saturate":
145 regCcCode = calcQCode
147 regCcCode = calcCcCode % {
148 "icValue": secondOpRe.sub(regOp2, cCode[1]),
149 "ivValue": secondOpRe.sub(regOp2, vCode),
152 regCode = secondOpRe.sub(regOp2, code)
153 regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
155 "predicate_test": predicateTest})
156 regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
158 {"code" : regCode + regCcCode,
159 "predicate_test": predicateTest})
162 global header_output, decoder_output, exec_output
163 header_output += DataRegDeclare.subst(iop)
164 decoder_output += DataRegConstructor.subst(iop)
165 exec_output += PredOpExecute.subst(iop)
172 def buildRegRegDataInst(mnem, code, flagType = "logic", \
174 buildCc = True, buildNonCc = True):
175 cCode = carryCode[flagType]
176 vCode = overflowCode[flagType]
178 if flagType == "llbit":
180 if flagType == "saturate":
181 regRegCcCode = calcQCode
183 regRegCcCode = calcCcCode % {
184 "icValue": secondOpRe.sub(regRegOp2, cCode[2]),
185 "ivValue": secondOpRe.sub(regRegOp2, vCode),
188 regRegCode = secondOpRe.sub(regRegOp2, code)
189 regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
191 {"code" : regRegCode,
192 "predicate_test": predicateTest})
193 regRegIopCc = InstObjParams(mnem + "s",
194 mnem.capitalize() + suffix + "Cc",
196 {"code" : regRegCode + regRegCcCode,
197 "predicate_test": predicateTest})
200 global header_output, decoder_output, exec_output
201 header_output += DataRegRegDeclare.subst(iop)
202 decoder_output += DataRegRegConstructor.subst(iop)
203 exec_output += PredOpExecute.subst(iop)
210 def buildDataInst(mnem, code, flagType = "logic", \
211 aiw = True, regRegAiw = True,
213 regRegCode = instCode = code
215 instCode = "AIW" + instCode
217 regRegCode = "AIW" + regRegCode
219 buildImmDataInst(mnem, instCode, flagType)
220 buildRegDataInst(mnem, instCode, flagType)
221 buildRegRegDataInst(mnem, regRegCode, flagType)
225 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
226 Cpsr = ~CondCodesMask & newCpsr;
227 CondCodes = CondCodesMask & newCpsr;
229 buildImmDataInst(mnem + 's', code, flagType,
230 suffix = "ImmPclr", buildCc = False)
231 buildRegDataInst(mnem + 's', code, flagType,
232 suffix = "RegPclr", buildCc = False)
234 buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
235 buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
236 buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
237 buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
238 buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
239 buildImmDataInst("adr", '''
240 Dest = resTemp = (readPC(xc) & ~0x3) +
241 (op1 ? secondOp : -secondOp);
243 buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
244 buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
245 buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
246 buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
247 buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
248 buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
249 buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
250 buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
251 buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
252 buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
253 buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
254 buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
255 buildDataInst("movt",
256 "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
259 buildRegDataInst("qadd", '''
261 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
263 ''', flagType="saturate", buildNonCc=False)
264 buildRegDataInst("qadd16", '''
266 for (unsigned i = 0; i < 2; i++) {
267 int high = (i + 1) * 16 - 1;
269 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
270 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
271 saturateOp<16>(midRes, arg1, arg2);
272 replaceBits(resTemp, high, low, midRes);
275 ''', flagType="none", buildCc=False)
276 buildRegDataInst("qadd8", '''
278 for (unsigned i = 0; i < 4; i++) {
279 int high = (i + 1) * 8 - 1;
281 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
282 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
283 saturateOp<8>(midRes, arg1, arg2);
284 replaceBits(resTemp, high, low, midRes);
287 ''', flagType="none", buildCc=False)
288 buildRegDataInst("qdadd", '''
290 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
291 saturateOp<32>(midRes, Op1.sw, midRes);
293 ''', flagType="saturate", buildNonCc=False)
294 buildRegDataInst("qsub", '''
296 resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
298 ''', flagType="saturate")
299 buildRegDataInst("qsub16", '''
301 for (unsigned i = 0; i < 2; i++) {
302 int high = (i + 1) * 16 - 1;
304 int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
305 int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
306 saturateOp<16>(midRes, arg1, arg2, true);
307 replaceBits(resTemp, high, low, midRes);
310 ''', flagType="none", buildCc=False)
311 buildRegDataInst("qsub8", '''
313 for (unsigned i = 0; i < 4; i++) {
314 int high = (i + 1) * 8 - 1;
316 int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
317 int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
318 saturateOp<8>(midRes, arg1, arg2, true);
319 replaceBits(resTemp, high, low, midRes);
322 ''', flagType="none", buildCc=False)
323 buildRegDataInst("qdsub", '''
325 resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
326 saturateOp<32>(midRes, Op1.sw, midRes, true);
328 ''', flagType="saturate", buildNonCc=False)
329 buildRegDataInst("qasx", '''
331 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
332 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
333 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
334 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
335 saturateOp<16>(midRes, arg1Low, arg2High, true);
336 replaceBits(resTemp, 15, 0, midRes);
337 saturateOp<16>(midRes, arg1High, arg2Low);
338 replaceBits(resTemp, 31, 16, midRes);
340 ''', flagType="none", buildCc=False)
341 buildRegDataInst("qsax", '''
343 int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
344 int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
345 int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
346 int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
347 saturateOp<16>(midRes, arg1Low, arg2High);
348 replaceBits(resTemp, 15, 0, midRes);
349 saturateOp<16>(midRes, arg1High, arg2Low, true);
350 replaceBits(resTemp, 31, 16, midRes);
352 ''', flagType="none", buildCc=False)