3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Copyright (c) 2007-2008 The Florida State University
16 // All rights reserved.
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are
20 // met: redistributions of source code must retain the above copyright
21 // notice, this list of conditions and the following disclaimer;
22 // redistributions in binary form must reproduce the above copyright
23 // notice, this list of conditions and the following disclaimer in the
24 // documentation and/or other materials provided with the distribution;
25 // neither the name of the copyright holders nor the names of its
26 // contributors may be used to endorse or promote products derived from
27 // this software without specific prior written permission.
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 // Authors: Stephen Hines
44 ////////////////////////////////////////////////////////////////////
46 // Load/store microops
50 microLdrUopCode = "IWRa = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
51 microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
53 {'memacc_code': microLdrUopCode,
54 'ea_code': 'EA = URb + (up ? imm : -imm);',
55 'predicate_test': predicateTest},
58 microLdrFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
59 microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop',
61 {'memacc_code': microLdrFpUopCode,
62 'ea_code': vfpEnabledCheckCode +
63 'EA = URb + (up ? imm : -imm);',
64 'predicate_test': predicateTest},
67 microLdrDBFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
68 microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop',
70 {'memacc_code': microLdrFpUopCode,
71 'ea_code': vfpEnabledCheckCode + '''
72 EA = URb + (up ? imm : -imm) +
73 (((CPSR)Cpsr).e ? 4 : 0);
75 'predicate_test': predicateTest},
78 microLdrDTFpUopCode = "Fa.uw = cSwap(Mem.uw, ((CPSR)Cpsr).e);"
79 microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop',
81 {'memacc_code': microLdrFpUopCode,
82 'ea_code': vfpEnabledCheckCode + '''
83 EA = URb + (up ? imm : -imm) -
84 (((CPSR)Cpsr).e ? 4 : 0);
86 'predicate_test': predicateTest},
93 cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
94 Cpsr = ~CondCodesMask & newCpsr;
95 CondCodes = CondCodesMask & newCpsr;
96 IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
97 ForcedItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
98 | (((CPSR)Spsr).it1 & 0x3);
101 microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
104 microRetUopCode % 'Mem.uw',
106 'EA = URb + (up ? imm : -imm);',
107 'predicate_test': condPredicateTest},
108 ['IsMicroop','IsNonSpeculative',
111 microStrUopCode = "Mem = cSwap(URa.uw, ((CPSR)Cpsr).e);"
112 microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
114 {'memacc_code': microStrUopCode,
116 'ea_code': 'EA = URb + (up ? imm : -imm);',
117 'predicate_test': predicateTest},
120 microStrFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
121 microStrFpUopIop = InstObjParams('strfp_uop', 'MicroStrFpUop',
123 {'memacc_code': microStrFpUopCode,
125 'ea_code': vfpEnabledCheckCode +
126 'EA = URb + (up ? imm : -imm);',
127 'predicate_test': predicateTest},
130 microStrDBFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
131 microStrDBFpUopIop = InstObjParams('strfp_uop', 'MicroStrDBFpUop',
133 {'memacc_code': microStrFpUopCode,
135 'ea_code': vfpEnabledCheckCode + '''
136 EA = URb + (up ? imm : -imm) +
137 (((CPSR)Cpsr).e ? 4 : 0);
139 'predicate_test': predicateTest},
142 microStrDTFpUopCode = "Mem = cSwap(Fa.uw, ((CPSR)Cpsr).e);"
143 microStrDTFpUopIop = InstObjParams('strfp_uop', 'MicroStrDTFpUop',
145 {'memacc_code': microStrFpUopCode,
147 'ea_code': vfpEnabledCheckCode + '''
148 EA = URb + (up ? imm : -imm) -
149 (((CPSR)Cpsr).e ? 4 : 0);
151 'predicate_test': predicateTest},
154 header_output = decoder_output = exec_output = ''
156 loadIops = (microLdrUopIop, microLdrRetUopIop,
157 microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop)
158 storeIops = (microStrUopIop, microStrFpUopIop,
159 microStrDBFpUopIop, microStrDTFpUopIop)
160 for iop in loadIops + storeIops:
161 header_output += MicroMemDeclare.subst(iop)
162 decoder_output += MicroMemConstructor.subst(iop)
164 exec_output += LoadExecute.subst(iop) + \
165 LoadInitiateAcc.subst(iop) + \
166 LoadCompleteAcc.subst(iop)
167 for iop in storeIops:
168 exec_output += StoreExecute.subst(iop) + \
169 StoreInitiateAcc.subst(iop) + \
170 StoreCompleteAcc.subst(iop)
174 exec_output = header_output = ''
176 eaCode = 'EA = URa + imm;'
178 for size in (1, 2, 3, 4, 6, 8, 12, 16):
179 # Set up the memory access.
180 regs = (size + 3) // 4
181 subst = { "size" : size, "regs" : regs }
184 uint8_t bytes[%(size)d];
185 Element elements[%(size)d / sizeof(Element)];
186 uint32_t floatRegBits[%(regs)d];
190 # Do endian conversion for all the elements.
192 const unsigned eCount = sizeof(memUnion.elements) /
193 sizeof(memUnion.elements[0]);
194 if (((CPSR)Cpsr).e) {
195 for (unsigned i = 0; i < eCount; i++) {
196 memUnion.elements[i] = gtobe(memUnion.elements[i]);
199 for (unsigned i = 0; i < eCount; i++) {
200 memUnion.elements[i] = gtole(memUnion.elements[i]);
205 # Offload everything into registers
207 for reg in range(regs):
210 mask = ' & mask(%d)' % (32 - 8 * (regs * 4 - size))
212 FpDestP%(reg)d.uw = gtoh(memUnion.floatRegBits[%(reg)d])%(mask)s;
213 ''' % { "reg" : reg, "mask" : mask }
215 # Pull everything in from registers
217 for reg in range(regs):
219 memUnion.floatRegBits[%(reg)d] = htog(FpDestP%(reg)d.uw);
220 ''' % { "reg" : reg }
222 loadMemAccCode = convCode + regSetCode
223 storeMemAccCode = regGetCode + convCode
225 loadIop = InstObjParams('ldrneon%(size)d_uop' % subst,
226 'MicroLdrNeon%(size)dUop' % subst,
228 { 'mem_decl' : memDecl,
230 'memacc_code' : loadMemAccCode,
231 'ea_code' : simdEnabledCheckCode + eaCode,
232 'predicate_test' : predicateTest },
233 [ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
234 storeIop = InstObjParams('strneon%(size)d_uop' % subst,
235 'MicroStrNeon%(size)dUop' % subst,
237 { 'mem_decl' : memDecl,
239 'memacc_code' : storeMemAccCode,
240 'ea_code' : simdEnabledCheckCode + eaCode,
241 'predicate_test' : predicateTest },
242 [ 'IsMicroop', 'IsMemRef', 'IsStore' ])
244 exec_output += NeonLoadExecute.subst(loadIop) + \
245 NeonLoadInitiateAcc.subst(loadIop) + \
246 NeonLoadCompleteAcc.subst(loadIop) + \
247 NeonStoreExecute.subst(storeIop) + \
248 NeonStoreInitiateAcc.subst(storeIop) + \
249 NeonStoreCompleteAcc.subst(storeIop)
250 header_output += MicroNeonMemDeclare.subst(loadIop) + \
251 MicroNeonMemDeclare.subst(storeIop)
256 for eSize, type in (1, 'uint8_t'), \
261 # An instruction handles no more than 16 bytes and no more than
262 # 4 elements, or the number of elements needed to fill 8 or 16 bytes.
264 for count in 1, 2, 3, 4:
270 "class_name" : "MicroLdrNeon%dUop" % size,
273 exec_output += MicroNeonMemExecDeclare.subst(substDict)
274 substDict["class_name"] = "MicroStrNeon%dUop" % size
275 exec_output += MicroNeonMemExecDeclare.subst(substDict)
279 ////////////////////////////////////////////////////////////////////
281 // Neon (de)interlacing microops
285 header_output = exec_output = ''
286 for dRegs in (2, 3, 4):
289 for dReg in range(dRegs):
291 conv1.cRegs[%(sReg0)d] = htog(FpOp1P%(sReg0)d.uw);
292 conv1.cRegs[%(sReg1)d] = htog(FpOp1P%(sReg1)d.uw);
293 ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
295 FpDestS%(dReg)dP0.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 0]);
296 FpDestS%(dReg)dP1.uw = gtoh(conv2.cRegs[2 * %(dReg)d + 1]);
297 ''' % { "dReg" : dReg }
298 microDeintNeonCode = '''
299 const unsigned dRegs = %(dRegs)d;
300 const unsigned regs = 2 * dRegs;
301 const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
304 FloatRegBits cRegs[regs];
305 Element elements[dRegs * perDReg];
310 unsigned srcElem = 0;
311 for (unsigned destOffset = 0;
312 destOffset < perDReg; destOffset++) {
313 for (unsigned dReg = 0; dReg < dRegs; dReg++) {
314 conv2.elements[dReg * perDReg + destOffset] =
315 conv1.elements[srcElem++];
320 ''' % { "dRegs" : dRegs,
321 "loadConv" : loadConv,
322 "unloadConv" : unloadConv }
323 microDeintNeonIop = \
324 InstObjParams('deintneon%duop' % (dRegs * 2),
325 'MicroDeintNeon%dUop' % (dRegs * 2),
327 { 'predicate_test': predicateTest,
328 'code' : microDeintNeonCode },
330 header_output += MicroNeonMixDeclare.subst(microDeintNeonIop)
331 exec_output += MicroNeonMixExecute.subst(microDeintNeonIop)
335 for dReg in range(dRegs):
337 conv1.cRegs[2 * %(dReg)d + 0] = htog(FpOp1S%(dReg)dP0.uw);
338 conv1.cRegs[2 * %(dReg)d + 1] = htog(FpOp1S%(dReg)dP1.uw);
339 ''' % { "dReg" : dReg }
341 FpDestP%(sReg0)d.uw = gtoh(conv2.cRegs[%(sReg0)d]);
342 FpDestP%(sReg1)d.uw = gtoh(conv2.cRegs[%(sReg1)d]);
343 ''' % { "sReg0" : (dReg * 2), "sReg1" : (dReg * 2 + 1) }
344 microInterNeonCode = '''
345 const unsigned dRegs = %(dRegs)d;
346 const unsigned regs = 2 * dRegs;
347 const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
350 FloatRegBits cRegs[regs];
351 Element elements[dRegs * perDReg];
356 unsigned destElem = 0;
357 for (unsigned srcOffset = 0;
358 srcOffset < perDReg; srcOffset++) {
359 for (unsigned dReg = 0; dReg < dRegs; dReg++) {
360 conv2.elements[destElem++] =
361 conv1.elements[dReg * perDReg + srcOffset];
366 ''' % { "dRegs" : dRegs,
367 "loadConv" : loadConv,
368 "unloadConv" : unloadConv }
369 microInterNeonIop = \
370 InstObjParams('interneon%duop' % (dRegs * 2),
371 'MicroInterNeon%dUop' % (dRegs * 2),
373 { 'predicate_test': predicateTest,
374 'code' : microInterNeonCode },
376 header_output += MicroNeonMixDeclare.subst(microInterNeonIop)
377 exec_output += MicroNeonMixExecute.subst(microInterNeonIop)
382 for type in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'):
383 for dRegs in (2, 3, 4):
384 Name = "MicroDeintNeon%dUop" % (dRegs * 2)
385 substDict = { "class_name" : Name, "targs" : type }
386 exec_output += MicroNeonExecDeclare.subst(substDict)
387 Name = "MicroInterNeon%dUop" % (dRegs * 2)
388 substDict = { "class_name" : Name, "targs" : type }
389 exec_output += MicroNeonExecDeclare.subst(substDict)
392 ////////////////////////////////////////////////////////////////////
394 // Neon microops to pack/unpack a single lane
398 header_output = exec_output = ''
401 for reg in range(sRegs):
403 sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
404 sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
405 ''' % { "reg0" : (2 * reg + 0),
406 "reg1" : (2 * reg + 1) }
407 for dRegs in range(sRegs, 5):
409 loadRegs = baseLoadRegs
410 for reg in range(dRegs):
412 destRegs[%(reg)d].fRegs[0] = htog(FpDestS%(reg)dP0.uw);
413 destRegs[%(reg)d].fRegs[1] = htog(FpDestS%(reg)dP1.uw);
414 ''' % { "reg" : reg }
416 FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
417 FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
418 ''' % { "reg" : reg }
419 microUnpackNeonCode = '''
420 const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
424 FloatRegBits fRegs[2 * %(sRegs)d];
425 Element elements[%(sRegs)d * perDReg];
429 FloatRegBits fRegs[2];
430 Element elements[perDReg];
431 } destRegs[%(dRegs)d];
435 for (unsigned i = 0; i < %(dRegs)d; i++) {
436 destRegs[i].elements[lane] = sourceRegs.elements[i];
440 ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
441 "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
443 microUnpackNeonIop = \
444 InstObjParams('unpackneon%dto%duop' % (sRegs * 2, dRegs * 2),
445 'MicroUnpackNeon%dto%dUop' %
446 (sRegs * 2, dRegs * 2),
447 'MicroNeonMixLaneOp',
448 { 'predicate_test': predicateTest,
449 'code' : microUnpackNeonCode },
451 header_output += MicroNeonMixLaneDeclare.subst(microUnpackNeonIop)
452 exec_output += MicroNeonMixExecute.subst(microUnpackNeonIop)
456 for reg in range(sRegs):
458 sourceRegs.fRegs[%(reg0)d] = htog(FpOp1P%(reg0)d.uw);
459 sourceRegs.fRegs[%(reg1)d] = htog(FpOp1P%(reg1)d.uw);
460 ''' % { "reg0" : (2 * reg + 0),
461 "reg1" : (2 * reg + 1) }
462 for dRegs in range(sRegs, 5):
464 for reg in range(dRegs):
466 FpDestS%(reg)dP0.uw = gtoh(destRegs[%(reg)d].fRegs[0]);
467 FpDestS%(reg)dP1.uw = gtoh(destRegs[%(reg)d].fRegs[1]);
468 ''' % { "reg" : reg }
469 microUnpackAllNeonCode = '''
470 const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
474 FloatRegBits fRegs[2 * %(sRegs)d];
475 Element elements[%(sRegs)d * perDReg];
479 FloatRegBits fRegs[2];
480 Element elements[perDReg];
481 } destRegs[%(dRegs)d];
485 for (unsigned i = 0; i < %(dRegs)d; i++) {
486 for (unsigned j = 0; j < perDReg; j++)
487 destRegs[i].elements[j] = sourceRegs.elements[i];
491 ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
492 "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
494 microUnpackAllNeonIop = \
495 InstObjParams('unpackallneon%dto%duop' % (sRegs * 2, dRegs * 2),
496 'MicroUnpackAllNeon%dto%dUop' %
497 (sRegs * 2, dRegs * 2),
499 { 'predicate_test': predicateTest,
500 'code' : microUnpackAllNeonCode },
502 header_output += MicroNeonMixDeclare.subst(microUnpackAllNeonIop)
503 exec_output += MicroNeonMixExecute.subst(microUnpackAllNeonIop)
507 for reg in range(dRegs):
509 FpDestP%(reg0)d.uw = gtoh(destRegs.fRegs[%(reg0)d]);
510 FpDestP%(reg1)d.uw = gtoh(destRegs.fRegs[%(reg1)d]);
511 ''' % { "reg0" : (2 * reg + 0),
512 "reg1" : (2 * reg + 1) }
513 for sRegs in range(dRegs, 5):
515 for reg in range(sRegs):
517 sourceRegs[%(reg)d].fRegs[0] = htog(FpOp1S%(reg)dP0.uw);
518 sourceRegs[%(reg)d].fRegs[1] = htog(FpOp1S%(reg)dP1.uw);
519 ''' % { "reg" : reg }
520 microPackNeonCode = '''
521 const unsigned perDReg = (2 * sizeof(FloatRegBits)) /
525 FloatRegBits fRegs[2];
526 Element elements[perDReg];
527 } sourceRegs[%(sRegs)d];
530 FloatRegBits fRegs[2 * %(dRegs)d];
531 Element elements[%(dRegs)d * perDReg];
536 for (unsigned i = 0; i < %(sRegs)d; i++) {
537 destRegs.elements[i] = sourceRegs[i].elements[lane];
541 ''' % { "sRegs" : sRegs, "dRegs" : dRegs,
542 "loadRegs" : loadRegs, "unloadRegs" : unloadRegs }
545 InstObjParams('packneon%dto%duop' % (sRegs * 2, dRegs * 2),
546 'MicroPackNeon%dto%dUop' %
547 (sRegs * 2, dRegs * 2),
548 'MicroNeonMixLaneOp',
549 { 'predicate_test': predicateTest,
550 'code' : microPackNeonCode },
552 header_output += MicroNeonMixLaneDeclare.subst(microPackNeonIop)
553 exec_output += MicroNeonMixExecute.subst(microPackNeonIop)
558 for type in ('uint8_t', 'uint16_t', 'uint32_t'):
560 for dRegs in range(sRegs, 5):
561 for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
562 "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
563 "MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
564 Name = format % { "sRegs" : sRegs * 2,
565 "dRegs" : dRegs * 2 }
566 substDict = { "class_name" : Name, "targs" : type }
567 exec_output += MicroNeonExecDeclare.subst(substDict)
570 ////////////////////////////////////////////////////////////////////
572 // Integer = Integer op Immediate microops
576 microAddiUopIop = InstObjParams('addi_uop', 'MicroAddiUop',
578 {'code': 'URa = URb + imm;',
579 'predicate_test': predicateTest},
582 microAddUopIop = InstObjParams('add_uop', 'MicroAddUop',
585 '''URa = URb + shift_rm_imm(URc, shiftAmt,
589 'predicate_test': predicateTest},
592 microSubiUopIop = InstObjParams('subi_uop', 'MicroSubiUop',
594 {'code': 'URa = URb - imm;',
595 'predicate_test': predicateTest},
598 microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop',
601 '''URa = URb - shift_rm_imm(URc, shiftAmt,
605 'predicate_test': predicateTest},
608 microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov',
610 {'code': 'IWRa = URb;',
611 'predicate_test': predicateTest},
614 microUopRegMovRetIop = InstObjParams('movret_uop', 'MicroUopRegMovRet',
616 {'code': microRetUopCode % 'URb',
617 'predicate_test': predicateTest},
618 ['IsMicroop', 'IsNonSpeculative',
622 CPSR cpsrOrCondCodes = URc;
626 cpsrWriteByInstr(cpsrOrCondCodes, URb,
627 0xF, true, sctlr.nmfi);
628 Cpsr = ~CondCodesMask & newCpsr;
629 NextThumb = ((CPSR)newCpsr).t;
630 NextJazelle = ((CPSR)newCpsr).j;
631 ForcedItState = ((((CPSR)URb).it2 << 2) & 0xFC)
632 | (((CPSR)URb).it1 & 0x3);
633 CondCodes = CondCodesMask & newCpsr;
636 microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
638 {'code': setPCCPSRDecl,
639 'predicate_test': predicateTest},
642 header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
643 MicroIntImmDeclare.subst(microSubiUopIop) + \
644 MicroIntRegDeclare.subst(microAddUopIop) + \
645 MicroIntRegDeclare.subst(microSubUopIop) + \
646 MicroIntMovDeclare.subst(microUopRegMovIop) + \
647 MicroIntMovDeclare.subst(microUopRegMovRetIop) + \
648 MicroSetPCCPSRDeclare.subst(microUopSetPCCPSRIop)
650 decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \
651 MicroIntImmConstructor.subst(microSubiUopIop) + \
652 MicroIntRegConstructor.subst(microAddUopIop) + \
653 MicroIntRegConstructor.subst(microSubUopIop) + \
654 MicroIntMovConstructor.subst(microUopRegMovIop) + \
655 MicroIntMovConstructor.subst(microUopRegMovRetIop) + \
656 MicroSetPCCPSRConstructor.subst(microUopSetPCCPSRIop)
658 exec_output = PredOpExecute.subst(microAddiUopIop) + \
659 PredOpExecute.subst(microSubiUopIop) + \
660 PredOpExecute.subst(microAddUopIop) + \
661 PredOpExecute.subst(microSubUopIop) + \
662 PredOpExecute.subst(microUopRegMovIop) + \
663 PredOpExecute.subst(microUopRegMovRetIop) + \
664 PredOpExecute.subst(microUopSetPCCPSRIop)
669 iop = InstObjParams("ldmstm", "LdmStm", 'MacroMemOp', "", [])
670 header_output = MacroMemDeclare.subst(iop)
671 decoder_output = MacroMemConstructor.subst(iop)
673 iop = InstObjParams("vldmult", "VldMult", 'VldMultOp', "", [])
674 header_output += VMemMultDeclare.subst(iop)
675 decoder_output += VMemMultConstructor.subst(iop)
677 iop = InstObjParams("vldsingle", "VldSingle", 'VldSingleOp', "", [])
678 header_output += VMemSingleDeclare.subst(iop)
679 decoder_output += VMemSingleConstructor.subst(iop)
681 iop = InstObjParams("vstmult", "VstMult", 'VstMultOp', "", [])
682 header_output += VMemMultDeclare.subst(iop)
683 decoder_output += VMemMultConstructor.subst(iop)
685 iop = InstObjParams("vstsingle", "VstSingle", 'VstSingleOp', "", [])
686 header_output += VMemSingleDeclare.subst(iop)
687 decoder_output += VMemSingleConstructor.subst(iop)
689 vfpIop = InstObjParams("vldmstm", "VLdmStm", 'MacroVFPMemOp', "", [])
690 header_output += MacroVFPMemDeclare.subst(vfpIop)
691 decoder_output += MacroVFPMemConstructor.subst(vfpIop)