src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010-2013,2017-2020 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
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  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37
  38 let {{
  39
  40     svcCode = '''
  41     ThreadContext *tc = xc->tcBase();
  42
  43     bool have_semi = ArmSystem::haveSemihosting(tc);
  44     if (have_semi && Thumb && imm == ArmSemihosting::T32Imm) {
  45         // Enable gem5 extensions since we can't distinguish in thumb.
  46         ArmSystem::callSemihosting32(tc, true);
  47     } else if (have_semi && imm == ArmSemihosting::A32Imm) {
  48         ArmSystem::callSemihosting32(tc);
  49     } else if (have_semi && imm == ArmSemihosting::Gem5Imm) {
  50         ArmSystem::callSemihosting32(tc, true);
  51     } else {
  52         fault = std::make_shared<SupervisorCall>(machInst, imm);
  53     }
  54     '''
  55
  56     svcIop = InstObjParams("svc", "Svc", "ImmOp",
  57                            { "code": svcCode,
  58                              "predicate_test": predicateTest,
  59                              "thumb_semihost": '0xAB',
  60                              "arm_semihost": '0x123456' },
  61                            ["IsSyscall", "IsNonSpeculative",
  62                             "IsSerializeAfter"])
  63     header_output = ImmOpDeclare.subst(svcIop)
  64     decoder_output = SemihostConstructor.subst(svcIop)
  65     exec_output = PredOpExecute.subst(svcIop)
  66
  67     hltCode = '''
  68     ThreadContext *tc = xc->tcBase();
  69
  70     const auto semihost_imm = Thumb? 0x3C : 0xF000;
  71
  72     if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
  73         ArmSystem::callSemihosting32(tc);
  74     } else {
  75         // HLT instructions aren't implemented, so treat them as undefined
  76         // instructions.
  77         fault = std::make_shared<UndefinedInstruction>(
  78             machInst, false, mnemonic);
  79     }
  80     '''
  81
  82     hltIop = InstObjParams("hlt", "Hlt", "ImmOp",
  83                            { "code": hltCode,
  84                              "predicate_test": predicateTest,
  85                              "thumb_semihost": '0x3C',
  86                              "arm_semihost": '0xF000' },
  87                            ["IsNonSpeculative", "IsSerializeAfter"])
  88     header_output += ImmOpDeclare.subst(hltIop)
  89     decoder_output += SemihostConstructor.subst(hltIop)
  90     exec_output += PredOpExecute.subst(hltIop)
  91
  92     smcCode = '''
  93     HCR  hcr  = Hcr;
  94     CPSR cpsr = Cpsr;
  95     SCR  scr  = Scr;
  96
  97     if ((cpsr.mode != MODE_USER) && FullSystem) {
  98         if (EL2Enabled(xc->tcBase()) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
  99             fault = std::make_shared<HypervisorTrap>(machInst, 0,
 100                                                      EC_SMC_TO_HYP);
 101         } else {
 102             if (scr.scd) {
 103                 fault = disabledFault();
 104             } else {
 105                 fault = std::make_shared<SecureMonitorCall>(machInst);
 106             }
 107         }
 108     } else {
 109         fault = disabledFault();
 110     }
 111     '''
 112
 113     smcIop = InstObjParams("smc", "Smc", "PredOp",
 114                            { "code": smcCode,
 115                              "predicate_test": predicateTest },
 116                            ["IsNonSpeculative", "IsSerializeAfter"])
 117     header_output += BasicDeclare.subst(smcIop)
 118     decoder_output += BasicConstructor.subst(smcIop)
 119     exec_output += PredOpExecute.subst(smcIop)
 120
 121     hvcCode = '''
 122     HCR  hcr  = Hcr;
 123     CPSR cpsr = Cpsr;
 124     SCR  scr  = Scr;
 125
 126     // Filter out the various cases where this instruction isn't defined
 127     if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
 128         (cpsr.mode == MODE_USER) ||
 129         (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) ||
 130         (ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) {
 131         fault = disabledFault();
 132     } else {
 133         fault = std::make_shared<HypervisorCall>(machInst, imm);
 134     }
 135     '''
 136
 137     hvcIop = InstObjParams("hvc", "Hvc", "ImmOp",
 138                            { "code": hvcCode,
 139                              "predicate_test": predicateTest },
 140                            ["IsNonSpeculative", "IsSerializeAfter"])
 141     header_output += ImmOpDeclare.subst(hvcIop)
 142     decoder_output += ImmOpConstructor.subst(hvcIop)
 143     exec_output += PredOpExecute.subst(hvcIop)
 144
 145     eretCode = '''
 146         SCTLR sctlr   = Sctlr;
 147         CPSR old_cpsr = Cpsr;
 148         old_cpsr.nz   = CondCodesNZ;
 149         old_cpsr.c    = CondCodesC;
 150         old_cpsr.v    = CondCodesV;
 151         old_cpsr.ge   = CondCodesGE;
 152
 153         CPSR new_cpsr = cpsrWriteByInstr(old_cpsr, Spsr, Scr, Nsacr, 0xF,
 154                             true, sctlr.nmfi, xc->tcBase());
 155         Cpsr        = ~CondCodesMask & new_cpsr;
 156         CondCodesNZ = new_cpsr.nz;
 157         CondCodesC  = new_cpsr.c;
 158         CondCodesV  = new_cpsr.v;
 159         CondCodesGE = new_cpsr.ge;
 160
 161         NextThumb = (new_cpsr).t;
 162                     NextJazelle = (new_cpsr).j;
 163                     NextItState = (((new_cpsr).it2 << 2) & 0xFC)
 164                         | ((new_cpsr).it1 & 0x3);
 165
 166         NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
 167     '''
 168
 169     eretIop = InstObjParams("eret", "Eret", "PredOp",
 170                            { "code": eretCode,
 171                              "predicate_test": predicateTest },
 172                            ["IsNonSpeculative", "IsSerializeAfter",
 173                             "IsSquashAfter"])
 174     header_output += BasicDeclare.subst(eretIop)
 175     decoder_output += BasicConstructor.subst(eretIop)
 176     exec_output += PredOpExecute.subst(eretIop)
 177
 178     crcCode = '''
 179     constexpr uint8_t size_bytes = %(sz)d;
 180     constexpr uint32_t poly = %(polynom)s;
 181
 182     uint32_t data = htole(Op2);
 183     auto data_buffer = reinterpret_cast<uint8_t*>(&data);
 184
 185     Dest = crc32<poly>(
 186         data_buffer,   /* Message Register */
 187         Op1,           /* Initial Value  of the CRC */
 188         size_bytes     /* Size of the original Message */
 189     );
 190     '''
 191
 192     def crc32Emit(mnem, implCode, castagnoli, size):
 193         global header_output, decoder_output, exec_output
 194
 195         if castagnoli:
 196             # crc32c instructions
 197             poly = "0x1EDC6F41"
 198         else:
 199             # crc32 instructions
 200             poly = "0x04C11DB7"
 201
 202         data = {'sz' : size, 'polynom': poly}
 203
 204         instCode = implCode % data
 205
 206         crcIop = InstObjParams(mnem, mnem.capitalize(), "RegRegRegOp",
 207                                { "code": instCode,
 208                                  "predicate_test": predicateTest }, [])
 209         header_output += RegRegRegOpDeclare.subst(crcIop)
 210         decoder_output += RegRegRegOpConstructor.subst(crcIop)
 211         exec_output += PredOpExecute.subst(crcIop)
 212
 213     crc32Emit("crc32b", crcCode, False, 1);
 214     crc32Emit("crc32h", crcCode, False, 2);
 215     crc32Emit("crc32w", crcCode, False, 4);
 216     crc32Emit("crc32cb", crcCode, True, 1);
 217     crc32Emit("crc32ch", crcCode, True, 2);
 218     crc32Emit("crc32cw", crcCode, True, 4);
 219
 220 }};
 221
 222 let {{
 223
 224     header_output = decoder_output = exec_output = ""
 225
 226     mrsCpsrCode = '''
 227         CPSR cpsr = Cpsr;
 228         cpsr.nz = CondCodesNZ;
 229         cpsr.c = CondCodesC;
 230         cpsr.v = CondCodesV;
 231         cpsr.ge = CondCodesGE;
 232         Dest = cpsr & (cpsr.mode == MODE_USER ? ApsrMask : CpsrMask);
 233     '''
 234
 235     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
 236                                { "code": mrsCpsrCode,
 237                                  "predicate_test": condPredicateTest },
 238                                ["IsSerializeBefore"])
 239     header_output += MrsDeclare.subst(mrsCpsrIop)
 240     decoder_output += MrsConstructor.subst(mrsCpsrIop)
 241     exec_output += PredOpExecute.subst(mrsCpsrIop)
 242
 243     mrsSpsrCode = "Dest = Spsr"
 244     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
 245                                { "code": mrsSpsrCode,
 246                                  "predicate_test": predicateTest },
 247                                ["IsSerializeBefore"])
 248     header_output += MrsDeclare.subst(mrsSpsrIop)
 249     decoder_output += MrsConstructor.subst(mrsSpsrIop)
 250     exec_output += PredOpExecute.subst(mrsSpsrIop)
 251
 252     mrsBankedRegCode = '''
 253         bool isIntReg;
 254         int  regIdx;
 255
 256         if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
 257             if (isIntReg) {
 258                 Dest = DecodedBankedIntReg;
 259             } else {
 260                 Dest = xc->readMiscReg(regIdx);
 261             }
 262         } else {
 263             return std::make_shared<UndefinedInstruction>(machInst, false,
 264                                                           mnemonic);
 265         }
 266     '''
 267     mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp",
 268                                     { "code": mrsBankedRegCode,
 269                                       "predicate_test": predicateTest },
 270                                     ["IsSerializeBefore"])
 271     header_output += MrsBankedRegDeclare.subst(mrsBankedRegIop)
 272     decoder_output += MrsBankedRegConstructor.subst(mrsBankedRegIop)
 273     exec_output += PredOpExecute.subst(mrsBankedRegIop)
 274
 275     msrBankedRegCode = '''
 276         bool isIntReg;
 277         int  regIdx;
 278
 279         if (decodeMrsMsrBankedReg(byteMask, r, isIntReg, regIdx, Cpsr, Scr, Nsacr)) {
 280             if (isIntReg) {
 281                 // This is a bit nasty, you would have thought that
 282                 // DecodedBankedIntReg wouldn't be written to unless the
 283                 // conditions on the IF statements above are met, however if
 284                 // you look at the generated C code you'll find that they are.
 285                 // However this is safe as DecodedBankedIntReg (which is used
 286                 // in operands.isa to get the index of DecodedBankedIntReg)
 287                 // will return INTREG_DUMMY if its not a valid integer
 288                 // register, so redirecting the write to somewhere we don't
 289                 // care about.
 290                 DecodedBankedIntReg = Op1;
 291             } else {
 292                 xc->setMiscReg(regIdx, Op1);
 293             }
 294         } else {
 295             return std::make_shared<UndefinedInstruction>(machInst, false,
 296                                                           mnemonic);
 297         }
 298     '''
 299     msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
 300                                     { "code": msrBankedRegCode,
 301                                       "predicate_test": predicateTest },
 302                                     ["IsSerializeAfter", "IsNonSpeculative"])
 303     header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
 304     decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
 305     exec_output += PredOpExecute.subst(msrBankedRegIop)
 306
 307     msrCpsrRegCode = '''
 308         SCTLR sctlr = Sctlr;
 309         CPSR old_cpsr = Cpsr;
 310         old_cpsr.nz = CondCodesNZ;
 311         old_cpsr.c = CondCodesC;
 312         old_cpsr.v = CondCodesV;
 313         old_cpsr.ge = CondCodesGE;
 314
 315         CPSR new_cpsr =
 316             cpsrWriteByInstr(old_cpsr, Op1, Scr, Nsacr, byteMask, false,
 317                              sctlr.nmfi, xc->tcBase());
 318         Cpsr = ~CondCodesMask & new_cpsr;
 319         CondCodesNZ = new_cpsr.nz;
 320         CondCodesC = new_cpsr.c;
 321         CondCodesV = new_cpsr.v;
 322         CondCodesGE = new_cpsr.ge;
 323     '''
 324     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
 325                                   { "code": msrCpsrRegCode,
 326                                     "predicate_test": condPredicateTest },
 327                                   ["IsSerializeAfter","IsNonSpeculative"])
 328     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
 329     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
 330     exec_output += PredOpExecute.subst(msrCpsrRegIop)
 331
 332     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
 333     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 334                                   { "code": msrSpsrRegCode,
 335                                     "predicate_test": predicateTest },
 336                                   ["IsSerializeAfter","IsNonSpeculative"])
 337     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 338     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 339     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 340
 341     msrCpsrImmCode = '''
 342         SCTLR sctlr = Sctlr;
 343         CPSR old_cpsr = Cpsr;
 344         old_cpsr.nz = CondCodesNZ;
 345         old_cpsr.c = CondCodesC;
 346         old_cpsr.v = CondCodesV;
 347         old_cpsr.ge = CondCodesGE;
 348         CPSR new_cpsr =
 349             cpsrWriteByInstr(old_cpsr, imm, Scr, Nsacr, byteMask, false,
 350                              sctlr.nmfi, xc->tcBase());
 351         Cpsr = ~CondCodesMask & new_cpsr;
 352         CondCodesNZ = new_cpsr.nz;
 353         CondCodesC = new_cpsr.c;
 354         CondCodesV = new_cpsr.v;
 355         CondCodesGE = new_cpsr.ge;
 356     '''
 357     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 358                                   { "code": msrCpsrImmCode,
 359                                     "predicate_test": condPredicateTest },
 360                                   ["IsSerializeAfter","IsNonSpeculative"])
 361     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 362     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 363     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 364
 365     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 366     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 367                                   { "code": msrSpsrImmCode,
 368                                     "predicate_test": predicateTest },
 369                                   ["IsSerializeAfter","IsNonSpeculative"])
 370     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 371     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 372     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 373
 374     revCode = '''
 375     uint32_t val = Op1;
 376     Dest = swap_byte(val);
 377     '''
 378     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 379                            { "code": revCode,
 380                              "predicate_test": predicateTest }, [])
 381     header_output += RegRegOpDeclare.subst(revIop)
 382     decoder_output += RegRegOpConstructor.subst(revIop)
 383     exec_output += PredOpExecute.subst(revIop)
 384
 385     rev16Code = '''
 386     uint32_t val = Op1;
 387     Dest = (bits(val, 15, 8) << 0) |
 388            (bits(val, 7, 0) << 8) |
 389            (bits(val, 31, 24) << 16) |
 390            (bits(val, 23, 16) << 24);
 391     '''
 392     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 393                              { "code": rev16Code,
 394                                "predicate_test": predicateTest }, [])
 395     header_output += RegRegOpDeclare.subst(rev16Iop)
 396     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 397     exec_output += PredOpExecute.subst(rev16Iop)
 398
 399     revshCode = '''
 400     uint16_t val = Op1;
 401     Dest = sext<16>(swap_byte(val));
 402     '''
 403     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 404                              { "code": revshCode,
 405                                "predicate_test": predicateTest }, [])
 406     header_output += RegRegOpDeclare.subst(revshIop)
 407     decoder_output += RegRegOpConstructor.subst(revshIop)
 408     exec_output += PredOpExecute.subst(revshIop)
 409
 410     rbitCode = '''
 411     Dest = reverseBits(Op1);
 412     '''
 413     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 414                             { "code": rbitCode,
 415                               "predicate_test": predicateTest }, [])
 416     header_output += RegRegOpDeclare.subst(rbitIop)
 417     decoder_output += RegRegOpConstructor.subst(rbitIop)
 418     exec_output += PredOpExecute.subst(rbitIop)
 419
 420     clzCode = '''
 421         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 422     '''
 423     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 424                            { "code": clzCode,
 425                              "predicate_test": predicateTest }, [])
 426     header_output += RegRegOpDeclare.subst(clzIop)
 427     decoder_output += RegRegOpConstructor.subst(clzIop)
 428     exec_output += PredOpExecute.subst(clzIop)
 429
 430     ssatCode = '''
 431         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 432         int32_t res;
 433         if (satInt(res, operand, imm))
 434             CpsrQ = 1 << 27;
 435         Dest = res;
 436     '''
 437     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 438                             { "code": ssatCode,
 439                               "predicate_test": pickPredicate(ssatCode) }, [])
 440     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 441     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 442     exec_output += PredOpExecute.subst(ssatIop)
 443
 444     usatCode = '''
 445         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 446         int32_t res;
 447         if (uSatInt(res, operand, imm))
 448             CpsrQ = 1 << 27;
 449         Dest = res;
 450     '''
 451     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 452                             { "code": usatCode,
 453                               "predicate_test": pickPredicate(usatCode) }, [])
 454     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 455     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 456     exec_output += PredOpExecute.subst(usatIop)
 457
 458     ssat16Code = '''
 459         int32_t res;
 460         uint32_t resTemp = 0;
 461         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 462         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 463         if (satInt(res, argLow, imm))
 464             CpsrQ = 1 << 27;
 465         replaceBits(resTemp, 15, 0, res);
 466         if (satInt(res, argHigh, imm))
 467             CpsrQ = 1 << 27;
 468         replaceBits(resTemp, 31, 16, res);
 469         Dest = resTemp;
 470     '''
 471     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 472                               { "code": ssat16Code,
 473                                 "predicate_test": pickPredicate(ssat16Code) }, [])
 474     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 475     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 476     exec_output += PredOpExecute.subst(ssat16Iop)
 477
 478     usat16Code = '''
 479         int32_t res;
 480         uint32_t resTemp = 0;
 481         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 482         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 483         if (uSatInt(res, argLow, imm))
 484             CpsrQ = 1 << 27;
 485         replaceBits(resTemp, 15, 0, res);
 486         if (uSatInt(res, argHigh, imm))
 487             CpsrQ = 1 << 27;
 488         replaceBits(resTemp, 31, 16, res);
 489         Dest = resTemp;
 490     '''
 491     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 492                               { "code": usat16Code,
 493                                 "predicate_test": pickPredicate(usat16Code) }, [])
 494     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 495     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 496     exec_output += PredOpExecute.subst(usat16Iop)
 497
 498     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 499                             { "code":
 500                               "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
 501                               "predicate_test": predicateTest }, [])
 502     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 503     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 504     exec_output += PredOpExecute.subst(sxtbIop)
 505
 506     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 507                              { "code":
 508                                '''
 509                                    Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
 510                                           Op1;
 511                                ''',
 512                                "predicate_test": predicateTest }, [])
 513     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 514     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 515     exec_output += PredOpExecute.subst(sxtabIop)
 516
 517     sxtb16Code = '''
 518     uint32_t resTemp = 0;
 519     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 520     replaceBits(resTemp, 31, 16,
 521                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 522     Dest = resTemp;
 523     '''
 524     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 525                               { "code": sxtb16Code,
 526                                 "predicate_test": predicateTest }, [])
 527     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 528     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 529     exec_output += PredOpExecute.subst(sxtb16Iop)
 530
 531     sxtab16Code = '''
 532     uint32_t resTemp = 0;
 533     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 534                                         bits(Op1, 15, 0));
 535     replaceBits(resTemp, 31, 16,
 536                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 537                 bits(Op1, 31, 16));
 538     Dest = resTemp;
 539     '''
 540     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 541                                { "code": sxtab16Code,
 542                                  "predicate_test": predicateTest }, [])
 543     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 544     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 545     exec_output += PredOpExecute.subst(sxtab16Iop)
 546
 547     sxthCode = '''
 548     uint64_t rotated = (uint32_t)Op1;
 549     rotated = (rotated | (rotated << 32)) >> imm;
 550     Dest = sext<16>((uint16_t)rotated);
 551     '''
 552     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 553                               { "code": sxthCode,
 554                                 "predicate_test": predicateTest }, [])
 555     header_output += RegImmRegOpDeclare.subst(sxthIop)
 556     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 557     exec_output += PredOpExecute.subst(sxthIop)
 558
 559     sxtahCode = '''
 560     uint64_t rotated = (uint32_t)Op2;
 561     rotated = (rotated | (rotated << 32)) >> imm;
 562     Dest = sext<16>((uint16_t)rotated) + Op1;
 563     '''
 564     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 565                              { "code": sxtahCode,
 566                                "predicate_test": predicateTest }, [])
 567     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 568     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 569     exec_output += PredOpExecute.subst(sxtahIop)
 570
 571     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 572                             { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
 573                               "predicate_test": predicateTest }, [])
 574     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 575     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 576     exec_output += PredOpExecute.subst(uxtbIop)
 577
 578     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 579                              { "code":
 580                                "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
 581                                "predicate_test": predicateTest }, [])
 582     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 583     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 584     exec_output += PredOpExecute.subst(uxtabIop)
 585
 586     uxtb16Code = '''
 587     uint32_t resTemp = 0;
 588     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 589     replaceBits(resTemp, 31, 16,
 590                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 591     Dest = resTemp;
 592     '''
 593     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 594                               { "code": uxtb16Code,
 595                                 "predicate_test": predicateTest }, [])
 596     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 597     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 598     exec_output += PredOpExecute.subst(uxtb16Iop)
 599
 600     uxtab16Code = '''
 601     uint32_t resTemp = 0;
 602     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 603                                         bits(Op1, 15, 0));
 604     replaceBits(resTemp, 31, 16,
 605                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 606                 bits(Op1, 31, 16));
 607     Dest = resTemp;
 608     '''
 609     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 610                                { "code": uxtab16Code,
 611                                  "predicate_test": predicateTest }, [])
 612     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 613     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 614     exec_output += PredOpExecute.subst(uxtab16Iop)
 615
 616     uxthCode = '''
 617     uint64_t rotated = (uint32_t)Op1;
 618     rotated = (rotated | (rotated << 32)) >> imm;
 619     Dest = (uint16_t)rotated;
 620     '''
 621     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 622                               { "code": uxthCode,
 623                                 "predicate_test": predicateTest }, [])
 624     header_output += RegImmRegOpDeclare.subst(uxthIop)
 625     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 626     exec_output += PredOpExecute.subst(uxthIop)
 627
 628     uxtahCode = '''
 629     uint64_t rotated = (uint32_t)Op2;
 630     rotated = (rotated | (rotated << 32)) >> imm;
 631     Dest = (uint16_t)rotated + Op1;
 632     '''
 633     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 634                              { "code": uxtahCode,
 635                                "predicate_test": predicateTest }, [])
 636     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 637     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 638     exec_output += PredOpExecute.subst(uxtahIop)
 639
 640     selCode = '''
 641         uint32_t resTemp = 0;
 642         for (unsigned i = 0; i < 4; i++) {
 643             int low = i * 8;
 644             int high = low + 7;
 645             replaceBits(resTemp, high, low,
 646                         bits(CondCodesGE, i) ?
 647                             bits(Op1, high, low) : bits(Op2, high, low));
 648         }
 649         Dest = resTemp;
 650     '''
 651     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 652                            { "code": selCode,
 653                              "predicate_test": predicateTest }, [])
 654     header_output += RegRegRegOpDeclare.subst(selIop)
 655     decoder_output += RegRegRegOpConstructor.subst(selIop)
 656     exec_output += PredOpExecute.subst(selIop)
 657
 658     usad8Code = '''
 659         uint32_t resTemp = 0;
 660         for (unsigned i = 0; i < 4; i++) {
 661             int low = i * 8;
 662             int high = low + 7;
 663             int32_t diff = bits(Op1, high, low) -
 664                            bits(Op2, high, low);
 665             resTemp += ((diff < 0) ? -diff : diff);
 666         }
 667         Dest = resTemp;
 668     '''
 669     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 670                              { "code": usad8Code,
 671                                "predicate_test": predicateTest }, [])
 672     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 673     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 674     exec_output += PredOpExecute.subst(usad8Iop)
 675
 676     usada8Code = '''
 677         uint32_t resTemp = 0;
 678         for (unsigned i = 0; i < 4; i++) {
 679             int low = i * 8;
 680             int high = low + 7;
 681             int32_t diff = bits(Op1, high, low) -
 682                            bits(Op2, high, low);
 683             resTemp += ((diff < 0) ? -diff : diff);
 684         }
 685         Dest = Op3 + resTemp;
 686     '''
 687     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 688                               { "code": usada8Code,
 689                                 "predicate_test": predicateTest }, [])
 690     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 691     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 692     exec_output += PredOpExecute.subst(usada8Iop)
 693
 694     bkptCode = '''
 695         uint16_t imm16;
 696         if (!machInst.thumb)
 697             imm16 = ((bits(machInst, 19, 8) << 4) | bits(machInst, 3, 0));
 698         else
 699             imm16 = bits(machInst, 7, 0);
 700
 701         return softwareBreakpoint32(xc, imm16);
 702     '''
 703     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 704     header_output += BasicDeclare.subst(bkptIop)
 705     decoder_output += BasicConstructor.subst(bkptIop)
 706     exec_output += BasicExecute.subst(bkptIop)
 707
 708     nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", ['IsNop'])
 709     header_output += BasicDeclare.subst(nopIop)
 710     decoder_output += BasicConstructor64.subst(nopIop)
 711     exec_output += BasicExecute.subst(nopIop)
 712
 713     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 714             { "code" : "", "predicate_test" : predicateTest })
 715     header_output += BasicDeclare.subst(yieldIop)
 716     decoder_output += BasicConstructor.subst(yieldIop)
 717     exec_output += PredOpExecute.subst(yieldIop)
 718
 719     wfeCode = '''
 720     CPSR cpsr = Cpsr;
 721     SCR  scr  = Scr64;
 722
 723     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending,
 724     ThreadContext *tc = xc->tcBase();
 725     Tick next_cycle = tc->getCpuPtr()->nextCycle();
 726     if (SevMailbox == 1) {
 727         SevMailbox = 0;
 728         tc->quiesceTick(next_cycle + 1);
 729     } else if (tc->getCpuPtr()->getInterruptController(
 730                 tc->threadId())->checkInterrupts()) {
 731         tc->quiesceTick(next_cycle + 1);
 732     } else {
 733         fault = trapWFx(tc, cpsr, scr, true);
 734         if (fault == NoFault) {
 735             tc->quiesce();
 736         } else {
 737             tc->quiesceTick(next_cycle + 1);
 738         }
 739     }
 740     '''
 741     wfePredFixUpCode = '''
 742     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
 743     // and SEV interrupts
 744     SevMailbox = 1;
 745     '''
 746     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 747             { "code" : wfeCode,
 748               "pred_fixup" : wfePredFixUpCode,
 749               "predicate_test" : predicateTest },
 750             ["IsNonSpeculative", "IsQuiesce",
 751              "IsSerializeAfter", "IsUnverifiable"])
 752     header_output += BasicDeclare.subst(wfeIop)
 753     decoder_output += BasicConstructor.subst(wfeIop)
 754     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 755
 756     wfiCode = '''
 757     HCR  hcr  = Hcr;
 758     CPSR cpsr = Cpsr;
 759     SCR  scr  = Scr64;
 760
 761     // WFI doesn't sleep if interrupts are pending (masked or not)
 762     ThreadContext *tc = xc->tcBase();
 763     auto *ic = dynamic_cast<ArmISA::Interrupts *>(
 764             tc->getCpuPtr()->getInterruptController(tc->threadId()));
 765     Tick next_cycle = tc->getCpuPtr()->nextCycle();
 766     if (ic->checkWfiWake(hcr, cpsr, scr)) {
 767         tc->quiesceTick(next_cycle + 1);
 768     } else {
 769         fault = trapWFx(tc, cpsr, scr, false);
 770         if (fault == NoFault) {
 771             tc->quiesce();
 772             ArmSystem::callSetStandByWfi(tc);
 773         } else {
 774             tc->quiesceTick(next_cycle + 1);
 775         }
 776     }
 777     tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
 778     '''
 779     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 780             { "code" : wfiCode, "predicate_test" : predicateTest },
 781             ["IsNonSpeculative", "IsQuiesce",
 782              "IsSerializeAfter", "IsUnverifiable"])
 783     header_output += BasicDeclare.subst(wfiIop)
 784     decoder_output += BasicConstructor.subst(wfiIop)
 785     exec_output += QuiescePredOpExecute.subst(wfiIop)
 786
 787     sevCode = '''
 788     SevMailbox = 1;
 789     System *sys = xc->tcBase()->getSystemPtr();
 790     for (int x = 0; x < sys->threads.size(); x++) {
 791         ThreadContext *oc = sys->threads[x];
 792         if (oc == xc->tcBase())
 793             continue;
 794
 795         // Wake CPU with interrupt if they were sleeping
 796         sendEvent(oc);
 797     }
 798     '''
 799     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 800             { "code" : sevCode, "predicate_test" : predicateTest },
 801             ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
 802     header_output += BasicDeclare.subst(sevIop)
 803     decoder_output += BasicConstructor.subst(sevIop)
 804     exec_output += PredOpExecute.subst(sevIop)
 805
 806     sevlCode = '''
 807     SevMailbox = 1;
 808     '''
 809     sevlIop = InstObjParams("sevl", "SevlInst", "PredOp", \
 810             { "code" : sevlCode, "predicate_test" : predicateTest },
 811             ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
 812     header_output += BasicDeclare.subst(sevlIop)
 813     decoder_output += BasicConstructor.subst(sevlIop)
 814     exec_output += BasicExecute.subst(sevlIop)
 815
 816     itIop = InstObjParams("it", "ItInst", "PredOp", \
 817             { "code" : ";",
 818               "predicate_test" : predicateTest }, [])
 819     header_output += BasicDeclare.subst(itIop)
 820     decoder_output += BasicConstructor.subst(itIop)
 821     exec_output += PredOpExecute.subst(itIop)
 822     unknownCode = '''
 823         return std::make_shared<UndefinedInstruction>(machInst, true);
 824     '''
 825     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 826                                { "code": unknownCode,
 827                                  "predicate_test": predicateTest })
 828     header_output += BasicDeclare.subst(unknownIop)
 829     decoder_output += BasicConstructor.subst(unknownIop)
 830     exec_output += PredOpExecute.subst(unknownIop)
 831
 832     ubfxCode = '''
 833         Dest = bits(Op1, imm2, imm1);
 834     '''
 835     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 836                             { "code": ubfxCode,
 837                               "predicate_test": predicateTest }, [])
 838     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 839     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 840     exec_output += PredOpExecute.subst(ubfxIop)
 841
 842     sbfxCode = '''
 843         int32_t resTemp = bits(Op1, imm2, imm1);
 844         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 845     '''
 846     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 847                             { "code": sbfxCode,
 848                               "predicate_test": predicateTest }, [])
 849     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 850     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 851     exec_output += PredOpExecute.subst(sbfxIop)
 852
 853     bfcCode = '''
 854         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 855     '''
 856     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 857                            { "code": bfcCode,
 858                              "predicate_test": predicateTest }, [])
 859     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 860     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 861     exec_output += PredOpExecute.subst(bfcIop)
 862
 863     bfiCode = '''
 864         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 865         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 866     '''
 867     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 868                            { "code": bfiCode,
 869                              "predicate_test": predicateTest }, [])
 870     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 871     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 872     exec_output += PredOpExecute.subst(bfiIop)
 873
 874     mrc14code = '''
 875     MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
 876                                RegId(MiscRegClass, op1)).index();
 877     bool can_read, undefined;
 878     std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
 879                                                      xc->tcBase());
 880     if (!can_read || undefined) {
 881         return std::make_shared<UndefinedInstruction>(machInst, false,
 882                                                       mnemonic);
 883     }
 884     if (mcrMrc14TrapToHyp((MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr,
 885                           Hstr, Hcptr, imm)) {
 886         return std::make_shared<HypervisorTrap>(machInst, imm,
 887                                                 EC_TRAPPED_CP14_MCR_MRC);
 888     }
 889     Dest = MiscOp1;
 890     '''
 891
 892     mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
 893                              { "code": mrc14code,
 894                                "predicate_test": predicateTest }, [])
 895     header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
 896     decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
 897     exec_output += PredOpExecute.subst(mrc14Iop)
 898
 899
 900     mcr14code = '''
 901     MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
 902                                RegId(MiscRegClass, dest)).index();
 903     bool can_write, undefined;
 904     std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
 905                                                        xc->tcBase());
 906     if (undefined || !can_write) {
 907         return std::make_shared<UndefinedInstruction>(machInst, false,
 908                                                       mnemonic);
 909     }
 910     if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
 911                           Hstr, Hcptr, imm)) {
 912         return std::make_shared<HypervisorTrap>(machInst, imm,
 913                                                 EC_TRAPPED_CP14_MCR_MRC);
 914     }
 915     MiscDest = Op1;
 916     '''
 917     mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
 918                              { "code": mcr14code,
 919                                "predicate_test": predicateTest },
 920                                ["IsSerializeAfter","IsNonSpeculative"])
 921     header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
 922     decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
 923     exec_output += PredOpExecute.subst(mcr14Iop)
 924
 925     mrc15code = '''
 926     int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 927     MiscRegIndex miscReg = (MiscRegIndex)
 928                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
 929                                                       preFlatOp1)).index();
 930
 931     Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
 932
 933     bool can_read, undefined;
 934     std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
 935                                                      xc->tcBase());
 936     // if we're in non secure PL1 mode then we can trap regargless of whether
 937     // the register is accessable, in other modes we trap if only if the register
 938     // IS accessable.
 939     if (undefined || (!can_read && !(fault != NoFault && !inUserMode(Cpsr) &&
 940                                     !isSecure(xc->tcBase())))) {
 941         return std::make_shared<UndefinedInstruction>(machInst, false,
 942                                                       mnemonic);
 943     }
 944     if (fault != NoFault) {
 945         return fault;
 946     }
 947     Dest = MiscNsBankedOp1;
 948     '''
 949
 950     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp",
 951                              { "code": mrc15code,
 952                                "predicate_test": predicateTest }, [])
 953     header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop)
 954     decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop)
 955     exec_output += PredOpExecute.subst(mrc15Iop)
 956
 957
 958     mcr15code = '''
 959     int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 960     MiscRegIndex miscReg = (MiscRegIndex)
 961                        xc->tcBase()->flattenRegId(RegId(MiscRegClass,
 962                                                   preFlatDest)).index();
 963
 964     Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
 965
 966     bool can_write, undefined;
 967     std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
 968                                                        xc->tcBase());
 969
 970     // if we're in non secure PL1 mode then we can trap regargless of whether
 971     // the register is accessable, in other modes we trap if only if the register
 972     // IS accessable.
 973     if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
 974                                       !isSecure(xc->tcBase())))) {
 975         return std::make_shared<UndefinedInstruction>(machInst, false,
 976                                                       mnemonic);
 977     }
 978     if (fault != NoFault) {
 979         return fault;
 980     }
 981     MiscNsBankedDest = Op1;
 982     '''
 983     mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
 984                              { "code": mcr15code,
 985                                "predicate_test": predicateTest },
 986                                ["IsSerializeAfter","IsNonSpeculative"])
 987     header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop)
 988     decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop)
 989     exec_output += PredOpExecute.subst(mcr15Iop)
 990
 991
 992     mrrc15code = '''
 993     int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 994     MiscRegIndex miscReg = (MiscRegIndex)
 995                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
 996                                                       preFlatOp1)).index();
 997
 998     Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
 999
1000     bool can_read, undefined;
1001     std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr,
1002                                                      xc->tcBase());
1003     // if we're in non secure PL1 mode then we can trap regargless of whether
1004     // the register is accessable, in other modes we trap if only if the register
1005     // IS accessable.
1006     if (undefined || (!can_read && !(fault != NoFault && !inUserMode(Cpsr) &&
1007                                      !isSecure(xc->tcBase())))) {
1008         return std::make_shared<UndefinedInstruction>(machInst, false,
1009                                                       mnemonic);
1010     }
1011     if (fault != NoFault) {
1012         return fault;
1013     }
1014     Dest = bits(MiscNsBankedOp164, 63, 32);
1015     Dest2 = bits(MiscNsBankedOp164, 31, 0);
1016     '''
1017     mrrc15Iop = InstObjParams("mrrc", "Mrrc15", "MrrcOp",
1018                               { "code": mrrc15code,
1019                                 "predicate_test": predicateTest }, [])
1020     header_output += MrrcOpDeclare.subst(mrrc15Iop)
1021     decoder_output += MrrcOpConstructor.subst(mrrc15Iop)
1022     exec_output += PredOpExecute.subst(mrrc15Iop)
1023
1024
1025     mcrr15code = '''
1026     int preFlatDest = snsBankedIndex(dest, xc->tcBase());
1027     MiscRegIndex miscReg = (MiscRegIndex)
1028                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
1029                                                       preFlatDest)).index();
1030
1031     Fault fault = mcrrMrrc15Trap(miscReg, machInst, xc->tcBase(), imm);
1032
1033     bool can_write, undefined;
1034     std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
1035                                                        xc->tcBase());
1036
1037     // if we're in non secure PL1 mode then we can trap regargless of whether
1038     // the register is accessable, in other modes we trap if only if the register
1039     // IS accessable.
1040     if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
1041                                      !isSecure(xc->tcBase())))) {
1042         return std::make_shared<UndefinedInstruction>(machInst, false,
1043                                                       mnemonic);
1044     }
1045     if (fault != NoFault) {
1046         return fault;
1047     }
1048     MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2;
1049     '''
1050     mcrr15Iop = InstObjParams("mcrr", "Mcrr15", "McrrOp",
1051                               { "code": mcrr15code,
1052                                 "predicate_test": predicateTest }, [])
1053     header_output += McrrOpDeclare.subst(mcrr15Iop)
1054     decoder_output += McrrOpConstructor.subst(mcrr15Iop)
1055     exec_output += PredOpExecute.subst(mcrr15Iop)
1056
1057
1058     enterxCode = '''
1059         NextThumb = true;
1060         NextJazelle = true;
1061     '''
1062     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
1063                               { "code": enterxCode,
1064                                 "predicate_test": predicateTest }, [])
1065     header_output += BasicDeclare.subst(enterxIop)
1066     decoder_output += BasicConstructor.subst(enterxIop)
1067     exec_output += PredOpExecute.subst(enterxIop)
1068
1069     leavexCode = '''
1070         NextThumb = true;
1071         NextJazelle = false;
1072     '''
1073     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
1074                               { "code": leavexCode,
1075                                 "predicate_test": predicateTest }, [])
1076     header_output += BasicDeclare.subst(leavexIop)
1077     decoder_output += BasicConstructor.subst(leavexIop)
1078     exec_output += PredOpExecute.subst(leavexIop)
1079
1080     setendCode = '''
1081         CPSR cpsr = Cpsr;
1082         cpsr.e = imm;
1083         Cpsr = cpsr;
1084         fault = checkSETENDEnabled(xc->tcBase(), cpsr);
1085     '''
1086     setendIop = InstObjParams("setend", "Setend", "ImmOp",
1087                               { "code": setendCode,
1088                                 "predicate_test": predicateTest },
1089                               ["IsSerializeAfter","IsNonSpeculative"])
1090     header_output += ImmOpDeclare.subst(setendIop)
1091     decoder_output += ImmOpConstructor.subst(setendIop)
1092     exec_output += PredOpExecute.subst(setendIop)
1093
1094     clrexCode = '''
1095         LLSCLock = 0;
1096     '''
1097     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
1098                              { "code": clrexCode,
1099                                "predicate_test": predicateTest },[])
1100     header_output += BasicDeclare.subst(clrexIop)
1101     decoder_output += BasicConstructor.subst(clrexIop)
1102     exec_output += PredOpExecute.subst(clrexIop)
1103
1104     McrDcCheckCode = '''
1105         int preFlatDest = snsBankedIndex(dest, xc->tcBase());
1106         MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
1107             RegId(MiscRegClass, preFlatDest)).index();
1108
1109         bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
1110
1111         bool can_write, undefined;
1112         std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr,
1113                                                            xc->tcBase());
1114
1115         // if we're in non secure PL1 mode then we can trap regardless
1116         // of whether the register is accessible, in other modes we
1117         // trap if only if the register IS accessible.
1118         if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
1119                                          !isSecure(xc->tcBase())))) {
1120             return std::make_shared<UndefinedInstruction>(machInst, false,
1121                                                           mnemonic);
1122         }
1123         if (hypTrap) {
1124             return std::make_shared<HypervisorTrap>(machInst, imm,
1125                                                     EC_TRAPPED_CP15_MCR_MRC);
1126         }
1127     '''
1128
1129     McrDcimvacCode = '''
1130         const Request::Flags memAccessFlags(Request::INVALIDATE |
1131                                             Request::DST_POC);
1132         EA = Op1;
1133     '''
1134     McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
1135                                   "MiscRegRegImmOp",
1136                                   {"memacc_code": McrDcCheckCode,
1137                                    "postacc_code": "",
1138                                    "ea_code": McrDcimvacCode,
1139                                    "predicate_test": predicateTest},
1140                                 ['IsMemRef', 'IsStore'])
1141     header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
1142     decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
1143     exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
1144                    Mcr15InitiateAcc.subst(McrDcimvacIop) + \
1145                    Mcr15CompleteAcc.subst(McrDcimvacIop)
1146
1147     McrDccmvacCode = '''
1148         const Request::Flags memAccessFlags(Request::CLEAN |
1149                                             Request::DST_POC);
1150         EA = Op1;
1151     '''
1152     McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
1153                                   "MiscRegRegImmOp",
1154                                   {"memacc_code": McrDcCheckCode,
1155                                    "postacc_code": "",
1156                                    "ea_code": McrDccmvacCode,
1157                                    "predicate_test": predicateTest},
1158                                 ['IsMemRef', 'IsStore'])
1159     header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
1160     decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
1161     exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
1162                    Mcr15InitiateAcc.subst(McrDccmvacIop) + \
1163                    Mcr15CompleteAcc.subst(McrDccmvacIop)
1164
1165     McrDccmvauCode = '''
1166         const Request::Flags memAccessFlags(Request::CLEAN |
1167                                             Request::DST_POU);
1168         EA = Op1;
1169     '''
1170     McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
1171                                   "MiscRegRegImmOp",
1172                                   {"memacc_code": McrDcCheckCode,
1173                                    "postacc_code": "",
1174                                    "ea_code": McrDccmvauCode,
1175                                    "predicate_test": predicateTest},
1176                                 ['IsMemRef', 'IsStore'])
1177     header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
1178     decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
1179     exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
1180                    Mcr15InitiateAcc.subst(McrDccmvauIop) + \
1181                    Mcr15CompleteAcc.subst(McrDccmvauIop)
1182
1183     McrDccimvacCode = '''
1184         const Request::Flags memAccessFlags(Request::CLEAN |
1185                                             Request::INVALIDATE |
1186                                             Request::DST_POC);
1187         EA = Op1;
1188     '''
1189     McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
1190                                   "MiscRegRegImmOp",
1191                                   {"memacc_code": McrDcCheckCode,
1192                                    "postacc_code": "",
1193                                    "ea_code": McrDccimvacCode,
1194                                    "predicate_test": predicateTest},
1195                                 ['IsMemRef', 'IsStore'])
1196     header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
1197     decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
1198     exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
1199                    Mcr15InitiateAcc.subst(McrDccimvacIop) + \
1200                    Mcr15CompleteAcc.subst(McrDccimvacIop)
1201
1202     isbCode = '''
1203         // If the barrier is due to a CP15 access check for hyp traps
1204         if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
1205             xc->tcBase(), imm)) {
1206             return std::make_shared<HypervisorTrap>(machInst, imm,
1207                 EC_TRAPPED_CP15_MCR_MRC);
1208         }
1209     '''
1210     isbIop = InstObjParams("isb", "Isb", "ImmOp",
1211                              {"code": isbCode,
1212                                "predicate_test": predicateTest},
1213                                 ['IsSquashAfter'])
1214     header_output += ImmOpDeclare.subst(isbIop)
1215     decoder_output += ImmOpConstructor.subst(isbIop)
1216     exec_output += PredOpExecute.subst(isbIop)
1217
1218     dsbCode = '''
1219         // If the barrier is due to a CP15 access check for hyp traps
1220         if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
1221             xc->tcBase(), imm)) {
1222             return std::make_shared<HypervisorTrap>(machInst, imm,
1223                 EC_TRAPPED_CP15_MCR_MRC);
1224         }
1225     '''
1226     dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
1227                              {"code": dsbCode,
1228                                "predicate_test": predicateTest},
1229                               ['IsMemBarrier', 'IsSerializeAfter'])
1230     header_output += ImmOpDeclare.subst(dsbIop)
1231     decoder_output += ImmOpConstructor.subst(dsbIop)
1232     exec_output += PredOpExecute.subst(dsbIop)
1233
1234     dmbCode = '''
1235         // If the barrier is due to a CP15 access check for hyp traps
1236         if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB,
1237             xc->tcBase(), imm)) {
1238             return std::make_shared<HypervisorTrap>(machInst, imm,
1239                 EC_TRAPPED_CP15_MCR_MRC);
1240         }
1241     '''
1242     dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
1243                              {"code": dmbCode,
1244                                "predicate_test": predicateTest},
1245                                ['IsMemBarrier'])
1246     header_output += ImmOpDeclare.subst(dmbIop)
1247     decoder_output += ImmOpConstructor.subst(dmbIop)
1248     exec_output += PredOpExecute.subst(dmbIop)
1249
1250     dbgCode = '''
1251     '''
1252     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
1253                              {"code": dbgCode,
1254                                "predicate_test": predicateTest})
1255     header_output += BasicDeclare.subst(dbgIop)
1256     decoder_output += BasicConstructor.subst(dbgIop)
1257     exec_output += PredOpExecute.subst(dbgIop)
1258
1259     cpsCode = '''
1260     uint32_t mode = bits(imm, 4, 0);
1261     uint32_t f = bits(imm, 5);
1262     uint32_t i = bits(imm, 6);
1263     uint32_t a = bits(imm, 7);
1264     bool setMode = bits(imm, 8);
1265     bool enable = bits(imm, 9);
1266     CPSR cpsr = Cpsr;
1267     SCTLR sctlr = Sctlr;
1268     if (cpsr.mode != MODE_USER) {
1269         if (enable) {
1270             if (f) cpsr.f = 0;
1271             if (i) cpsr.i = 0;
1272             if (a) cpsr.a = 0;
1273         } else {
1274             if (f && !sctlr.nmfi) cpsr.f = 1;
1275             if (i) cpsr.i = 1;
1276             if (a) cpsr.a = 1;
1277         }
1278         if (setMode) {
1279             cpsr.mode = mode;
1280         }
1281     }
1282     Cpsr = cpsr;
1283     '''
1284     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
1285                            { "code": cpsCode,
1286                              "predicate_test": predicateTest },
1287                            ["IsSerializeAfter","IsNonSpeculative"])
1288     header_output += ImmOpDeclare.subst(cpsIop)
1289     decoder_output += ImmOpConstructor.subst(cpsIop)
1290     exec_output += PredOpExecute.subst(cpsIop)
1291 }};