src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
  64     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  65                                { "code": mrsCpsrCode,
  66                                  "predicate_test": condPredicateTest },
  67                                ["IsSerializeBefore"])
  68     header_output += MrsDeclare.subst(mrsCpsrIop)
  69     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  70     exec_output += PredOpExecute.subst(mrsCpsrIop)
  71
  72     mrsSpsrCode = "Dest = Spsr"
  73     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  74                                { "code": mrsSpsrCode,
  75                                  "predicate_test": predicateTest },
  76                                ["IsSerializeBefore"])
  77     header_output += MrsDeclare.subst(mrsSpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  79     exec_output += PredOpExecute.subst(mrsSpsrIop)
  80
  81     msrCpsrRegCode = '''
  82         SCTLR sctlr = Sctlr;
  83         uint32_t newCpsr =
  84             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
  85         Cpsr = ~CondCodesMask & newCpsr;
  86         CondCodes = CondCodesMask & newCpsr;
  87     '''
  88     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
  89                                   { "code": msrCpsrRegCode,
  90                                     "predicate_test": condPredicateTest },
  91                                   ["IsSerializeAfter","IsNonSpeculative"])
  92     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
  93     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
  94     exec_output += PredOpExecute.subst(msrCpsrRegIop)
  95
  96     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
  97     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
  98                                   { "code": msrSpsrRegCode,
  99                                     "predicate_test": predicateTest },
 100                                   ["IsSerializeAfter","IsNonSpeculative"])
 101     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 102     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 103     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 104
 105     msrCpsrImmCode = '''
 106         SCTLR sctlr = Sctlr;
 107         uint32_t newCpsr =
 108             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
 109         Cpsr = ~CondCodesMask & newCpsr;
 110         CondCodes = CondCodesMask & newCpsr;
 111     '''
 112     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 113                                   { "code": msrCpsrImmCode,
 114                                     "predicate_test": condPredicateTest },
 115                                   ["IsSerializeAfter","IsNonSpeculative"])
 116     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 117     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 118     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 119
 120     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 121     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 122                                   { "code": msrSpsrImmCode,
 123                                     "predicate_test": predicateTest },
 124                                   ["IsSerializeAfter","IsNonSpeculative"])
 125     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 126     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 127     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 128
 129     revCode = '''
 130     uint32_t val = Op1;
 131     Dest = swap_byte(val);
 132     '''
 133     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 134                            { "code": revCode,
 135                              "predicate_test": predicateTest }, [])
 136     header_output += RegRegOpDeclare.subst(revIop)
 137     decoder_output += RegRegOpConstructor.subst(revIop)
 138     exec_output += PredOpExecute.subst(revIop)
 139
 140     rev16Code = '''
 141     uint32_t val = Op1;
 142     Dest = (bits(val, 15, 8) << 0) |
 143            (bits(val, 7, 0) << 8) |
 144            (bits(val, 31, 24) << 16) |
 145            (bits(val, 23, 16) << 24);
 146     '''
 147     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 148                              { "code": rev16Code,
 149                                "predicate_test": predicateTest }, [])
 150     header_output += RegRegOpDeclare.subst(rev16Iop)
 151     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 152     exec_output += PredOpExecute.subst(rev16Iop)
 153
 154     revshCode = '''
 155     uint16_t val = Op1;
 156     Dest = sext<16>(swap_byte(val));
 157     '''
 158     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 159                              { "code": revshCode,
 160                                "predicate_test": predicateTest }, [])
 161     header_output += RegRegOpDeclare.subst(revshIop)
 162     decoder_output += RegRegOpConstructor.subst(revshIop)
 163     exec_output += PredOpExecute.subst(revshIop)
 164
 165     rbitCode = '''
 166     uint8_t *opBytes = (uint8_t *)&Op1;
 167     uint32_t resTemp;
 168     uint8_t *destBytes = (uint8_t *)&resTemp;
 169     // This reverses the bytes and bits of the input, or so says the
 170     // internet.
 171     for (int i = 0; i < 4; i++) {
 172         uint32_t temp = opBytes[i];
 173         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 174         destBytes[3 - i] = (temp * 0x10101) >> 16;
 175     }
 176     Dest = resTemp;
 177     '''
 178     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 179                             { "code": rbitCode,
 180                               "predicate_test": predicateTest }, [])
 181     header_output += RegRegOpDeclare.subst(rbitIop)
 182     decoder_output += RegRegOpConstructor.subst(rbitIop)
 183     exec_output += PredOpExecute.subst(rbitIop)
 184
 185     clzCode = '''
 186         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 187     '''
 188     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 189                            { "code": clzCode,
 190                              "predicate_test": predicateTest }, [])
 191     header_output += RegRegOpDeclare.subst(clzIop)
 192     decoder_output += RegRegOpConstructor.subst(clzIop)
 193     exec_output += PredOpExecute.subst(clzIop)
 194
 195     ssatCode = '''
 196         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 197         int32_t res;
 198         if (satInt(res, operand, imm))
 199             CondCodes = CondCodes | (1 << 27);
 200         else
 201             CondCodes = CondCodes;
 202         Dest = res;
 203     '''
 204     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 205                             { "code": ssatCode,
 206                               "predicate_test": condPredicateTest }, [])
 207     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 208     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 209     exec_output += PredOpExecute.subst(ssatIop)
 210
 211     usatCode = '''
 212         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 213         int32_t res;
 214         if (uSatInt(res, operand, imm))
 215             CondCodes = CondCodes | (1 << 27);
 216         else
 217             CondCodes = CondCodes;
 218         Dest = res;
 219     '''
 220     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 221                             { "code": usatCode,
 222                               "predicate_test": condPredicateTest }, [])
 223     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 224     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 225     exec_output += PredOpExecute.subst(usatIop)
 226
 227     ssat16Code = '''
 228         int32_t res;
 229         uint32_t resTemp = 0;
 230         CondCodes = CondCodes;
 231         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 232         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 233         if (satInt(res, argLow, imm))
 234             CondCodes = CondCodes | (1 << 27);
 235         replaceBits(resTemp, 15, 0, res);
 236         if (satInt(res, argHigh, imm))
 237             CondCodes = CondCodes | (1 << 27);
 238         replaceBits(resTemp, 31, 16, res);
 239         Dest = resTemp;
 240     '''
 241     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 242                               { "code": ssat16Code,
 243                                 "predicate_test": condPredicateTest }, [])
 244     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 245     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 246     exec_output += PredOpExecute.subst(ssat16Iop)
 247
 248     usat16Code = '''
 249         int32_t res;
 250         uint32_t resTemp = 0;
 251         CondCodes = CondCodes;
 252         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 253         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 254         if (uSatInt(res, argLow, imm))
 255             CondCodes = CondCodes | (1 << 27);
 256         replaceBits(resTemp, 15, 0, res);
 257         if (uSatInt(res, argHigh, imm))
 258             CondCodes = CondCodes | (1 << 27);
 259         replaceBits(resTemp, 31, 16, res);
 260         Dest = resTemp;
 261     '''
 262     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 263                               { "code": usat16Code,
 264                                 "predicate_test": condPredicateTest }, [])
 265     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 266     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 267     exec_output += PredOpExecute.subst(usat16Iop)
 268
 269     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 270                             { "code":
 271                               "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
 272                               "predicate_test": predicateTest }, [])
 273     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 274     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 275     exec_output += PredOpExecute.subst(sxtbIop)
 276
 277     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 278                              { "code":
 279                                '''
 280                                    Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
 281                                           Op1;
 282                                ''',
 283                                "predicate_test": predicateTest }, [])
 284     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 285     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 286     exec_output += PredOpExecute.subst(sxtabIop)
 287
 288     sxtb16Code = '''
 289     uint32_t resTemp = 0;
 290     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 291     replaceBits(resTemp, 31, 16,
 292                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 293     Dest = resTemp;
 294     '''
 295     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 296                               { "code": sxtb16Code,
 297                                 "predicate_test": predicateTest }, [])
 298     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 299     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 300     exec_output += PredOpExecute.subst(sxtb16Iop)
 301
 302     sxtab16Code = '''
 303     uint32_t resTemp = 0;
 304     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 305                                         bits(Op1, 15, 0));
 306     replaceBits(resTemp, 31, 16,
 307                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 308                 bits(Op1, 31, 16));
 309     Dest = resTemp;
 310     '''
 311     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 312                                { "code": sxtab16Code,
 313                                  "predicate_test": predicateTest }, [])
 314     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 315     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 316     exec_output += PredOpExecute.subst(sxtab16Iop)
 317
 318     sxthCode = '''
 319     uint64_t rotated = (uint32_t)Op1;
 320     rotated = (rotated | (rotated << 32)) >> imm;
 321     Dest = sext<16>((uint16_t)rotated);
 322     '''
 323     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 324                               { "code": sxthCode,
 325                                 "predicate_test": predicateTest }, [])
 326     header_output += RegImmRegOpDeclare.subst(sxthIop)
 327     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 328     exec_output += PredOpExecute.subst(sxthIop)
 329
 330     sxtahCode = '''
 331     uint64_t rotated = (uint32_t)Op2;
 332     rotated = (rotated | (rotated << 32)) >> imm;
 333     Dest = sext<16>((uint16_t)rotated) + Op1;
 334     '''
 335     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 336                              { "code": sxtahCode,
 337                                "predicate_test": predicateTest }, [])
 338     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 339     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 340     exec_output += PredOpExecute.subst(sxtahIop)
 341
 342     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 343                             { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
 344                               "predicate_test": predicateTest }, [])
 345     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 346     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 347     exec_output += PredOpExecute.subst(uxtbIop)
 348
 349     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 350                              { "code":
 351                                "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
 352                                "predicate_test": predicateTest }, [])
 353     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 354     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 355     exec_output += PredOpExecute.subst(uxtabIop)
 356
 357     uxtb16Code = '''
 358     uint32_t resTemp = 0;
 359     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 360     replaceBits(resTemp, 31, 16,
 361                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 362     Dest = resTemp;
 363     '''
 364     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 365                               { "code": uxtb16Code,
 366                                 "predicate_test": predicateTest }, [])
 367     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 368     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 369     exec_output += PredOpExecute.subst(uxtb16Iop)
 370
 371     uxtab16Code = '''
 372     uint32_t resTemp = 0;
 373     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 374                                         bits(Op1, 15, 0));
 375     replaceBits(resTemp, 31, 16,
 376                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 377                 bits(Op1, 31, 16));
 378     Dest = resTemp;
 379     '''
 380     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 381                                { "code": uxtab16Code,
 382                                  "predicate_test": predicateTest }, [])
 383     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 384     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 385     exec_output += PredOpExecute.subst(uxtab16Iop)
 386
 387     uxthCode = '''
 388     uint64_t rotated = (uint32_t)Op1;
 389     rotated = (rotated | (rotated << 32)) >> imm;
 390     Dest = (uint16_t)rotated;
 391     '''
 392     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 393                               { "code": uxthCode,
 394                                 "predicate_test": predicateTest }, [])
 395     header_output += RegImmRegOpDeclare.subst(uxthIop)
 396     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 397     exec_output += PredOpExecute.subst(uxthIop)
 398
 399     uxtahCode = '''
 400     uint64_t rotated = (uint32_t)Op2;
 401     rotated = (rotated | (rotated << 32)) >> imm;
 402     Dest = (uint16_t)rotated + Op1;
 403     '''
 404     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 405                              { "code": uxtahCode,
 406                                "predicate_test": predicateTest }, [])
 407     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 408     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 409     exec_output += PredOpExecute.subst(uxtahIop)
 410
 411     selCode = '''
 412         uint32_t resTemp = 0;
 413         for (unsigned i = 0; i < 4; i++) {
 414             int low = i * 8;
 415             int high = low + 7;
 416             replaceBits(resTemp, high, low,
 417                         bits(CondCodes, 16 + i) ?
 418                             bits(Op1, high, low) : bits(Op2, high, low));
 419         }
 420         Dest = resTemp;
 421     '''
 422     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 423                            { "code": selCode,
 424                              "predicate_test": condPredicateTest }, [])
 425     header_output += RegRegRegOpDeclare.subst(selIop)
 426     decoder_output += RegRegRegOpConstructor.subst(selIop)
 427     exec_output += PredOpExecute.subst(selIop)
 428
 429     usad8Code = '''
 430         uint32_t resTemp = 0;
 431         for (unsigned i = 0; i < 4; i++) {
 432             int low = i * 8;
 433             int high = low + 7;
 434             int32_t diff = bits(Op1, high, low) -
 435                            bits(Op2, high, low);
 436             resTemp += ((diff < 0) ? -diff : diff);
 437         }
 438         Dest = resTemp;
 439     '''
 440     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 441                              { "code": usad8Code,
 442                                "predicate_test": predicateTest }, [])
 443     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 444     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 445     exec_output += PredOpExecute.subst(usad8Iop)
 446
 447     usada8Code = '''
 448         uint32_t resTemp = 0;
 449         for (unsigned i = 0; i < 4; i++) {
 450             int low = i * 8;
 451             int high = low + 7;
 452             int32_t diff = bits(Op1, high, low) -
 453                            bits(Op2, high, low);
 454             resTemp += ((diff < 0) ? -diff : diff);
 455         }
 456         Dest = Op3 + resTemp;
 457     '''
 458     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 459                               { "code": usada8Code,
 460                                 "predicate_test": predicateTest }, [])
 461     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 462     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 463     exec_output += PredOpExecute.subst(usada8Iop)
 464
 465     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 466     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 467     header_output += BasicDeclare.subst(bkptIop)
 468     decoder_output += BasicConstructor.subst(bkptIop)
 469     exec_output += BasicExecute.subst(bkptIop)
 470
 471     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 472             { "code" : "", "predicate_test" : predicateTest },
 473             ['IsNop'])
 474     header_output += BasicDeclare.subst(nopIop)
 475     decoder_output += BasicConstructor.subst(nopIop)
 476     exec_output += PredOpExecute.subst(nopIop)
 477
 478     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 479             { "code" : "", "predicate_test" : predicateTest })
 480     header_output += BasicDeclare.subst(yieldIop)
 481     decoder_output += BasicConstructor.subst(yieldIop)
 482     exec_output += PredOpExecute.subst(yieldIop)
 483
 484     wfeCode = '''
 485 #if FULL_SYSTEM
 486     if (SevMailbox == 1) {
 487         SevMailbox = 0;
 488         PseudoInst::quiesceSkip(xc->tcBase());
 489     } else {
 490         PseudoInst::quiesce(xc->tcBase());
 491     }
 492 #endif
 493     '''
 494     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 495             { "code" : wfeCode, "predicate_test" : predicateTest },
 496             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 497     header_output += BasicDeclare.subst(wfeIop)
 498     decoder_output += BasicConstructor.subst(wfeIop)
 499     exec_output += QuiescePredOpExecute.subst(wfeIop)
 500
 501     wfiCode = '''
 502 #if FULL_SYSTEM
 503     // WFI doesn't sleep if interrupts are pending (masked or not)
 504     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
 505         PseudoInst::quiesceSkip(xc->tcBase());
 506     } else {
 507         PseudoInst::quiesce(xc->tcBase());
 508     }
 509 #endif
 510     '''
 511     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 512             { "code" : wfiCode, "predicate_test" : predicateTest },
 513             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 514     header_output += BasicDeclare.subst(wfiIop)
 515     decoder_output += BasicConstructor.subst(wfiIop)
 516     exec_output += QuiescePredOpExecute.subst(wfiIop)
 517
 518     sevCode = '''
 519     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
 520     SevMailbox = 1;
 521     System *sys = xc->tcBase()->getSystemPtr();
 522     for (int x = 0; x < sys->numContexts(); x++) {
 523         ThreadContext *oc = sys->getThreadContext(x);
 524         if (oc == xc->tcBase())
 525             continue;
 526         // Only wake if they were sleeping
 527         if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 528             oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
 529             PseudoInst::wakeCPU(xc->tcBase(), x);
 530         }
 531     }
 532     '''
 533     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 534             { "code" : sevCode, "predicate_test" : predicateTest },
 535             ["IsNonSpeculative", "IsSquashAfter"])
 536     header_output += BasicDeclare.subst(sevIop)
 537     decoder_output += BasicConstructor.subst(sevIop)
 538     exec_output += PredOpExecute.subst(sevIop)
 539
 540     itIop = InstObjParams("it", "ItInst", "PredOp", \
 541             { "code" : ";",
 542               "predicate_test" : predicateTest },
 543             ["IsNonSpeculative", "IsSerializeAfter"])
 544     header_output += BasicDeclare.subst(itIop)
 545     decoder_output += BasicConstructor.subst(itIop)
 546     exec_output += PredOpExecute.subst(itIop)
 547     unknownCode = '''
 548 #if FULL_SYSTEM
 549             return new UndefinedInstruction;
 550 #else
 551             return new UndefinedInstruction(machInst, true);
 552 #endif
 553     '''
 554     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 555                                { "code": unknownCode,
 556                                  "predicate_test": predicateTest })
 557     header_output += BasicDeclare.subst(unknownIop)
 558     decoder_output += BasicConstructor.subst(unknownIop)
 559     exec_output += PredOpExecute.subst(unknownIop)
 560
 561     ubfxCode = '''
 562         Dest = bits(Op1, imm2, imm1);
 563     '''
 564     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 565                             { "code": ubfxCode,
 566                               "predicate_test": predicateTest }, [])
 567     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 568     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 569     exec_output += PredOpExecute.subst(ubfxIop)
 570
 571     sbfxCode = '''
 572         int32_t resTemp = bits(Op1, imm2, imm1);
 573         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 574     '''
 575     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 576                             { "code": sbfxCode,
 577                               "predicate_test": predicateTest }, [])
 578     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 579     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 580     exec_output += PredOpExecute.subst(sbfxIop)
 581
 582     bfcCode = '''
 583         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 584     '''
 585     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 586                            { "code": bfcCode,
 587                              "predicate_test": predicateTest }, [])
 588     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 589     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 590     exec_output += PredOpExecute.subst(bfcIop)
 591
 592     bfiCode = '''
 593         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 594         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 595     '''
 596     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 597                            { "code": bfiCode,
 598                              "predicate_test": predicateTest }, [])
 599     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 600     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 601     exec_output += PredOpExecute.subst(bfiIop)
 602
 603     mrc15code = '''
 604     CPSR cpsr = Cpsr;
 605     if (cpsr.mode == MODE_USER)
 606 #if FULL_SYSTEM
 607         return new UndefinedInstruction;
 608 #else
 609         return new UndefinedInstruction(false, mnemonic);
 610 #endif
 611     Dest = MiscOp1;
 612     '''
 613
 614     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 615                              { "code": mrc15code,
 616                                "predicate_test": predicateTest }, [])
 617     header_output += RegRegOpDeclare.subst(mrc15Iop)
 618     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 619     exec_output += PredOpExecute.subst(mrc15Iop)
 620
 621
 622     mcr15code = '''
 623     CPSR cpsr = Cpsr;
 624     if (cpsr.mode == MODE_USER)
 625 #if FULL_SYSTEM
 626         return new UndefinedInstruction;
 627 #else
 628         return new UndefinedInstruction(false, mnemonic);
 629 #endif
 630     MiscDest = Op1;
 631     '''
 632     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 633                              { "code": mcr15code,
 634                                "predicate_test": predicateTest },
 635                                ["IsSerializeAfter","IsNonSpeculative"])
 636     header_output += RegRegOpDeclare.subst(mcr15Iop)
 637     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 638     exec_output += PredOpExecute.subst(mcr15Iop)
 639
 640     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 641                                  { "code": "Dest = MiscOp1;",
 642                                    "predicate_test": predicateTest }, [])
 643     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 644     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 645     exec_output += PredOpExecute.subst(mrc15UserIop)
 646
 647     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 648                                  { "code": "MiscDest = Op1",
 649                                    "predicate_test": predicateTest },
 650                                    ["IsSerializeAfter","IsNonSpeculative"])
 651     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 652     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 653     exec_output += PredOpExecute.subst(mcr15UserIop)
 654
 655     enterxCode = '''
 656         NextThumb = true;
 657         NextJazelle = true;
 658     '''
 659     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 660                               { "code": enterxCode,
 661                                 "predicate_test": predicateTest }, [])
 662     header_output += BasicDeclare.subst(enterxIop)
 663     decoder_output += BasicConstructor.subst(enterxIop)
 664     exec_output += PredOpExecute.subst(enterxIop)
 665
 666     leavexCode = '''
 667         NextThumb = true;
 668         NextJazelle = false;
 669     '''
 670     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 671                               { "code": leavexCode,
 672                                 "predicate_test": predicateTest }, [])
 673     header_output += BasicDeclare.subst(leavexIop)
 674     decoder_output += BasicConstructor.subst(leavexIop)
 675     exec_output += PredOpExecute.subst(leavexIop)
 676
 677     setendCode = '''
 678         CPSR cpsr = Cpsr;
 679         cpsr.e = imm;
 680         Cpsr = cpsr;
 681     '''
 682     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 683                               { "code": setendCode,
 684                                 "predicate_test": predicateTest },
 685                               ["IsSerializeAfter","IsNonSpeculative"])
 686     header_output += ImmOpDeclare.subst(setendIop)
 687     decoder_output += ImmOpConstructor.subst(setendIop)
 688     exec_output += PredOpExecute.subst(setendIop)
 689
 690     clrexCode = '''
 691         LLSCLock = 0;
 692     '''
 693     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 694                              { "code": clrexCode,
 695                                "predicate_test": predicateTest },[])
 696     header_output += BasicDeclare.subst(clrexIop)
 697     decoder_output += BasicConstructor.subst(clrexIop)
 698     exec_output += PredOpExecute.subst(clrexIop)
 699
 700     isbCode = '''
 701         fault = new FlushPipe;
 702     '''
 703     isbIop = InstObjParams("isb", "Isb", "PredOp",
 704                              {"code": isbCode,
 705                                "predicate_test": predicateTest},
 706                                 ['IsSerializeAfter'])
 707     header_output += BasicDeclare.subst(isbIop)
 708     decoder_output += BasicConstructor.subst(isbIop)
 709     exec_output += PredOpExecute.subst(isbIop)
 710
 711     dsbCode = '''
 712         fault = new FlushPipe;
 713     '''
 714     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 715                              {"code": dsbCode,
 716                                "predicate_test": predicateTest},
 717                               ['IsMemBarrier', 'IsSerializeAfter'])
 718     header_output += BasicDeclare.subst(dsbIop)
 719     decoder_output += BasicConstructor.subst(dsbIop)
 720     exec_output += PredOpExecute.subst(dsbIop)
 721
 722     dmbCode = '''
 723     '''
 724     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 725                              {"code": dmbCode,
 726                                "predicate_test": predicateTest},
 727                                ['IsMemBarrier'])
 728     header_output += BasicDeclare.subst(dmbIop)
 729     decoder_output += BasicConstructor.subst(dmbIop)
 730     exec_output += PredOpExecute.subst(dmbIop)
 731
 732     dbgCode = '''
 733     '''
 734     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 735                              {"code": dbgCode,
 736                                "predicate_test": predicateTest})
 737     header_output += BasicDeclare.subst(dbgIop)
 738     decoder_output += BasicConstructor.subst(dbgIop)
 739     exec_output += PredOpExecute.subst(dbgIop)
 740
 741     cpsCode = '''
 742     uint32_t mode = bits(imm, 4, 0);
 743     uint32_t f = bits(imm, 5);
 744     uint32_t i = bits(imm, 6);
 745     uint32_t a = bits(imm, 7);
 746     bool setMode = bits(imm, 8);
 747     bool enable = bits(imm, 9);
 748     CPSR cpsr = Cpsr;
 749     SCTLR sctlr = Sctlr;
 750     if (cpsr.mode != MODE_USER) {
 751         if (enable) {
 752             if (f) cpsr.f = 0;
 753             if (i) cpsr.i = 0;
 754             if (a) cpsr.a = 0;
 755         } else {
 756             if (f && !sctlr.nmfi) cpsr.f = 1;
 757             if (i) cpsr.i = 1;
 758             if (a) cpsr.a = 1;
 759         }
 760         if (setMode) {
 761             cpsr.mode = mode;
 762         }
 763     }
 764     Cpsr = cpsr;
 765     '''
 766     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 767                            { "code": cpsCode,
 768                              "predicate_test": predicateTest },
 769                            ["IsSerializeAfter","IsNonSpeculative"])
 770     header_output += ImmOpDeclare.subst(cpsIop)
 771     decoder_output += ImmOpConstructor.subst(cpsIop)
 772     exec_output += PredOpExecute.subst(cpsIop)
 773 }};