src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
  64     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  65                                { "code": mrsCpsrCode,
  66                                  "predicate_test": condPredicateTest },
  67                                ["IsSerializeBefore"])
  68     header_output += MrsDeclare.subst(mrsCpsrIop)
  69     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  70     exec_output += PredOpExecute.subst(mrsCpsrIop)
  71
  72     mrsSpsrCode = "Dest = Spsr"
  73     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  74                                { "code": mrsSpsrCode,
  75                                  "predicate_test": predicateTest },
  76                                ["IsSerializeBefore"])
  77     header_output += MrsDeclare.subst(mrsSpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  79     exec_output += PredOpExecute.subst(mrsSpsrIop)
  80
  81     msrCpsrRegCode = '''
  82         SCTLR sctlr = Sctlr;
  83         uint32_t newCpsr =
  84             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
  85         Cpsr = ~CondCodesMask & newCpsr;
  86         NextThumb = ((CPSR)newCpsr).t;
  87         NextJazelle = ((CPSR)newCpsr).j;
  88         CondCodes = CondCodesMask & newCpsr;
  89     '''
  90     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
  91                                   { "code": msrCpsrRegCode,
  92                                     "predicate_test": condPredicateTest },
  93                                   ["IsSerializeAfter","IsNonSpeculative"])
  94     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
  95     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
  96     exec_output += PredOpExecute.subst(msrCpsrRegIop)
  97
  98     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
  99     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 100                                   { "code": msrSpsrRegCode,
 101                                     "predicate_test": predicateTest },
 102                                   ["IsSerializeAfter","IsNonSpeculative"])
 103     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 104     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 105     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 106
 107     msrCpsrImmCode = '''
 108         SCTLR sctlr = Sctlr;
 109         uint32_t newCpsr =
 110             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
 111         Cpsr = ~CondCodesMask & newCpsr;
 112         NextThumb = ((CPSR)newCpsr).t;
 113         NextJazelle = ((CPSR)newCpsr).j;
 114         CondCodes = CondCodesMask & newCpsr;
 115     '''
 116     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 117                                   { "code": msrCpsrImmCode,
 118                                     "predicate_test": condPredicateTest },
 119                                   ["IsSerializeAfter","IsNonSpeculative"])
 120     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 121     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 122     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 123
 124     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 125     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 126                                   { "code": msrSpsrImmCode,
 127                                     "predicate_test": predicateTest },
 128                                   ["IsSerializeAfter","IsNonSpeculative"])
 129     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 130     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 131     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 132
 133     revCode = '''
 134     uint32_t val = Op1;
 135     Dest = swap_byte(val);
 136     '''
 137     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 138                            { "code": revCode,
 139                              "predicate_test": predicateTest }, [])
 140     header_output += RegRegOpDeclare.subst(revIop)
 141     decoder_output += RegRegOpConstructor.subst(revIop)
 142     exec_output += PredOpExecute.subst(revIop)
 143
 144     rev16Code = '''
 145     uint32_t val = Op1;
 146     Dest = (bits(val, 15, 8) << 0) |
 147            (bits(val, 7, 0) << 8) |
 148            (bits(val, 31, 24) << 16) |
 149            (bits(val, 23, 16) << 24);
 150     '''
 151     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 152                              { "code": rev16Code,
 153                                "predicate_test": predicateTest }, [])
 154     header_output += RegRegOpDeclare.subst(rev16Iop)
 155     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 156     exec_output += PredOpExecute.subst(rev16Iop)
 157
 158     revshCode = '''
 159     uint16_t val = Op1;
 160     Dest = sext<16>(swap_byte(val));
 161     '''
 162     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 163                              { "code": revshCode,
 164                                "predicate_test": predicateTest }, [])
 165     header_output += RegRegOpDeclare.subst(revshIop)
 166     decoder_output += RegRegOpConstructor.subst(revshIop)
 167     exec_output += PredOpExecute.subst(revshIop)
 168
 169     rbitCode = '''
 170     uint8_t *opBytes = (uint8_t *)&Op1;
 171     uint32_t resTemp;
 172     uint8_t *destBytes = (uint8_t *)&resTemp;
 173     // This reverses the bytes and bits of the input, or so says the
 174     // internet.
 175     for (int i = 0; i < 4; i++) {
 176         uint32_t temp = opBytes[i];
 177         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 178         destBytes[3 - i] = (temp * 0x10101) >> 16;
 179     }
 180     Dest = resTemp;
 181     '''
 182     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 183                             { "code": rbitCode,
 184                               "predicate_test": predicateTest }, [])
 185     header_output += RegRegOpDeclare.subst(rbitIop)
 186     decoder_output += RegRegOpConstructor.subst(rbitIop)
 187     exec_output += PredOpExecute.subst(rbitIop)
 188
 189     clzCode = '''
 190         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 191     '''
 192     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 193                            { "code": clzCode,
 194                              "predicate_test": predicateTest }, [])
 195     header_output += RegRegOpDeclare.subst(clzIop)
 196     decoder_output += RegRegOpConstructor.subst(clzIop)
 197     exec_output += PredOpExecute.subst(clzIop)
 198
 199     ssatCode = '''
 200         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 201         int32_t res;
 202         if (satInt(res, operand, imm))
 203             CondCodes = CondCodes | (1 << 27);
 204         else
 205             CondCodes = CondCodes;
 206         Dest = res;
 207     '''
 208     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 209                             { "code": ssatCode,
 210                               "predicate_test": condPredicateTest }, [])
 211     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 212     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 213     exec_output += PredOpExecute.subst(ssatIop)
 214
 215     usatCode = '''
 216         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 217         int32_t res;
 218         if (uSatInt(res, operand, imm))
 219             CondCodes = CondCodes | (1 << 27);
 220         else
 221             CondCodes = CondCodes;
 222         Dest = res;
 223     '''
 224     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 225                             { "code": usatCode,
 226                               "predicate_test": condPredicateTest }, [])
 227     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 228     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 229     exec_output += PredOpExecute.subst(usatIop)
 230
 231     ssat16Code = '''
 232         int32_t res;
 233         uint32_t resTemp = 0;
 234         CondCodes = CondCodes;
 235         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 236         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 237         if (satInt(res, argLow, imm))
 238             CondCodes = CondCodes | (1 << 27);
 239         replaceBits(resTemp, 15, 0, res);
 240         if (satInt(res, argHigh, imm))
 241             CondCodes = CondCodes | (1 << 27);
 242         replaceBits(resTemp, 31, 16, res);
 243         Dest = resTemp;
 244     '''
 245     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 246                               { "code": ssat16Code,
 247                                 "predicate_test": condPredicateTest }, [])
 248     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 249     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 250     exec_output += PredOpExecute.subst(ssat16Iop)
 251
 252     usat16Code = '''
 253         int32_t res;
 254         uint32_t resTemp = 0;
 255         CondCodes = CondCodes;
 256         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 257         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 258         if (uSatInt(res, argLow, imm))
 259             CondCodes = CondCodes | (1 << 27);
 260         replaceBits(resTemp, 15, 0, res);
 261         if (uSatInt(res, argHigh, imm))
 262             CondCodes = CondCodes | (1 << 27);
 263         replaceBits(resTemp, 31, 16, res);
 264         Dest = resTemp;
 265     '''
 266     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 267                               { "code": usat16Code,
 268                                 "predicate_test": condPredicateTest }, [])
 269     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 270     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 271     exec_output += PredOpExecute.subst(usat16Iop)
 272
 273     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 274                             { "code":
 275                               "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
 276                               "predicate_test": predicateTest }, [])
 277     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 278     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 279     exec_output += PredOpExecute.subst(sxtbIop)
 280
 281     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 282                              { "code":
 283                                '''
 284                                    Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
 285                                           Op1;
 286                                ''',
 287                                "predicate_test": predicateTest }, [])
 288     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 289     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 290     exec_output += PredOpExecute.subst(sxtabIop)
 291
 292     sxtb16Code = '''
 293     uint32_t resTemp = 0;
 294     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 295     replaceBits(resTemp, 31, 16,
 296                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 297     Dest = resTemp;
 298     '''
 299     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 300                               { "code": sxtb16Code,
 301                                 "predicate_test": predicateTest }, [])
 302     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 303     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 304     exec_output += PredOpExecute.subst(sxtb16Iop)
 305
 306     sxtab16Code = '''
 307     uint32_t resTemp = 0;
 308     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 309                                         bits(Op1, 15, 0));
 310     replaceBits(resTemp, 31, 16,
 311                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 312                 bits(Op1, 31, 16));
 313     Dest = resTemp;
 314     '''
 315     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 316                                { "code": sxtab16Code,
 317                                  "predicate_test": predicateTest }, [])
 318     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 319     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 320     exec_output += PredOpExecute.subst(sxtab16Iop)
 321
 322     sxthCode = '''
 323     uint64_t rotated = (uint32_t)Op1;
 324     rotated = (rotated | (rotated << 32)) >> imm;
 325     Dest = sext<16>((uint16_t)rotated);
 326     '''
 327     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 328                               { "code": sxthCode,
 329                                 "predicate_test": predicateTest }, [])
 330     header_output += RegImmRegOpDeclare.subst(sxthIop)
 331     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 332     exec_output += PredOpExecute.subst(sxthIop)
 333
 334     sxtahCode = '''
 335     uint64_t rotated = (uint32_t)Op2;
 336     rotated = (rotated | (rotated << 32)) >> imm;
 337     Dest = sext<16>((uint16_t)rotated) + Op1;
 338     '''
 339     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 340                              { "code": sxtahCode,
 341                                "predicate_test": predicateTest }, [])
 342     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 343     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 344     exec_output += PredOpExecute.subst(sxtahIop)
 345
 346     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 347                             { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
 348                               "predicate_test": predicateTest }, [])
 349     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 350     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 351     exec_output += PredOpExecute.subst(uxtbIop)
 352
 353     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 354                              { "code":
 355                                "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
 356                                "predicate_test": predicateTest }, [])
 357     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 358     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 359     exec_output += PredOpExecute.subst(uxtabIop)
 360
 361     uxtb16Code = '''
 362     uint32_t resTemp = 0;
 363     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 364     replaceBits(resTemp, 31, 16,
 365                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 366     Dest = resTemp;
 367     '''
 368     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 369                               { "code": uxtb16Code,
 370                                 "predicate_test": predicateTest }, [])
 371     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 372     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 373     exec_output += PredOpExecute.subst(uxtb16Iop)
 374
 375     uxtab16Code = '''
 376     uint32_t resTemp = 0;
 377     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 378                                         bits(Op1, 15, 0));
 379     replaceBits(resTemp, 31, 16,
 380                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 381                 bits(Op1, 31, 16));
 382     Dest = resTemp;
 383     '''
 384     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 385                                { "code": uxtab16Code,
 386                                  "predicate_test": predicateTest }, [])
 387     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 388     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 389     exec_output += PredOpExecute.subst(uxtab16Iop)
 390
 391     uxthCode = '''
 392     uint64_t rotated = (uint32_t)Op1;
 393     rotated = (rotated | (rotated << 32)) >> imm;
 394     Dest = (uint16_t)rotated;
 395     '''
 396     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 397                               { "code": uxthCode,
 398                                 "predicate_test": predicateTest }, [])
 399     header_output += RegImmRegOpDeclare.subst(uxthIop)
 400     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 401     exec_output += PredOpExecute.subst(uxthIop)
 402
 403     uxtahCode = '''
 404     uint64_t rotated = (uint32_t)Op2;
 405     rotated = (rotated | (rotated << 32)) >> imm;
 406     Dest = (uint16_t)rotated + Op1;
 407     '''
 408     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 409                              { "code": uxtahCode,
 410                                "predicate_test": predicateTest }, [])
 411     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 412     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 413     exec_output += PredOpExecute.subst(uxtahIop)
 414
 415     selCode = '''
 416         uint32_t resTemp = 0;
 417         for (unsigned i = 0; i < 4; i++) {
 418             int low = i * 8;
 419             int high = low + 7;
 420             replaceBits(resTemp, high, low,
 421                         bits(CondCodes, 16 + i) ?
 422                             bits(Op1, high, low) : bits(Op2, high, low));
 423         }
 424         Dest = resTemp;
 425     '''
 426     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 427                            { "code": selCode,
 428                              "predicate_test": condPredicateTest }, [])
 429     header_output += RegRegRegOpDeclare.subst(selIop)
 430     decoder_output += RegRegRegOpConstructor.subst(selIop)
 431     exec_output += PredOpExecute.subst(selIop)
 432
 433     usad8Code = '''
 434         uint32_t resTemp = 0;
 435         for (unsigned i = 0; i < 4; i++) {
 436             int low = i * 8;
 437             int high = low + 7;
 438             int32_t diff = bits(Op1, high, low) -
 439                            bits(Op2, high, low);
 440             resTemp += ((diff < 0) ? -diff : diff);
 441         }
 442         Dest = resTemp;
 443     '''
 444     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 445                              { "code": usad8Code,
 446                                "predicate_test": predicateTest }, [])
 447     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 448     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 449     exec_output += PredOpExecute.subst(usad8Iop)
 450
 451     usada8Code = '''
 452         uint32_t resTemp = 0;
 453         for (unsigned i = 0; i < 4; i++) {
 454             int low = i * 8;
 455             int high = low + 7;
 456             int32_t diff = bits(Op1, high, low) -
 457                            bits(Op2, high, low);
 458             resTemp += ((diff < 0) ? -diff : diff);
 459         }
 460         Dest = Op3 + resTemp;
 461     '''
 462     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 463                               { "code": usada8Code,
 464                                 "predicate_test": predicateTest }, [])
 465     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 466     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 467     exec_output += PredOpExecute.subst(usada8Iop)
 468
 469     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 470     bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
 471             bkptCode)
 472     header_output += BasicDeclare.subst(bkptIop)
 473     decoder_output += BasicConstructor.subst(bkptIop)
 474     exec_output += BasicExecute.subst(bkptIop)
 475
 476     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 477             { "code" : "", "predicate_test" : predicateTest })
 478     header_output += BasicDeclare.subst(nopIop)
 479     decoder_output += BasicConstructor.subst(nopIop)
 480     exec_output += PredOpExecute.subst(nopIop)
 481
 482     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 483             { "code" : "", "predicate_test" : predicateTest })
 484     header_output += BasicDeclare.subst(yieldIop)
 485     decoder_output += BasicConstructor.subst(yieldIop)
 486     exec_output += PredOpExecute.subst(yieldIop)
 487
 488     wfeCode = '''
 489 #if FULL_SYSTEM
 490     if (SevMailbox)
 491         SevMailbox = 0;
 492     else
 493         PseudoInst::quiesce(xc->tcBase());
 494 #endif
 495     '''
 496     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 497             { "code" : wfeCode, "predicate_test" : predicateTest },
 498             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 499     header_output += BasicDeclare.subst(wfeIop)
 500     decoder_output += BasicConstructor.subst(wfeIop)
 501     exec_output += PredOpExecute.subst(wfeIop)
 502
 503     wfiCode = '''
 504 #if FULL_SYSTEM
 505     PseudoInst::quiesce(xc->tcBase());
 506 #endif
 507     '''
 508     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 509             { "code" : wfiCode, "predicate_test" : predicateTest },
 510             ["IsNonSpeculative", "IsQuiesce"])
 511     header_output += BasicDeclare.subst(wfiIop)
 512     decoder_output += BasicConstructor.subst(wfiIop)
 513     exec_output += PredOpExecute.subst(wfiIop)
 514
 515     sevCode = '''
 516     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
 517     System *sys = xc->tcBase()->getSystemPtr();
 518     for (int x = 0; x < sys->numContexts(); x++) {
 519         ThreadContext *oc = sys->getThreadContext(x);
 520         oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
 521     }
 522     '''
 523     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 524             { "code" : sevCode, "predicate_test" : predicateTest },
 525             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 526     header_output += BasicDeclare.subst(sevIop)
 527     decoder_output += BasicConstructor.subst(sevIop)
 528     exec_output += PredOpExecute.subst(sevIop)
 529
 530     itIop = InstObjParams("it", "ItInst", "PredOp", \
 531             { "code" : "Itstate = machInst.newItstate;",
 532               "predicate_test" : predicateTest },
 533             ["IsNonSpeculative", "IsSerializeAfter"])
 534     header_output += BasicDeclare.subst(itIop)
 535     decoder_output += BasicConstructor.subst(itIop)
 536     exec_output += PredOpExecute.subst(itIop)
 537     unknownCode = '''
 538 #if FULL_SYSTEM
 539             return new UndefinedInstruction;
 540 #else
 541             return new UndefinedInstruction(machInst, true);
 542 #endif
 543     '''
 544     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 545                                { "code": unknownCode,
 546                                  "predicate_test": predicateTest })
 547     header_output += BasicDeclare.subst(unknownIop)
 548     decoder_output += BasicConstructor.subst(unknownIop)
 549     exec_output += PredOpExecute.subst(unknownIop)
 550
 551     ubfxCode = '''
 552         Dest = bits(Op1, imm2, imm1);
 553     '''
 554     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 555                             { "code": ubfxCode,
 556                               "predicate_test": predicateTest }, [])
 557     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 558     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 559     exec_output += PredOpExecute.subst(ubfxIop)
 560
 561     sbfxCode = '''
 562         int32_t resTemp = bits(Op1, imm2, imm1);
 563         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 564     '''
 565     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 566                             { "code": sbfxCode,
 567                               "predicate_test": predicateTest }, [])
 568     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 569     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 570     exec_output += PredOpExecute.subst(sbfxIop)
 571
 572     bfcCode = '''
 573         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 574     '''
 575     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 576                            { "code": bfcCode,
 577                              "predicate_test": predicateTest }, [])
 578     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 579     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 580     exec_output += PredOpExecute.subst(bfcIop)
 581
 582     bfiCode = '''
 583         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 584         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 585     '''
 586     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 587                            { "code": bfiCode,
 588                              "predicate_test": predicateTest }, [])
 589     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 590     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 591     exec_output += PredOpExecute.subst(bfiIop)
 592
 593     mrc15code = '''
 594     CPSR cpsr = Cpsr;
 595     if (cpsr.mode == MODE_USER)
 596 #if FULL_SYSTEM
 597         return new UndefinedInstruction;
 598 #else
 599         return new UndefinedInstruction(false, mnemonic);
 600 #endif
 601     Dest = MiscOp1;
 602     '''
 603
 604     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 605                              { "code": mrc15code,
 606                                "predicate_test": predicateTest }, [])
 607     header_output += RegRegOpDeclare.subst(mrc15Iop)
 608     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 609     exec_output += PredOpExecute.subst(mrc15Iop)
 610
 611
 612     mcr15code = '''
 613     CPSR cpsr = Cpsr;
 614     if (cpsr.mode == MODE_USER)
 615 #if FULL_SYSTEM
 616         return new UndefinedInstruction;
 617 #else
 618         return new UndefinedInstruction(false, mnemonic);
 619 #endif
 620     MiscDest = Op1;
 621     '''
 622     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 623                              { "code": mcr15code,
 624                                "predicate_test": predicateTest },
 625                                ["IsSerializeAfter","IsNonSpeculative"])
 626     header_output += RegRegOpDeclare.subst(mcr15Iop)
 627     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 628     exec_output += PredOpExecute.subst(mcr15Iop)
 629
 630     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 631                                  { "code": "Dest = MiscOp1;",
 632                                    "predicate_test": predicateTest }, [])
 633     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 634     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 635     exec_output += PredOpExecute.subst(mrc15UserIop)
 636
 637     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 638                                  { "code": "MiscDest = Op1",
 639                                    "predicate_test": predicateTest },
 640                                    ["IsSerializeAfter","IsNonSpeculative"])
 641     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 642     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 643     exec_output += PredOpExecute.subst(mcr15UserIop)
 644
 645     enterxCode = '''
 646         NextThumb = true;
 647         NextJazelle = true;
 648     '''
 649     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 650                               { "code": enterxCode,
 651                                 "predicate_test": predicateTest }, [])
 652     header_output += BasicDeclare.subst(enterxIop)
 653     decoder_output += BasicConstructor.subst(enterxIop)
 654     exec_output += PredOpExecute.subst(enterxIop)
 655
 656     leavexCode = '''
 657         NextThumb = true;
 658         NextJazelle = false;
 659     '''
 660     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 661                               { "code": leavexCode,
 662                                 "predicate_test": predicateTest }, [])
 663     header_output += BasicDeclare.subst(leavexIop)
 664     decoder_output += BasicConstructor.subst(leavexIop)
 665     exec_output += PredOpExecute.subst(leavexIop)
 666
 667     setendCode = '''
 668         CPSR cpsr = Cpsr;
 669         cpsr.e = imm;
 670         Cpsr = cpsr;
 671     '''
 672     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 673                               { "code": setendCode,
 674                                 "predicate_test": predicateTest },
 675                               ["IsSerializeAfter","IsNonSpeculative"])
 676     header_output += ImmOpDeclare.subst(setendIop)
 677     decoder_output += ImmOpConstructor.subst(setendIop)
 678     exec_output += PredOpExecute.subst(setendIop)
 679
 680     clrexCode = '''
 681         unsigned memAccessFlags = Request::CLEAR_LL |
 682             ArmISA::TLB::AlignWord | Request::LLSC;
 683         fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
 684     '''
 685     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 686                              { "code": clrexCode,
 687                                "predicate_test": predicateTest },[])
 688     header_output += ClrexDeclare.subst(clrexIop)
 689     decoder_output += BasicConstructor.subst(clrexIop)
 690     exec_output += PredOpExecute.subst(clrexIop)
 691     exec_output += ClrexInitiateAcc.subst(clrexIop)
 692     exec_output += ClrexCompleteAcc.subst(clrexIop)
 693
 694     isbCode = '''
 695     '''
 696     isbIop = InstObjParams("isb", "Isb", "PredOp",
 697                              {"code": isbCode,
 698                                "predicate_test": predicateTest}, ['IsSerializing'])
 699     header_output += BasicDeclare.subst(isbIop)
 700     decoder_output += BasicConstructor.subst(isbIop)
 701     exec_output += PredOpExecute.subst(isbIop)
 702
 703     dsbCode = '''
 704     '''
 705     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 706                              {"code": dsbCode,
 707                                "predicate_test": predicateTest},['IsMemBarrier'])
 708     header_output += BasicDeclare.subst(dsbIop)
 709     decoder_output += BasicConstructor.subst(dsbIop)
 710     exec_output += PredOpExecute.subst(dsbIop)
 711
 712     dmbCode = '''
 713     '''
 714     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 715                              {"code": dmbCode,
 716                                "predicate_test": predicateTest},['IsMemBarrier'])
 717     header_output += BasicDeclare.subst(dmbIop)
 718     decoder_output += BasicConstructor.subst(dmbIop)
 719     exec_output += PredOpExecute.subst(dmbIop)
 720
 721     dbgCode = '''
 722     '''
 723     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 724                              {"code": dbgCode,
 725                                "predicate_test": predicateTest})
 726     header_output += BasicDeclare.subst(dbgIop)
 727     decoder_output += BasicConstructor.subst(dbgIop)
 728     exec_output += PredOpExecute.subst(dbgIop)
 729
 730     cpsCode = '''
 731     uint32_t mode = bits(imm, 4, 0);
 732     uint32_t f = bits(imm, 5);
 733     uint32_t i = bits(imm, 6);
 734     uint32_t a = bits(imm, 7);
 735     bool setMode = bits(imm, 8);
 736     bool enable = bits(imm, 9);
 737     CPSR cpsr = Cpsr;
 738     SCTLR sctlr = Sctlr;
 739     if (cpsr.mode != MODE_USER) {
 740         if (enable) {
 741             if (f) cpsr.f = 0;
 742             if (i) cpsr.i = 0;
 743             if (a) cpsr.a = 0;
 744         } else {
 745             if (f && !sctlr.nmfi) cpsr.f = 1;
 746             if (i) cpsr.i = 1;
 747             if (a) cpsr.a = 1;
 748         }
 749         if (setMode) {
 750             cpsr.mode = mode;
 751         }
 752     }
 753     Cpsr = cpsr;
 754     '''
 755     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 756                            { "code": cpsCode,
 757                              "predicate_test": predicateTest },
 758                            ["IsSerializeAfter","IsNonSpeculative"])
 759     header_output += ImmOpDeclare.subst(cpsIop)
 760     decoder_output += ImmOpConstructor.subst(cpsIop)
 761     exec_output += PredOpExecute.subst(cpsIop)
 762 }};