3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are
17 // met: redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer;
19 // redistributions in binary form must reproduce the above copyright
20 // notice, this list of conditions and the following disclaimer in the
21 // documentation and/or other materials provided with the distribution;
22 // neither the name of the copyright holders nor the names of its
23 // contributors may be used to endorse or promote products derived from
24 // this software without specific prior written permission.
26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 // Authors: Gabe Black
44 fault = new SupervisorCall;
46 fault = new SupervisorCall(machInst);
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
52 "predicate_test": predicateTest }, ["IsSyscall"])
53 header_output = BasicDeclare.subst(svcIop)
54 decoder_output = BasicConstructor.subst(svcIop)
55 exec_output = PredOpExecute.subst(svcIop)
61 header_output = decoder_output = exec_output = ""
65 cpsr.nz = CondCodesNZ;
68 cpsr.ge = CondCodesGE;
69 Dest = cpsr & 0xF8FF03DF
72 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
73 { "code": mrsCpsrCode,
74 "predicate_test": condPredicateTest },
75 ["IsSerializeBefore"])
76 header_output += MrsDeclare.subst(mrsCpsrIop)
77 decoder_output += MrsConstructor.subst(mrsCpsrIop)
78 exec_output += PredOpExecute.subst(mrsCpsrIop)
80 mrsSpsrCode = "Dest = Spsr"
81 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
82 { "code": mrsSpsrCode,
83 "predicate_test": predicateTest },
84 ["IsSerializeBefore"])
85 header_output += MrsDeclare.subst(mrsSpsrIop)
86 decoder_output += MrsConstructor.subst(mrsSpsrIop)
87 exec_output += PredOpExecute.subst(mrsSpsrIop)
92 old_cpsr.nz = CondCodesNZ;
93 old_cpsr.c = CondCodesC;
94 old_cpsr.v = CondCodesV;
95 old_cpsr.ge = CondCodesGE;
98 cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
99 Cpsr = ~CondCodesMask & new_cpsr;
100 CondCodesNZ = new_cpsr.nz;
101 CondCodesC = new_cpsr.c;
102 CondCodesV = new_cpsr.v;
103 CondCodesGE = new_cpsr.ge;
105 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
106 { "code": msrCpsrRegCode,
107 "predicate_test": condPredicateTest },
108 ["IsSerializeAfter","IsNonSpeculative"])
109 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
110 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
111 exec_output += PredOpExecute.subst(msrCpsrRegIop)
113 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
114 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
115 { "code": msrSpsrRegCode,
116 "predicate_test": predicateTest },
117 ["IsSerializeAfter","IsNonSpeculative"])
118 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
119 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
120 exec_output += PredOpExecute.subst(msrSpsrRegIop)
124 CPSR old_cpsr = Cpsr;
125 old_cpsr.nz = CondCodesNZ;
126 old_cpsr.c = CondCodesC;
127 old_cpsr.v = CondCodesV;
128 old_cpsr.ge = CondCodesGE;
130 cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
131 Cpsr = ~CondCodesMask & new_cpsr;
132 CondCodesNZ = new_cpsr.nz;
133 CondCodesC = new_cpsr.c;
134 CondCodesV = new_cpsr.v;
135 CondCodesGE = new_cpsr.ge;
137 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
138 { "code": msrCpsrImmCode,
139 "predicate_test": condPredicateTest },
140 ["IsSerializeAfter","IsNonSpeculative"])
141 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
142 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
143 exec_output += PredOpExecute.subst(msrCpsrImmIop)
145 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
146 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
147 { "code": msrSpsrImmCode,
148 "predicate_test": predicateTest },
149 ["IsSerializeAfter","IsNonSpeculative"])
150 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
151 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
152 exec_output += PredOpExecute.subst(msrSpsrImmIop)
156 Dest = swap_byte(val);
158 revIop = InstObjParams("rev", "Rev", "RegRegOp",
160 "predicate_test": predicateTest }, [])
161 header_output += RegRegOpDeclare.subst(revIop)
162 decoder_output += RegRegOpConstructor.subst(revIop)
163 exec_output += PredOpExecute.subst(revIop)
167 Dest = (bits(val, 15, 8) << 0) |
168 (bits(val, 7, 0) << 8) |
169 (bits(val, 31, 24) << 16) |
170 (bits(val, 23, 16) << 24);
172 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
174 "predicate_test": predicateTest }, [])
175 header_output += RegRegOpDeclare.subst(rev16Iop)
176 decoder_output += RegRegOpConstructor.subst(rev16Iop)
177 exec_output += PredOpExecute.subst(rev16Iop)
181 Dest = sext<16>(swap_byte(val));
183 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
185 "predicate_test": predicateTest }, [])
186 header_output += RegRegOpDeclare.subst(revshIop)
187 decoder_output += RegRegOpConstructor.subst(revshIop)
188 exec_output += PredOpExecute.subst(revshIop)
191 uint8_t *opBytes = (uint8_t *)&Op1;
193 uint8_t *destBytes = (uint8_t *)&resTemp;
194 // This reverses the bytes and bits of the input, or so says the
196 for (int i = 0; i < 4; i++) {
197 uint32_t temp = opBytes[i];
198 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
199 destBytes[3 - i] = (temp * 0x10101) >> 16;
203 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
205 "predicate_test": predicateTest }, [])
206 header_output += RegRegOpDeclare.subst(rbitIop)
207 decoder_output += RegRegOpConstructor.subst(rbitIop)
208 exec_output += PredOpExecute.subst(rbitIop)
211 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
213 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
215 "predicate_test": predicateTest }, [])
216 header_output += RegRegOpDeclare.subst(clzIop)
217 decoder_output += RegRegOpConstructor.subst(clzIop)
218 exec_output += PredOpExecute.subst(clzIop)
221 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
223 if (satInt(res, operand, imm))
227 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
229 "predicate_test": pickPredicate(ssatCode) }, [])
230 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
231 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
232 exec_output += PredOpExecute.subst(ssatIop)
235 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
237 if (uSatInt(res, operand, imm))
241 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
243 "predicate_test": pickPredicate(usatCode) }, [])
244 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
245 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
246 exec_output += PredOpExecute.subst(usatIop)
250 uint32_t resTemp = 0;
251 int32_t argLow = sext<16>(bits(Op1, 15, 0));
252 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
253 if (satInt(res, argLow, imm))
255 replaceBits(resTemp, 15, 0, res);
256 if (satInt(res, argHigh, imm))
258 replaceBits(resTemp, 31, 16, res);
261 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
262 { "code": ssat16Code,
263 "predicate_test": pickPredicate(ssat16Code) }, [])
264 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
265 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
266 exec_output += PredOpExecute.subst(ssat16Iop)
270 uint32_t resTemp = 0;
271 int32_t argLow = sext<16>(bits(Op1, 15, 0));
272 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
273 if (uSatInt(res, argLow, imm))
275 replaceBits(resTemp, 15, 0, res);
276 if (uSatInt(res, argHigh, imm))
278 replaceBits(resTemp, 31, 16, res);
281 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
282 { "code": usat16Code,
283 "predicate_test": pickPredicate(usat16Code) }, [])
284 header_output += RegImmRegOpDeclare.subst(usat16Iop)
285 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
286 exec_output += PredOpExecute.subst(usat16Iop)
288 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
290 "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
291 "predicate_test": predicateTest }, [])
292 header_output += RegImmRegOpDeclare.subst(sxtbIop)
293 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
294 exec_output += PredOpExecute.subst(sxtbIop)
296 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
299 Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
302 "predicate_test": predicateTest }, [])
303 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
304 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
305 exec_output += PredOpExecute.subst(sxtabIop)
308 uint32_t resTemp = 0;
309 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
310 replaceBits(resTemp, 31, 16,
311 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
314 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
315 { "code": sxtb16Code,
316 "predicate_test": predicateTest }, [])
317 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
318 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
319 exec_output += PredOpExecute.subst(sxtb16Iop)
322 uint32_t resTemp = 0;
323 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
325 replaceBits(resTemp, 31, 16,
326 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
330 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
331 { "code": sxtab16Code,
332 "predicate_test": predicateTest }, [])
333 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
334 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
335 exec_output += PredOpExecute.subst(sxtab16Iop)
338 uint64_t rotated = (uint32_t)Op1;
339 rotated = (rotated | (rotated << 32)) >> imm;
340 Dest = sext<16>((uint16_t)rotated);
342 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
344 "predicate_test": predicateTest }, [])
345 header_output += RegImmRegOpDeclare.subst(sxthIop)
346 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
347 exec_output += PredOpExecute.subst(sxthIop)
350 uint64_t rotated = (uint32_t)Op2;
351 rotated = (rotated | (rotated << 32)) >> imm;
352 Dest = sext<16>((uint16_t)rotated) + Op1;
354 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
356 "predicate_test": predicateTest }, [])
357 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
358 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
359 exec_output += PredOpExecute.subst(sxtahIop)
361 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
362 { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
363 "predicate_test": predicateTest }, [])
364 header_output += RegImmRegOpDeclare.subst(uxtbIop)
365 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
366 exec_output += PredOpExecute.subst(uxtbIop)
368 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
370 "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
371 "predicate_test": predicateTest }, [])
372 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
373 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
374 exec_output += PredOpExecute.subst(uxtabIop)
377 uint32_t resTemp = 0;
378 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
379 replaceBits(resTemp, 31, 16,
380 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
383 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
384 { "code": uxtb16Code,
385 "predicate_test": predicateTest }, [])
386 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
387 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
388 exec_output += PredOpExecute.subst(uxtb16Iop)
391 uint32_t resTemp = 0;
392 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
394 replaceBits(resTemp, 31, 16,
395 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
399 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
400 { "code": uxtab16Code,
401 "predicate_test": predicateTest }, [])
402 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
403 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
404 exec_output += PredOpExecute.subst(uxtab16Iop)
407 uint64_t rotated = (uint32_t)Op1;
408 rotated = (rotated | (rotated << 32)) >> imm;
409 Dest = (uint16_t)rotated;
411 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
413 "predicate_test": predicateTest }, [])
414 header_output += RegImmRegOpDeclare.subst(uxthIop)
415 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
416 exec_output += PredOpExecute.subst(uxthIop)
419 uint64_t rotated = (uint32_t)Op2;
420 rotated = (rotated | (rotated << 32)) >> imm;
421 Dest = (uint16_t)rotated + Op1;
423 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
425 "predicate_test": predicateTest }, [])
426 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
427 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
428 exec_output += PredOpExecute.subst(uxtahIop)
431 uint32_t resTemp = 0;
432 for (unsigned i = 0; i < 4; i++) {
435 replaceBits(resTemp, high, low,
436 bits(CondCodesGE, i) ?
437 bits(Op1, high, low) : bits(Op2, high, low));
441 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
443 "predicate_test": predicateTest }, [])
444 header_output += RegRegRegOpDeclare.subst(selIop)
445 decoder_output += RegRegRegOpConstructor.subst(selIop)
446 exec_output += PredOpExecute.subst(selIop)
449 uint32_t resTemp = 0;
450 for (unsigned i = 0; i < 4; i++) {
453 int32_t diff = bits(Op1, high, low) -
454 bits(Op2, high, low);
455 resTemp += ((diff < 0) ? -diff : diff);
459 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
461 "predicate_test": predicateTest }, [])
462 header_output += RegRegRegOpDeclare.subst(usad8Iop)
463 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
464 exec_output += PredOpExecute.subst(usad8Iop)
467 uint32_t resTemp = 0;
468 for (unsigned i = 0; i < 4; i++) {
471 int32_t diff = bits(Op1, high, low) -
472 bits(Op2, high, low);
473 resTemp += ((diff < 0) ? -diff : diff);
475 Dest = Op3 + resTemp;
477 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
478 { "code": usada8Code,
479 "predicate_test": predicateTest }, [])
480 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
481 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
482 exec_output += PredOpExecute.subst(usada8Iop)
484 bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
485 bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
486 header_output += BasicDeclare.subst(bkptIop)
487 decoder_output += BasicConstructor.subst(bkptIop)
488 exec_output += BasicExecute.subst(bkptIop)
490 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
491 { "code" : "", "predicate_test" : predicateTest },
493 header_output += BasicDeclare.subst(nopIop)
494 decoder_output += BasicConstructor.subst(nopIop)
495 exec_output += PredOpExecute.subst(nopIop)
497 yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
498 { "code" : "", "predicate_test" : predicateTest })
499 header_output += BasicDeclare.subst(yieldIop)
500 decoder_output += BasicConstructor.subst(yieldIop)
501 exec_output += PredOpExecute.subst(yieldIop)
504 // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
505 if (SevMailbox == 1) {
507 PseudoInst::quiesceSkip(xc->tcBase());
508 } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
509 PseudoInst::quiesceSkip(xc->tcBase());
511 PseudoInst::quiesce(xc->tcBase());
514 wfePredFixUpCode = '''
515 // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
516 // and SEV interrupts
519 wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
521 "pred_fixup" : wfePredFixUpCode,
522 "predicate_test" : predicateTest },
523 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
524 header_output += BasicDeclare.subst(wfeIop)
525 decoder_output += BasicConstructor.subst(wfeIop)
526 exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
529 // WFI doesn't sleep if interrupts are pending (masked or not)
530 if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
531 PseudoInst::quiesceSkip(xc->tcBase());
533 PseudoInst::quiesce(xc->tcBase());
536 wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
537 { "code" : wfiCode, "predicate_test" : predicateTest },
538 ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
539 header_output += BasicDeclare.subst(wfiIop)
540 decoder_output += BasicConstructor.subst(wfiIop)
541 exec_output += QuiescePredOpExecute.subst(wfiIop)
545 System *sys = xc->tcBase()->getSystemPtr();
546 for (int x = 0; x < sys->numContexts(); x++) {
547 ThreadContext *oc = sys->getThreadContext(x);
548 if (oc == xc->tcBase())
550 // Wake CPU with interrupt if they were sleeping
551 if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
552 // Post Interrupt and wake cpu if needed
553 oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
557 sevIop = InstObjParams("sev", "SevInst", "PredOp", \
558 { "code" : sevCode, "predicate_test" : predicateTest },
559 ["IsNonSpeculative", "IsSquashAfter"])
560 header_output += BasicDeclare.subst(sevIop)
561 decoder_output += BasicConstructor.subst(sevIop)
562 exec_output += PredOpExecute.subst(sevIop)
564 itIop = InstObjParams("it", "ItInst", "PredOp", \
566 "predicate_test" : predicateTest },
567 ["IsNonSpeculative", "IsSerializeAfter"])
568 header_output += BasicDeclare.subst(itIop)
569 decoder_output += BasicConstructor.subst(itIop)
570 exec_output += PredOpExecute.subst(itIop)
573 return new UndefinedInstruction;
575 return new UndefinedInstruction(machInst, true);
577 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
578 { "code": unknownCode,
579 "predicate_test": predicateTest })
580 header_output += BasicDeclare.subst(unknownIop)
581 decoder_output += BasicConstructor.subst(unknownIop)
582 exec_output += PredOpExecute.subst(unknownIop)
585 Dest = bits(Op1, imm2, imm1);
587 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
589 "predicate_test": predicateTest }, [])
590 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
591 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
592 exec_output += PredOpExecute.subst(ubfxIop)
595 int32_t resTemp = bits(Op1, imm2, imm1);
596 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
598 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
600 "predicate_test": predicateTest }, [])
601 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
602 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
603 exec_output += PredOpExecute.subst(sbfxIop)
606 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
608 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
610 "predicate_test": predicateTest }, [])
611 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
612 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
613 exec_output += PredOpExecute.subst(bfcIop)
616 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
617 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
619 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
621 "predicate_test": predicateTest }, [])
622 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
623 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
624 exec_output += PredOpExecute.subst(bfiIop)
628 if (cpsr.mode == MODE_USER) {
630 return new UndefinedInstruction;
632 return new UndefinedInstruction(false, mnemonic);
637 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
639 "predicate_test": predicateTest }, [])
640 header_output += RegRegOpDeclare.subst(mrc15Iop)
641 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
642 exec_output += PredOpExecute.subst(mrc15Iop)
647 if (cpsr.mode == MODE_USER) {
649 return new UndefinedInstruction;
651 return new UndefinedInstruction(false, mnemonic);
655 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
657 "predicate_test": predicateTest },
658 ["IsSerializeAfter","IsNonSpeculative"])
659 header_output += RegRegOpDeclare.subst(mcr15Iop)
660 decoder_output += RegRegOpConstructor.subst(mcr15Iop)
661 exec_output += PredOpExecute.subst(mcr15Iop)
663 mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
664 { "code": "Dest = MiscOp1;",
665 "predicate_test": predicateTest }, [])
666 header_output += RegRegOpDeclare.subst(mrc15UserIop)
667 decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
668 exec_output += PredOpExecute.subst(mrc15UserIop)
670 mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
671 { "code": "MiscDest = Op1",
672 "predicate_test": predicateTest },
673 ["IsSerializeAfter","IsNonSpeculative"])
674 header_output += RegRegOpDeclare.subst(mcr15UserIop)
675 decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
676 exec_output += PredOpExecute.subst(mcr15UserIop)
682 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
683 { "code": enterxCode,
684 "predicate_test": predicateTest }, [])
685 header_output += BasicDeclare.subst(enterxIop)
686 decoder_output += BasicConstructor.subst(enterxIop)
687 exec_output += PredOpExecute.subst(enterxIop)
693 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
694 { "code": leavexCode,
695 "predicate_test": predicateTest }, [])
696 header_output += BasicDeclare.subst(leavexIop)
697 decoder_output += BasicConstructor.subst(leavexIop)
698 exec_output += PredOpExecute.subst(leavexIop)
705 setendIop = InstObjParams("setend", "Setend", "ImmOp",
706 { "code": setendCode,
707 "predicate_test": predicateTest },
708 ["IsSerializeAfter","IsNonSpeculative"])
709 header_output += ImmOpDeclare.subst(setendIop)
710 decoder_output += ImmOpConstructor.subst(setendIop)
711 exec_output += PredOpExecute.subst(setendIop)
716 clrexIop = InstObjParams("clrex", "Clrex","PredOp",
718 "predicate_test": predicateTest },[])
719 header_output += BasicDeclare.subst(clrexIop)
720 decoder_output += BasicConstructor.subst(clrexIop)
721 exec_output += PredOpExecute.subst(clrexIop)
724 fault = new FlushPipe;
726 isbIop = InstObjParams("isb", "Isb", "PredOp",
728 "predicate_test": predicateTest},
729 ['IsSerializeAfter'])
730 header_output += BasicDeclare.subst(isbIop)
731 decoder_output += BasicConstructor.subst(isbIop)
732 exec_output += PredOpExecute.subst(isbIop)
735 fault = new FlushPipe;
737 dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
739 "predicate_test": predicateTest},
740 ['IsMemBarrier', 'IsSerializeAfter'])
741 header_output += BasicDeclare.subst(dsbIop)
742 decoder_output += BasicConstructor.subst(dsbIop)
743 exec_output += PredOpExecute.subst(dsbIop)
747 dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
749 "predicate_test": predicateTest},
751 header_output += BasicDeclare.subst(dmbIop)
752 decoder_output += BasicConstructor.subst(dmbIop)
753 exec_output += PredOpExecute.subst(dmbIop)
757 dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
759 "predicate_test": predicateTest})
760 header_output += BasicDeclare.subst(dbgIop)
761 decoder_output += BasicConstructor.subst(dbgIop)
762 exec_output += PredOpExecute.subst(dbgIop)
765 uint32_t mode = bits(imm, 4, 0);
766 uint32_t f = bits(imm, 5);
767 uint32_t i = bits(imm, 6);
768 uint32_t a = bits(imm, 7);
769 bool setMode = bits(imm, 8);
770 bool enable = bits(imm, 9);
773 if (cpsr.mode != MODE_USER) {
779 if (f && !sctlr.nmfi) cpsr.f = 1;
789 cpsIop = InstObjParams("cps", "Cps", "ImmOp",
791 "predicate_test": predicateTest },
792 ["IsSerializeAfter","IsNonSpeculative"])
793 header_output += ImmOpDeclare.subst(cpsIop)
794 decoder_output += ImmOpConstructor.subst(cpsIop)
795 exec_output += PredOpExecute.subst(cpsIop)