src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43     if (FullSystem) {
  44         fault = new SupervisorCall;
  45     } else {
  46         fault = new SupervisorCall(machInst);
  47     }
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest },
  53                            ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
  54     header_output = BasicDeclare.subst(svcIop)
  55     decoder_output = BasicConstructor.subst(svcIop)
  56     exec_output = PredOpExecute.subst(svcIop)
  57
  58 }};
  59
  60 let {{
  61
  62     header_output = decoder_output = exec_output = ""
  63
  64     mrsCpsrCode = '''
  65         CPSR cpsr = Cpsr;
  66         cpsr.nz = CondCodesNZ;
  67         cpsr.c = CondCodesC;
  68         cpsr.v = CondCodesV;
  69         cpsr.ge = CondCodesGE;
  70         Dest = cpsr & 0xF8FF03DF
  71     '''
  72
  73     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  74                                { "code": mrsCpsrCode,
  75                                  "predicate_test": condPredicateTest },
  76                                ["IsSerializeBefore"])
  77     header_output += MrsDeclare.subst(mrsCpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  79     exec_output += PredOpExecute.subst(mrsCpsrIop)
  80
  81     mrsSpsrCode = "Dest = Spsr"
  82     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  83                                { "code": mrsSpsrCode,
  84                                  "predicate_test": predicateTest },
  85                                ["IsSerializeBefore"])
  86     header_output += MrsDeclare.subst(mrsSpsrIop)
  87     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  88     exec_output += PredOpExecute.subst(mrsSpsrIop)
  89
  90     msrCpsrRegCode = '''
  91         SCTLR sctlr = Sctlr;
  92         CPSR old_cpsr = Cpsr;
  93         old_cpsr.nz = CondCodesNZ;
  94         old_cpsr.c = CondCodesC;
  95         old_cpsr.v = CondCodesV;
  96         old_cpsr.ge = CondCodesGE;
  97
  98         CPSR new_cpsr =
  99             cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
 100         Cpsr = ~CondCodesMask & new_cpsr;
 101         CondCodesNZ = new_cpsr.nz;
 102         CondCodesC = new_cpsr.c;
 103         CondCodesV = new_cpsr.v;
 104         CondCodesGE = new_cpsr.ge;
 105     '''
 106     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
 107                                   { "code": msrCpsrRegCode,
 108                                     "predicate_test": condPredicateTest },
 109                                   ["IsSerializeAfter","IsNonSpeculative"])
 110     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
 111     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
 112     exec_output += PredOpExecute.subst(msrCpsrRegIop)
 113
 114     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
 115     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 116                                   { "code": msrSpsrRegCode,
 117                                     "predicate_test": predicateTest },
 118                                   ["IsSerializeAfter","IsNonSpeculative"])
 119     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 120     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 121     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 122
 123     msrCpsrImmCode = '''
 124         SCTLR sctlr = Sctlr;
 125         CPSR old_cpsr = Cpsr;
 126         old_cpsr.nz = CondCodesNZ;
 127         old_cpsr.c = CondCodesC;
 128         old_cpsr.v = CondCodesV;
 129         old_cpsr.ge = CondCodesGE;
 130         CPSR new_cpsr =
 131             cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
 132         Cpsr = ~CondCodesMask & new_cpsr;
 133         CondCodesNZ = new_cpsr.nz;
 134         CondCodesC = new_cpsr.c;
 135         CondCodesV = new_cpsr.v;
 136         CondCodesGE = new_cpsr.ge;
 137     '''
 138     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 139                                   { "code": msrCpsrImmCode,
 140                                     "predicate_test": condPredicateTest },
 141                                   ["IsSerializeAfter","IsNonSpeculative"])
 142     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 143     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 144     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 145
 146     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 147     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 148                                   { "code": msrSpsrImmCode,
 149                                     "predicate_test": predicateTest },
 150                                   ["IsSerializeAfter","IsNonSpeculative"])
 151     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 152     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 153     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 154
 155     revCode = '''
 156     uint32_t val = Op1;
 157     Dest = swap_byte(val);
 158     '''
 159     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 160                            { "code": revCode,
 161                              "predicate_test": predicateTest }, [])
 162     header_output += RegRegOpDeclare.subst(revIop)
 163     decoder_output += RegRegOpConstructor.subst(revIop)
 164     exec_output += PredOpExecute.subst(revIop)
 165
 166     rev16Code = '''
 167     uint32_t val = Op1;
 168     Dest = (bits(val, 15, 8) << 0) |
 169            (bits(val, 7, 0) << 8) |
 170            (bits(val, 31, 24) << 16) |
 171            (bits(val, 23, 16) << 24);
 172     '''
 173     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 174                              { "code": rev16Code,
 175                                "predicate_test": predicateTest }, [])
 176     header_output += RegRegOpDeclare.subst(rev16Iop)
 177     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 178     exec_output += PredOpExecute.subst(rev16Iop)
 179
 180     revshCode = '''
 181     uint16_t val = Op1;
 182     Dest = sext<16>(swap_byte(val));
 183     '''
 184     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 185                              { "code": revshCode,
 186                                "predicate_test": predicateTest }, [])
 187     header_output += RegRegOpDeclare.subst(revshIop)
 188     decoder_output += RegRegOpConstructor.subst(revshIop)
 189     exec_output += PredOpExecute.subst(revshIop)
 190
 191     rbitCode = '''
 192     uint8_t *opBytes = (uint8_t *)&Op1;
 193     uint32_t resTemp;
 194     uint8_t *destBytes = (uint8_t *)&resTemp;
 195     // This reverses the bytes and bits of the input, or so says the
 196     // internet.
 197     for (int i = 0; i < 4; i++) {
 198         uint32_t temp = opBytes[i];
 199         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 200         destBytes[3 - i] = (temp * 0x10101) >> 16;
 201     }
 202     Dest = resTemp;
 203     '''
 204     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 205                             { "code": rbitCode,
 206                               "predicate_test": predicateTest }, [])
 207     header_output += RegRegOpDeclare.subst(rbitIop)
 208     decoder_output += RegRegOpConstructor.subst(rbitIop)
 209     exec_output += PredOpExecute.subst(rbitIop)
 210
 211     clzCode = '''
 212         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 213     '''
 214     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 215                            { "code": clzCode,
 216                              "predicate_test": predicateTest }, [])
 217     header_output += RegRegOpDeclare.subst(clzIop)
 218     decoder_output += RegRegOpConstructor.subst(clzIop)
 219     exec_output += PredOpExecute.subst(clzIop)
 220
 221     ssatCode = '''
 222         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 223         int32_t res;
 224         if (satInt(res, operand, imm))
 225             CpsrQ = 1 << 27;
 226         Dest = res;
 227     '''
 228     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 229                             { "code": ssatCode,
 230                               "predicate_test": pickPredicate(ssatCode) }, [])
 231     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 232     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 233     exec_output += PredOpExecute.subst(ssatIop)
 234
 235     usatCode = '''
 236         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 237         int32_t res;
 238         if (uSatInt(res, operand, imm))
 239             CpsrQ = 1 << 27;
 240         Dest = res;
 241     '''
 242     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 243                             { "code": usatCode,
 244                               "predicate_test": pickPredicate(usatCode) }, [])
 245     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 246     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 247     exec_output += PredOpExecute.subst(usatIop)
 248
 249     ssat16Code = '''
 250         int32_t res;
 251         uint32_t resTemp = 0;
 252         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 253         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 254         if (satInt(res, argLow, imm))
 255             CpsrQ = 1 << 27;
 256         replaceBits(resTemp, 15, 0, res);
 257         if (satInt(res, argHigh, imm))
 258             CpsrQ = 1 << 27;
 259         replaceBits(resTemp, 31, 16, res);
 260         Dest = resTemp;
 261     '''
 262     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 263                               { "code": ssat16Code,
 264                                 "predicate_test": pickPredicate(ssat16Code) }, [])
 265     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 266     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 267     exec_output += PredOpExecute.subst(ssat16Iop)
 268
 269     usat16Code = '''
 270         int32_t res;
 271         uint32_t resTemp = 0;
 272         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 273         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 274         if (uSatInt(res, argLow, imm))
 275             CpsrQ = 1 << 27;
 276         replaceBits(resTemp, 15, 0, res);
 277         if (uSatInt(res, argHigh, imm))
 278             CpsrQ = 1 << 27;
 279         replaceBits(resTemp, 31, 16, res);
 280         Dest = resTemp;
 281     '''
 282     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 283                               { "code": usat16Code,
 284                                 "predicate_test": pickPredicate(usat16Code) }, [])
 285     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 286     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 287     exec_output += PredOpExecute.subst(usat16Iop)
 288
 289     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 290                             { "code":
 291                               "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
 292                               "predicate_test": predicateTest }, [])
 293     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 294     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 295     exec_output += PredOpExecute.subst(sxtbIop)
 296
 297     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 298                              { "code":
 299                                '''
 300                                    Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
 301                                           Op1;
 302                                ''',
 303                                "predicate_test": predicateTest }, [])
 304     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 305     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 306     exec_output += PredOpExecute.subst(sxtabIop)
 307
 308     sxtb16Code = '''
 309     uint32_t resTemp = 0;
 310     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 311     replaceBits(resTemp, 31, 16,
 312                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 313     Dest = resTemp;
 314     '''
 315     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 316                               { "code": sxtb16Code,
 317                                 "predicate_test": predicateTest }, [])
 318     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 319     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 320     exec_output += PredOpExecute.subst(sxtb16Iop)
 321
 322     sxtab16Code = '''
 323     uint32_t resTemp = 0;
 324     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 325                                         bits(Op1, 15, 0));
 326     replaceBits(resTemp, 31, 16,
 327                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 328                 bits(Op1, 31, 16));
 329     Dest = resTemp;
 330     '''
 331     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 332                                { "code": sxtab16Code,
 333                                  "predicate_test": predicateTest }, [])
 334     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 335     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 336     exec_output += PredOpExecute.subst(sxtab16Iop)
 337
 338     sxthCode = '''
 339     uint64_t rotated = (uint32_t)Op1;
 340     rotated = (rotated | (rotated << 32)) >> imm;
 341     Dest = sext<16>((uint16_t)rotated);
 342     '''
 343     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 344                               { "code": sxthCode,
 345                                 "predicate_test": predicateTest }, [])
 346     header_output += RegImmRegOpDeclare.subst(sxthIop)
 347     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 348     exec_output += PredOpExecute.subst(sxthIop)
 349
 350     sxtahCode = '''
 351     uint64_t rotated = (uint32_t)Op2;
 352     rotated = (rotated | (rotated << 32)) >> imm;
 353     Dest = sext<16>((uint16_t)rotated) + Op1;
 354     '''
 355     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 356                              { "code": sxtahCode,
 357                                "predicate_test": predicateTest }, [])
 358     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 359     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 360     exec_output += PredOpExecute.subst(sxtahIop)
 361
 362     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 363                             { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
 364                               "predicate_test": predicateTest }, [])
 365     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 366     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 367     exec_output += PredOpExecute.subst(uxtbIop)
 368
 369     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 370                              { "code":
 371                                "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
 372                                "predicate_test": predicateTest }, [])
 373     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 374     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 375     exec_output += PredOpExecute.subst(uxtabIop)
 376
 377     uxtb16Code = '''
 378     uint32_t resTemp = 0;
 379     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 380     replaceBits(resTemp, 31, 16,
 381                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 382     Dest = resTemp;
 383     '''
 384     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 385                               { "code": uxtb16Code,
 386                                 "predicate_test": predicateTest }, [])
 387     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 388     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 389     exec_output += PredOpExecute.subst(uxtb16Iop)
 390
 391     uxtab16Code = '''
 392     uint32_t resTemp = 0;
 393     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 394                                         bits(Op1, 15, 0));
 395     replaceBits(resTemp, 31, 16,
 396                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 397                 bits(Op1, 31, 16));
 398     Dest = resTemp;
 399     '''
 400     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 401                                { "code": uxtab16Code,
 402                                  "predicate_test": predicateTest }, [])
 403     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 404     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 405     exec_output += PredOpExecute.subst(uxtab16Iop)
 406
 407     uxthCode = '''
 408     uint64_t rotated = (uint32_t)Op1;
 409     rotated = (rotated | (rotated << 32)) >> imm;
 410     Dest = (uint16_t)rotated;
 411     '''
 412     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 413                               { "code": uxthCode,
 414                                 "predicate_test": predicateTest }, [])
 415     header_output += RegImmRegOpDeclare.subst(uxthIop)
 416     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 417     exec_output += PredOpExecute.subst(uxthIop)
 418
 419     uxtahCode = '''
 420     uint64_t rotated = (uint32_t)Op2;
 421     rotated = (rotated | (rotated << 32)) >> imm;
 422     Dest = (uint16_t)rotated + Op1;
 423     '''
 424     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 425                              { "code": uxtahCode,
 426                                "predicate_test": predicateTest }, [])
 427     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 428     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 429     exec_output += PredOpExecute.subst(uxtahIop)
 430
 431     selCode = '''
 432         uint32_t resTemp = 0;
 433         for (unsigned i = 0; i < 4; i++) {
 434             int low = i * 8;
 435             int high = low + 7;
 436             replaceBits(resTemp, high, low,
 437                         bits(CondCodesGE, i) ?
 438                             bits(Op1, high, low) : bits(Op2, high, low));
 439         }
 440         Dest = resTemp;
 441     '''
 442     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 443                            { "code": selCode,
 444                              "predicate_test": predicateTest }, [])
 445     header_output += RegRegRegOpDeclare.subst(selIop)
 446     decoder_output += RegRegRegOpConstructor.subst(selIop)
 447     exec_output += PredOpExecute.subst(selIop)
 448
 449     usad8Code = '''
 450         uint32_t resTemp = 0;
 451         for (unsigned i = 0; i < 4; i++) {
 452             int low = i * 8;
 453             int high = low + 7;
 454             int32_t diff = bits(Op1, high, low) -
 455                            bits(Op2, high, low);
 456             resTemp += ((diff < 0) ? -diff : diff);
 457         }
 458         Dest = resTemp;
 459     '''
 460     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 461                              { "code": usad8Code,
 462                                "predicate_test": predicateTest }, [])
 463     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 464     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 465     exec_output += PredOpExecute.subst(usad8Iop)
 466
 467     usada8Code = '''
 468         uint32_t resTemp = 0;
 469         for (unsigned i = 0; i < 4; i++) {
 470             int low = i * 8;
 471             int high = low + 7;
 472             int32_t diff = bits(Op1, high, low) -
 473                            bits(Op2, high, low);
 474             resTemp += ((diff < 0) ? -diff : diff);
 475         }
 476         Dest = Op3 + resTemp;
 477     '''
 478     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 479                               { "code": usada8Code,
 480                                 "predicate_test": predicateTest }, [])
 481     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 482     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 483     exec_output += PredOpExecute.subst(usada8Iop)
 484
 485     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 486     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 487     header_output += BasicDeclare.subst(bkptIop)
 488     decoder_output += BasicConstructor.subst(bkptIop)
 489     exec_output += BasicExecute.subst(bkptIop)
 490
 491     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 492             { "code" : "", "predicate_test" : predicateTest },
 493             ['IsNop'])
 494     header_output += BasicDeclare.subst(nopIop)
 495     decoder_output += BasicConstructor.subst(nopIop)
 496     exec_output += PredOpExecute.subst(nopIop)
 497
 498     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 499             { "code" : "", "predicate_test" : predicateTest })
 500     header_output += BasicDeclare.subst(yieldIop)
 501     decoder_output += BasicConstructor.subst(yieldIop)
 502     exec_output += PredOpExecute.subst(yieldIop)
 503
 504     wfeCode = '''
 505     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
 506     if (SevMailbox == 1) {
 507         SevMailbox = 0;
 508         PseudoInst::quiesceSkip(xc->tcBase());
 509     } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
 510         PseudoInst::quiesceSkip(xc->tcBase());
 511     } else {
 512         PseudoInst::quiesce(xc->tcBase());
 513     }
 514     '''
 515     wfePredFixUpCode = '''
 516     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
 517     // and SEV interrupts
 518     SevMailbox = 1;
 519     '''
 520     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 521             { "code" : wfeCode,
 522               "pred_fixup" : wfePredFixUpCode,
 523               "predicate_test" : predicateTest },
 524             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 525     header_output += BasicDeclare.subst(wfeIop)
 526     decoder_output += BasicConstructor.subst(wfeIop)
 527     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 528
 529     wfiCode = '''
 530     // WFI doesn't sleep if interrupts are pending (masked or not)
 531     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
 532         PseudoInst::quiesceSkip(xc->tcBase());
 533     } else {
 534         PseudoInst::quiesce(xc->tcBase());
 535     }
 536     '''
 537     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 538             { "code" : wfiCode, "predicate_test" : predicateTest },
 539             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 540     header_output += BasicDeclare.subst(wfiIop)
 541     decoder_output += BasicConstructor.subst(wfiIop)
 542     exec_output += QuiescePredOpExecute.subst(wfiIop)
 543
 544     sevCode = '''
 545     SevMailbox = 1;
 546     System *sys = xc->tcBase()->getSystemPtr();
 547     for (int x = 0; x < sys->numContexts(); x++) {
 548         ThreadContext *oc = sys->getThreadContext(x);
 549         if (oc == xc->tcBase())
 550             continue;
 551         // Wake CPU with interrupt if they were sleeping
 552         if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 553             // Post Interrupt and wake cpu if needed
 554             oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
 555         }
 556     }
 557     '''
 558     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 559             { "code" : sevCode, "predicate_test" : predicateTest },
 560             ["IsNonSpeculative", "IsSquashAfter"])
 561     header_output += BasicDeclare.subst(sevIop)
 562     decoder_output += BasicConstructor.subst(sevIop)
 563     exec_output += PredOpExecute.subst(sevIop)
 564
 565     itIop = InstObjParams("it", "ItInst", "PredOp", \
 566             { "code" : ";",
 567               "predicate_test" : predicateTest },
 568             ["IsNonSpeculative", "IsSerializeAfter"])
 569     header_output += BasicDeclare.subst(itIop)
 570     decoder_output += BasicConstructor.subst(itIop)
 571     exec_output += PredOpExecute.subst(itIop)
 572     unknownCode = '''
 573     if (FullSystem)
 574         return new UndefinedInstruction;
 575     else
 576         return new UndefinedInstruction(machInst, true);
 577     '''
 578     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 579                                { "code": unknownCode,
 580                                  "predicate_test": predicateTest })
 581     header_output += BasicDeclare.subst(unknownIop)
 582     decoder_output += BasicConstructor.subst(unknownIop)
 583     exec_output += PredOpExecute.subst(unknownIop)
 584
 585     ubfxCode = '''
 586         Dest = bits(Op1, imm2, imm1);
 587     '''
 588     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 589                             { "code": ubfxCode,
 590                               "predicate_test": predicateTest }, [])
 591     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 592     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 593     exec_output += PredOpExecute.subst(ubfxIop)
 594
 595     sbfxCode = '''
 596         int32_t resTemp = bits(Op1, imm2, imm1);
 597         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 598     '''
 599     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 600                             { "code": sbfxCode,
 601                               "predicate_test": predicateTest }, [])
 602     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 603     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 604     exec_output += PredOpExecute.subst(sbfxIop)
 605
 606     bfcCode = '''
 607         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 608     '''
 609     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 610                            { "code": bfcCode,
 611                              "predicate_test": predicateTest }, [])
 612     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 613     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 614     exec_output += PredOpExecute.subst(bfcIop)
 615
 616     bfiCode = '''
 617         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 618         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 619     '''
 620     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 621                            { "code": bfiCode,
 622                              "predicate_test": predicateTest }, [])
 623     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 624     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 625     exec_output += PredOpExecute.subst(bfiIop)
 626
 627     mrc15code = '''
 628     CPSR cpsr = Cpsr;
 629     if (cpsr.mode == MODE_USER) {
 630         if (FullSystem)
 631             return new UndefinedInstruction;
 632         else
 633             return new UndefinedInstruction(false, mnemonic);
 634     }
 635     Dest = MiscOp1;
 636     '''
 637
 638     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 639                              { "code": mrc15code,
 640                                "predicate_test": predicateTest }, [])
 641     header_output += RegRegOpDeclare.subst(mrc15Iop)
 642     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 643     exec_output += PredOpExecute.subst(mrc15Iop)
 644
 645
 646     mcr15code = '''
 647     CPSR cpsr = Cpsr;
 648     if (cpsr.mode == MODE_USER) {
 649         if (FullSystem)
 650             return new UndefinedInstruction;
 651         else
 652             return new UndefinedInstruction(false, mnemonic);
 653     }
 654     MiscDest = Op1;
 655     '''
 656     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 657                              { "code": mcr15code,
 658                                "predicate_test": predicateTest },
 659                                ["IsSerializeAfter","IsNonSpeculative"])
 660     header_output += RegRegOpDeclare.subst(mcr15Iop)
 661     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 662     exec_output += PredOpExecute.subst(mcr15Iop)
 663
 664     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 665                                  { "code": "Dest = MiscOp1;",
 666                                    "predicate_test": predicateTest }, [])
 667     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 668     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 669     exec_output += PredOpExecute.subst(mrc15UserIop)
 670
 671     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 672                                  { "code": "MiscDest = Op1",
 673                                    "predicate_test": predicateTest },
 674                                    ["IsSerializeAfter","IsNonSpeculative"])
 675     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 676     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 677     exec_output += PredOpExecute.subst(mcr15UserIop)
 678
 679     enterxCode = '''
 680         NextThumb = true;
 681         NextJazelle = true;
 682     '''
 683     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 684                               { "code": enterxCode,
 685                                 "predicate_test": predicateTest }, [])
 686     header_output += BasicDeclare.subst(enterxIop)
 687     decoder_output += BasicConstructor.subst(enterxIop)
 688     exec_output += PredOpExecute.subst(enterxIop)
 689
 690     leavexCode = '''
 691         NextThumb = true;
 692         NextJazelle = false;
 693     '''
 694     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 695                               { "code": leavexCode,
 696                                 "predicate_test": predicateTest }, [])
 697     header_output += BasicDeclare.subst(leavexIop)
 698     decoder_output += BasicConstructor.subst(leavexIop)
 699     exec_output += PredOpExecute.subst(leavexIop)
 700
 701     setendCode = '''
 702         CPSR cpsr = Cpsr;
 703         cpsr.e = imm;
 704         Cpsr = cpsr;
 705     '''
 706     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 707                               { "code": setendCode,
 708                                 "predicate_test": predicateTest },
 709                               ["IsSerializeAfter","IsNonSpeculative"])
 710     header_output += ImmOpDeclare.subst(setendIop)
 711     decoder_output += ImmOpConstructor.subst(setendIop)
 712     exec_output += PredOpExecute.subst(setendIop)
 713
 714     clrexCode = '''
 715         LLSCLock = 0;
 716     '''
 717     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 718                              { "code": clrexCode,
 719                                "predicate_test": predicateTest },[])
 720     header_output += BasicDeclare.subst(clrexIop)
 721     decoder_output += BasicConstructor.subst(clrexIop)
 722     exec_output += PredOpExecute.subst(clrexIop)
 723
 724     isbCode = '''
 725         fault = new FlushPipe;
 726     '''
 727     isbIop = InstObjParams("isb", "Isb", "PredOp",
 728                              {"code": isbCode,
 729                                "predicate_test": predicateTest},
 730                                 ['IsSerializeAfter'])
 731     header_output += BasicDeclare.subst(isbIop)
 732     decoder_output += BasicConstructor.subst(isbIop)
 733     exec_output += PredOpExecute.subst(isbIop)
 734
 735     dsbCode = '''
 736         fault = new FlushPipe;
 737     '''
 738     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 739                              {"code": dsbCode,
 740                                "predicate_test": predicateTest},
 741                               ['IsMemBarrier', 'IsSerializeAfter'])
 742     header_output += BasicDeclare.subst(dsbIop)
 743     decoder_output += BasicConstructor.subst(dsbIop)
 744     exec_output += PredOpExecute.subst(dsbIop)
 745
 746     dmbCode = '''
 747     '''
 748     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 749                              {"code": dmbCode,
 750                                "predicate_test": predicateTest},
 751                                ['IsMemBarrier'])
 752     header_output += BasicDeclare.subst(dmbIop)
 753     decoder_output += BasicConstructor.subst(dmbIop)
 754     exec_output += PredOpExecute.subst(dmbIop)
 755
 756     dbgCode = '''
 757     '''
 758     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 759                              {"code": dbgCode,
 760                                "predicate_test": predicateTest})
 761     header_output += BasicDeclare.subst(dbgIop)
 762     decoder_output += BasicConstructor.subst(dbgIop)
 763     exec_output += PredOpExecute.subst(dbgIop)
 764
 765     cpsCode = '''
 766     uint32_t mode = bits(imm, 4, 0);
 767     uint32_t f = bits(imm, 5);
 768     uint32_t i = bits(imm, 6);
 769     uint32_t a = bits(imm, 7);
 770     bool setMode = bits(imm, 8);
 771     bool enable = bits(imm, 9);
 772     CPSR cpsr = Cpsr;
 773     SCTLR sctlr = Sctlr;
 774     if (cpsr.mode != MODE_USER) {
 775         if (enable) {
 776             if (f) cpsr.f = 0;
 777             if (i) cpsr.i = 0;
 778             if (a) cpsr.a = 0;
 779         } else {
 780             if (f && !sctlr.nmfi) cpsr.f = 1;
 781             if (i) cpsr.i = 1;
 782             if (a) cpsr.a = 1;
 783         }
 784         if (setMode) {
 785             cpsr.mode = mode;
 786         }
 787     }
 788     Cpsr = cpsr;
 789     '''
 790     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 791                            { "code": cpsCode,
 792                              "predicate_test": predicateTest },
 793                            ["IsSerializeAfter","IsNonSpeculative"])
 794     header_output += ImmOpDeclare.subst(cpsIop)
 795     decoder_output += ImmOpConstructor.subst(cpsIop)
 796     exec_output += PredOpExecute.subst(cpsIop)
 797 }};