3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are
17 // met: redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer;
19 // redistributions in binary form must reproduce the above copyright
20 // notice, this list of conditions and the following disclaimer in the
21 // documentation and/or other materials provided with the distribution;
22 // neither the name of the copyright holders nor the names of its
23 // contributors may be used to endorse or promote products derived from
24 // this software without specific prior written permission.
26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 // Authors: Gabe Black
44 fault = new SupervisorCall;
46 fault = new SupervisorCall(machInst);
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
52 "predicate_test": predicateTest }, ["IsSyscall"])
53 header_output = BasicDeclare.subst(svcIop)
54 decoder_output = BasicConstructor.subst(svcIop)
55 exec_output = PredOpExecute.subst(svcIop)
61 header_output = decoder_output = exec_output = ""
63 mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65 { "code": mrsCpsrCode,
66 "predicate_test": predicateTest }, [])
67 header_output += MrsDeclare.subst(mrsCpsrIop)
68 decoder_output += MrsConstructor.subst(mrsCpsrIop)
69 exec_output += PredOpExecute.subst(mrsCpsrIop)
71 mrsSpsrCode = "Dest = Spsr"
72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
73 { "code": mrsSpsrCode,
74 "predicate_test": predicateTest }, [])
75 header_output += MrsDeclare.subst(mrsSpsrIop)
76 decoder_output += MrsConstructor.subst(mrsSpsrIop)
77 exec_output += PredOpExecute.subst(mrsSpsrIop)
81 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
82 Cpsr = ~CondCodesMask & newCpsr;
83 CondCodes = CondCodesMask & newCpsr;
85 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
86 { "code": msrCpsrRegCode,
87 "predicate_test": predicateTest }, [])
88 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
89 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
90 exec_output += PredOpExecute.subst(msrCpsrRegIop)
92 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
93 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
94 { "code": msrSpsrRegCode,
95 "predicate_test": predicateTest }, [])
96 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
97 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
98 exec_output += PredOpExecute.subst(msrSpsrRegIop)
102 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
103 Cpsr = ~CondCodesMask & newCpsr;
104 CondCodes = CondCodesMask & newCpsr;
106 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
107 { "code": msrCpsrImmCode,
108 "predicate_test": predicateTest }, [])
109 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
110 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
111 exec_output += PredOpExecute.subst(msrCpsrImmIop)
113 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
114 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
115 { "code": msrSpsrImmCode,
116 "predicate_test": predicateTest }, [])
117 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
118 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
119 exec_output += PredOpExecute.subst(msrSpsrImmIop)
123 Dest = swap_byte(val);
125 revIop = InstObjParams("rev", "Rev", "RevOp",
127 "predicate_test": predicateTest }, [])
128 header_output += RevOpDeclare.subst(revIop)
129 decoder_output += RevOpConstructor.subst(revIop)
130 exec_output += PredOpExecute.subst(revIop)
134 Dest = (bits(val, 15, 8) << 0) |
135 (bits(val, 7, 0) << 8) |
136 (bits(val, 31, 24) << 16) |
137 (bits(val, 23, 16) << 24);
139 rev16Iop = InstObjParams("rev16", "Rev16", "RevOp",
141 "predicate_test": predicateTest }, [])
142 header_output += RevOpDeclare.subst(rev16Iop)
143 decoder_output += RevOpConstructor.subst(rev16Iop)
144 exec_output += PredOpExecute.subst(rev16Iop)
148 Dest = sext<16>(swap_byte(val));
150 revshIop = InstObjParams("revsh", "Revsh", "RevOp",
152 "predicate_test": predicateTest }, [])
153 header_output += RevOpDeclare.subst(revshIop)
154 decoder_output += RevOpConstructor.subst(revshIop)
155 exec_output += PredOpExecute.subst(revshIop)
158 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
160 if (satInt(res, operand, imm))
161 CondCodes = CondCodes | (1 << 27);
163 CondCodes = CondCodes;
166 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
168 "predicate_test": predicateTest }, [])
169 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
170 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
171 exec_output += PredOpExecute.subst(ssatIop)
174 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
176 if (uSatInt(res, operand, imm))
177 CondCodes = CondCodes | (1 << 27);
179 CondCodes = CondCodes;
182 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
184 "predicate_test": predicateTest }, [])
185 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
186 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
187 exec_output += PredOpExecute.subst(usatIop)
191 uint32_t resTemp = 0;
192 CondCodes = CondCodes;
193 int32_t argLow = sext<16>(bits(Op1, 15, 0));
194 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
195 if (satInt(res, argLow, imm))
196 CondCodes = CondCodes | (1 << 27);
197 replaceBits(resTemp, 15, 0, res);
198 if (satInt(res, argHigh, imm))
199 CondCodes = CondCodes | (1 << 27);
200 replaceBits(resTemp, 31, 16, res);
203 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
204 { "code": ssat16Code,
205 "predicate_test": predicateTest }, [])
206 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
207 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
208 exec_output += PredOpExecute.subst(ssat16Iop)
212 uint32_t resTemp = 0;
213 CondCodes = CondCodes;
214 int32_t argLow = sext<16>(bits(Op1, 15, 0));
215 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
216 if (uSatInt(res, argLow, imm))
217 CondCodes = CondCodes | (1 << 27);
218 replaceBits(resTemp, 15, 0, res);
219 if (uSatInt(res, argHigh, imm))
220 CondCodes = CondCodes | (1 << 27);
221 replaceBits(resTemp, 31, 16, res);
224 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
225 { "code": usat16Code,
226 "predicate_test": predicateTest }, [])
227 header_output += RegImmRegOpDeclare.subst(usat16Iop)
228 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
229 exec_output += PredOpExecute.subst(usat16Iop)
231 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
233 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
234 "predicate_test": predicateTest }, [])
235 header_output += RegImmRegOpDeclare.subst(sxtbIop)
236 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
237 exec_output += PredOpExecute.subst(sxtbIop)
239 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
242 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
245 "predicate_test": predicateTest }, [])
246 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
247 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
248 exec_output += PredOpExecute.subst(sxtabIop)
251 uint32_t resTemp = 0;
252 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
253 replaceBits(resTemp, 31, 16,
254 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
257 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
258 { "code": sxtb16Code,
259 "predicate_test": predicateTest }, [])
260 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
261 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
262 exec_output += PredOpExecute.subst(sxtb16Iop)
265 uint32_t resTemp = 0;
266 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
268 replaceBits(resTemp, 31, 16,
269 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
273 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
274 { "code": sxtab16Code,
275 "predicate_test": predicateTest }, [])
276 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
277 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
278 exec_output += PredOpExecute.subst(sxtab16Iop)
281 uint64_t rotated = (uint32_t)Op1;
282 rotated = (rotated | (rotated << 32)) >> imm;
283 Dest = sext<16>((uint16_t)rotated);
285 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
287 "predicate_test": predicateTest }, [])
288 header_output += RegImmRegOpDeclare.subst(sxthIop)
289 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
290 exec_output += PredOpExecute.subst(sxthIop)
293 uint64_t rotated = (uint32_t)Op2;
294 rotated = (rotated | (rotated << 32)) >> imm;
295 Dest = sext<16>((uint16_t)rotated) + Op1;
297 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
299 "predicate_test": predicateTest }, [])
300 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
301 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
302 exec_output += PredOpExecute.subst(sxtahIop)
304 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
305 { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
306 "predicate_test": predicateTest }, [])
307 header_output += RegImmRegOpDeclare.subst(uxtbIop)
308 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
309 exec_output += PredOpExecute.subst(uxtbIop)
311 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
313 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
314 "predicate_test": predicateTest }, [])
315 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
316 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
317 exec_output += PredOpExecute.subst(uxtabIop)
320 uint32_t resTemp = 0;
321 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
322 replaceBits(resTemp, 31, 16,
323 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
326 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
327 { "code": uxtb16Code,
328 "predicate_test": predicateTest }, [])
329 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
330 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
331 exec_output += PredOpExecute.subst(uxtb16Iop)
334 uint32_t resTemp = 0;
335 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
337 replaceBits(resTemp, 31, 16,
338 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
342 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
343 { "code": uxtab16Code,
344 "predicate_test": predicateTest }, [])
345 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
346 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
347 exec_output += PredOpExecute.subst(uxtab16Iop)
350 uint64_t rotated = (uint32_t)Op1;
351 rotated = (rotated | (rotated << 32)) >> imm;
352 Dest = (uint16_t)rotated;
354 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
356 "predicate_test": predicateTest }, [])
357 header_output += RegImmRegOpDeclare.subst(uxthIop)
358 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
359 exec_output += PredOpExecute.subst(uxthIop)
362 uint64_t rotated = (uint32_t)Op2;
363 rotated = (rotated | (rotated << 32)) >> imm;
364 Dest = (uint16_t)rotated + Op1;
366 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
368 "predicate_test": predicateTest }, [])
369 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
370 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
371 exec_output += PredOpExecute.subst(uxtahIop)