src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
  64     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  65                                { "code": mrsCpsrCode,
  66                                  "predicate_test": condPredicateTest },
  67                                ["IsSerializeBefore"])
  68     header_output += MrsDeclare.subst(mrsCpsrIop)
  69     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  70     exec_output += PredOpExecute.subst(mrsCpsrIop)
  71
  72     mrsSpsrCode = "Dest = Spsr"
  73     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  74                                { "code": mrsSpsrCode,
  75                                  "predicate_test": predicateTest },
  76                                ["IsSerializeBefore"])
  77     header_output += MrsDeclare.subst(mrsSpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  79     exec_output += PredOpExecute.subst(mrsSpsrIop)
  80
  81     msrCpsrRegCode = '''
  82         SCTLR sctlr = Sctlr;
  83         uint32_t newCpsr =
  84             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
  85         Cpsr = ~CondCodesMask & newCpsr;
  86         NextThumb = ((CPSR)newCpsr).t;
  87         NextJazelle = ((CPSR)newCpsr).j;
  88         ForcedItState = ((((CPSR)Op1).it2 << 2) & 0xFC)
  89                 | (((CPSR)Op1).it1 & 0x3);
  90         CondCodes = CondCodesMask & newCpsr;
  91     '''
  92     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
  93                                   { "code": msrCpsrRegCode,
  94                                     "predicate_test": condPredicateTest },
  95                                   ["IsSerializeAfter","IsNonSpeculative"])
  96     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
  97     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
  98     exec_output += PredOpExecute.subst(msrCpsrRegIop)
  99
 100     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
 101     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 102                                   { "code": msrSpsrRegCode,
 103                                     "predicate_test": predicateTest },
 104                                   ["IsSerializeAfter","IsNonSpeculative"])
 105     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 106     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 107     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 108
 109     msrCpsrImmCode = '''
 110         SCTLR sctlr = Sctlr;
 111         uint32_t newCpsr =
 112             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
 113         Cpsr = ~CondCodesMask & newCpsr;
 114         NextThumb = ((CPSR)newCpsr).t;
 115         NextJazelle = ((CPSR)newCpsr).j;
 116         ForcedItState = ((((CPSR)imm).it2 << 2) & 0xFC)
 117             | (((CPSR)imm).it1 & 0x3);
 118         CondCodes = CondCodesMask & newCpsr;
 119     '''
 120     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 121                                   { "code": msrCpsrImmCode,
 122                                     "predicate_test": condPredicateTest },
 123                                   ["IsSerializeAfter","IsNonSpeculative"])
 124     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 125     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 126     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 127
 128     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 129     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 130                                   { "code": msrSpsrImmCode,
 131                                     "predicate_test": predicateTest },
 132                                   ["IsSerializeAfter","IsNonSpeculative"])
 133     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 134     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 135     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 136
 137     revCode = '''
 138     uint32_t val = Op1;
 139     Dest = swap_byte(val);
 140     '''
 141     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 142                            { "code": revCode,
 143                              "predicate_test": predicateTest }, [])
 144     header_output += RegRegOpDeclare.subst(revIop)
 145     decoder_output += RegRegOpConstructor.subst(revIop)
 146     exec_output += PredOpExecute.subst(revIop)
 147
 148     rev16Code = '''
 149     uint32_t val = Op1;
 150     Dest = (bits(val, 15, 8) << 0) |
 151            (bits(val, 7, 0) << 8) |
 152            (bits(val, 31, 24) << 16) |
 153            (bits(val, 23, 16) << 24);
 154     '''
 155     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 156                              { "code": rev16Code,
 157                                "predicate_test": predicateTest }, [])
 158     header_output += RegRegOpDeclare.subst(rev16Iop)
 159     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 160     exec_output += PredOpExecute.subst(rev16Iop)
 161
 162     revshCode = '''
 163     uint16_t val = Op1;
 164     Dest = sext<16>(swap_byte(val));
 165     '''
 166     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 167                              { "code": revshCode,
 168                                "predicate_test": predicateTest }, [])
 169     header_output += RegRegOpDeclare.subst(revshIop)
 170     decoder_output += RegRegOpConstructor.subst(revshIop)
 171     exec_output += PredOpExecute.subst(revshIop)
 172
 173     rbitCode = '''
 174     uint8_t *opBytes = (uint8_t *)&Op1;
 175     uint32_t resTemp;
 176     uint8_t *destBytes = (uint8_t *)&resTemp;
 177     // This reverses the bytes and bits of the input, or so says the
 178     // internet.
 179     for (int i = 0; i < 4; i++) {
 180         uint32_t temp = opBytes[i];
 181         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 182         destBytes[3 - i] = (temp * 0x10101) >> 16;
 183     }
 184     Dest = resTemp;
 185     '''
 186     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 187                             { "code": rbitCode,
 188                               "predicate_test": predicateTest }, [])
 189     header_output += RegRegOpDeclare.subst(rbitIop)
 190     decoder_output += RegRegOpConstructor.subst(rbitIop)
 191     exec_output += PredOpExecute.subst(rbitIop)
 192
 193     clzCode = '''
 194         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 195     '''
 196     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 197                            { "code": clzCode,
 198                              "predicate_test": predicateTest }, [])
 199     header_output += RegRegOpDeclare.subst(clzIop)
 200     decoder_output += RegRegOpConstructor.subst(clzIop)
 201     exec_output += PredOpExecute.subst(clzIop)
 202
 203     ssatCode = '''
 204         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 205         int32_t res;
 206         if (satInt(res, operand, imm))
 207             CondCodes = CondCodes | (1 << 27);
 208         else
 209             CondCodes = CondCodes;
 210         Dest = res;
 211     '''
 212     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 213                             { "code": ssatCode,
 214                               "predicate_test": condPredicateTest }, [])
 215     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 216     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 217     exec_output += PredOpExecute.subst(ssatIop)
 218
 219     usatCode = '''
 220         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 221         int32_t res;
 222         if (uSatInt(res, operand, imm))
 223             CondCodes = CondCodes | (1 << 27);
 224         else
 225             CondCodes = CondCodes;
 226         Dest = res;
 227     '''
 228     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 229                             { "code": usatCode,
 230                               "predicate_test": condPredicateTest }, [])
 231     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 232     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 233     exec_output += PredOpExecute.subst(usatIop)
 234
 235     ssat16Code = '''
 236         int32_t res;
 237         uint32_t resTemp = 0;
 238         CondCodes = CondCodes;
 239         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 240         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 241         if (satInt(res, argLow, imm))
 242             CondCodes = CondCodes | (1 << 27);
 243         replaceBits(resTemp, 15, 0, res);
 244         if (satInt(res, argHigh, imm))
 245             CondCodes = CondCodes | (1 << 27);
 246         replaceBits(resTemp, 31, 16, res);
 247         Dest = resTemp;
 248     '''
 249     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 250                               { "code": ssat16Code,
 251                                 "predicate_test": condPredicateTest }, [])
 252     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 253     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 254     exec_output += PredOpExecute.subst(ssat16Iop)
 255
 256     usat16Code = '''
 257         int32_t res;
 258         uint32_t resTemp = 0;
 259         CondCodes = CondCodes;
 260         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 261         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 262         if (uSatInt(res, argLow, imm))
 263             CondCodes = CondCodes | (1 << 27);
 264         replaceBits(resTemp, 15, 0, res);
 265         if (uSatInt(res, argHigh, imm))
 266             CondCodes = CondCodes | (1 << 27);
 267         replaceBits(resTemp, 31, 16, res);
 268         Dest = resTemp;
 269     '''
 270     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 271                               { "code": usat16Code,
 272                                 "predicate_test": condPredicateTest }, [])
 273     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 274     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 275     exec_output += PredOpExecute.subst(usat16Iop)
 276
 277     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 278                             { "code":
 279                               "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
 280                               "predicate_test": predicateTest }, [])
 281     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 282     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 283     exec_output += PredOpExecute.subst(sxtbIop)
 284
 285     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 286                              { "code":
 287                                '''
 288                                    Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
 289                                           Op1;
 290                                ''',
 291                                "predicate_test": predicateTest }, [])
 292     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 293     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 294     exec_output += PredOpExecute.subst(sxtabIop)
 295
 296     sxtb16Code = '''
 297     uint32_t resTemp = 0;
 298     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 299     replaceBits(resTemp, 31, 16,
 300                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 301     Dest = resTemp;
 302     '''
 303     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 304                               { "code": sxtb16Code,
 305                                 "predicate_test": predicateTest }, [])
 306     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 307     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 308     exec_output += PredOpExecute.subst(sxtb16Iop)
 309
 310     sxtab16Code = '''
 311     uint32_t resTemp = 0;
 312     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 313                                         bits(Op1, 15, 0));
 314     replaceBits(resTemp, 31, 16,
 315                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 316                 bits(Op1, 31, 16));
 317     Dest = resTemp;
 318     '''
 319     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 320                                { "code": sxtab16Code,
 321                                  "predicate_test": predicateTest }, [])
 322     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 323     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 324     exec_output += PredOpExecute.subst(sxtab16Iop)
 325
 326     sxthCode = '''
 327     uint64_t rotated = (uint32_t)Op1;
 328     rotated = (rotated | (rotated << 32)) >> imm;
 329     Dest = sext<16>((uint16_t)rotated);
 330     '''
 331     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 332                               { "code": sxthCode,
 333                                 "predicate_test": predicateTest }, [])
 334     header_output += RegImmRegOpDeclare.subst(sxthIop)
 335     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 336     exec_output += PredOpExecute.subst(sxthIop)
 337
 338     sxtahCode = '''
 339     uint64_t rotated = (uint32_t)Op2;
 340     rotated = (rotated | (rotated << 32)) >> imm;
 341     Dest = sext<16>((uint16_t)rotated) + Op1;
 342     '''
 343     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 344                              { "code": sxtahCode,
 345                                "predicate_test": predicateTest }, [])
 346     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 347     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 348     exec_output += PredOpExecute.subst(sxtahIop)
 349
 350     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 351                             { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
 352                               "predicate_test": predicateTest }, [])
 353     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 354     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 355     exec_output += PredOpExecute.subst(uxtbIop)
 356
 357     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 358                              { "code":
 359                                "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
 360                                "predicate_test": predicateTest }, [])
 361     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 362     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 363     exec_output += PredOpExecute.subst(uxtabIop)
 364
 365     uxtb16Code = '''
 366     uint32_t resTemp = 0;
 367     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 368     replaceBits(resTemp, 31, 16,
 369                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 370     Dest = resTemp;
 371     '''
 372     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 373                               { "code": uxtb16Code,
 374                                 "predicate_test": predicateTest }, [])
 375     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 376     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 377     exec_output += PredOpExecute.subst(uxtb16Iop)
 378
 379     uxtab16Code = '''
 380     uint32_t resTemp = 0;
 381     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 382                                         bits(Op1, 15, 0));
 383     replaceBits(resTemp, 31, 16,
 384                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 385                 bits(Op1, 31, 16));
 386     Dest = resTemp;
 387     '''
 388     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 389                                { "code": uxtab16Code,
 390                                  "predicate_test": predicateTest }, [])
 391     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 392     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 393     exec_output += PredOpExecute.subst(uxtab16Iop)
 394
 395     uxthCode = '''
 396     uint64_t rotated = (uint32_t)Op1;
 397     rotated = (rotated | (rotated << 32)) >> imm;
 398     Dest = (uint16_t)rotated;
 399     '''
 400     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 401                               { "code": uxthCode,
 402                                 "predicate_test": predicateTest }, [])
 403     header_output += RegImmRegOpDeclare.subst(uxthIop)
 404     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 405     exec_output += PredOpExecute.subst(uxthIop)
 406
 407     uxtahCode = '''
 408     uint64_t rotated = (uint32_t)Op2;
 409     rotated = (rotated | (rotated << 32)) >> imm;
 410     Dest = (uint16_t)rotated + Op1;
 411     '''
 412     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 413                              { "code": uxtahCode,
 414                                "predicate_test": predicateTest }, [])
 415     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 416     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 417     exec_output += PredOpExecute.subst(uxtahIop)
 418
 419     selCode = '''
 420         uint32_t resTemp = 0;
 421         for (unsigned i = 0; i < 4; i++) {
 422             int low = i * 8;
 423             int high = low + 7;
 424             replaceBits(resTemp, high, low,
 425                         bits(CondCodes, 16 + i) ?
 426                             bits(Op1, high, low) : bits(Op2, high, low));
 427         }
 428         Dest = resTemp;
 429     '''
 430     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 431                            { "code": selCode,
 432                              "predicate_test": condPredicateTest }, [])
 433     header_output += RegRegRegOpDeclare.subst(selIop)
 434     decoder_output += RegRegRegOpConstructor.subst(selIop)
 435     exec_output += PredOpExecute.subst(selIop)
 436
 437     usad8Code = '''
 438         uint32_t resTemp = 0;
 439         for (unsigned i = 0; i < 4; i++) {
 440             int low = i * 8;
 441             int high = low + 7;
 442             int32_t diff = bits(Op1, high, low) -
 443                            bits(Op2, high, low);
 444             resTemp += ((diff < 0) ? -diff : diff);
 445         }
 446         Dest = resTemp;
 447     '''
 448     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 449                              { "code": usad8Code,
 450                                "predicate_test": predicateTest }, [])
 451     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 452     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 453     exec_output += PredOpExecute.subst(usad8Iop)
 454
 455     usada8Code = '''
 456         uint32_t resTemp = 0;
 457         for (unsigned i = 0; i < 4; i++) {
 458             int low = i * 8;
 459             int high = low + 7;
 460             int32_t diff = bits(Op1, high, low) -
 461                            bits(Op2, high, low);
 462             resTemp += ((diff < 0) ? -diff : diff);
 463         }
 464         Dest = Op3 + resTemp;
 465     '''
 466     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 467                               { "code": usada8Code,
 468                                 "predicate_test": predicateTest }, [])
 469     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 470     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 471     exec_output += PredOpExecute.subst(usada8Iop)
 472
 473     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 474     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 475     header_output += BasicDeclare.subst(bkptIop)
 476     decoder_output += BasicConstructor.subst(bkptIop)
 477     exec_output += BasicExecute.subst(bkptIop)
 478
 479     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 480             { "code" : "", "predicate_test" : predicateTest },
 481             ['IsNop'])
 482     header_output += BasicDeclare.subst(nopIop)
 483     decoder_output += BasicConstructor.subst(nopIop)
 484     exec_output += PredOpExecute.subst(nopIop)
 485
 486     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 487             { "code" : "", "predicate_test" : predicateTest })
 488     header_output += BasicDeclare.subst(yieldIop)
 489     decoder_output += BasicConstructor.subst(yieldIop)
 490     exec_output += PredOpExecute.subst(yieldIop)
 491
 492     wfeCode = '''
 493 #if FULL_SYSTEM
 494     if (SevMailbox) {
 495         SevMailbox = 0;
 496         PseudoInst::quiesceSkip(xc->tcBase());
 497     }
 498     else {
 499         PseudoInst::quiesce(xc->tcBase());
 500     }
 501 #endif
 502     '''
 503     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 504             { "code" : wfeCode, "predicate_test" : predicateTest },
 505             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 506     header_output += BasicDeclare.subst(wfeIop)
 507     decoder_output += BasicConstructor.subst(wfeIop)
 508     exec_output += QuiescePredOpExecute.subst(wfeIop)
 509
 510     wfiCode = '''
 511 #if FULL_SYSTEM
 512     PseudoInst::quiesce(xc->tcBase());
 513 #endif
 514     '''
 515     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 516             { "code" : wfiCode, "predicate_test" : predicateTest },
 517             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 518     header_output += BasicDeclare.subst(wfiIop)
 519     decoder_output += BasicConstructor.subst(wfiIop)
 520     exec_output += QuiescePredOpExecute.subst(wfiIop)
 521
 522     sevCode = '''
 523     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
 524     SevMailbox = 1;
 525     System *sys = xc->tcBase()->getSystemPtr();
 526     for (int x = 0; x < sys->numContexts(); x++) {
 527         ThreadContext *oc = sys->getThreadContext(x);
 528         if (oc != xc->tcBase()) {
 529             oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
 530         }
 531     }
 532     '''
 533     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 534             { "code" : sevCode, "predicate_test" : predicateTest },
 535             ["IsNonSpeculative", "IsSquashAfter"])
 536     header_output += BasicDeclare.subst(sevIop)
 537     decoder_output += BasicConstructor.subst(sevIop)
 538     exec_output += PredOpExecute.subst(sevIop)
 539
 540     itIop = InstObjParams("it", "ItInst", "PredOp", \
 541             { "code" : "Itstate = machInst.newItstate;",
 542               "predicate_test" : predicateTest },
 543             ["IsNonSpeculative", "IsSerializeAfter"])
 544     header_output += BasicDeclare.subst(itIop)
 545     decoder_output += BasicConstructor.subst(itIop)
 546     exec_output += PredOpExecute.subst(itIop)
 547     unknownCode = '''
 548 #if FULL_SYSTEM
 549             return new UndefinedInstruction;
 550 #else
 551             return new UndefinedInstruction(machInst, true);
 552 #endif
 553     '''
 554     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 555                                { "code": unknownCode,
 556                                  "predicate_test": predicateTest })
 557     header_output += BasicDeclare.subst(unknownIop)
 558     decoder_output += BasicConstructor.subst(unknownIop)
 559     exec_output += PredOpExecute.subst(unknownIop)
 560
 561     ubfxCode = '''
 562         Dest = bits(Op1, imm2, imm1);
 563     '''
 564     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 565                             { "code": ubfxCode,
 566                               "predicate_test": predicateTest }, [])
 567     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 568     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 569     exec_output += PredOpExecute.subst(ubfxIop)
 570
 571     sbfxCode = '''
 572         int32_t resTemp = bits(Op1, imm2, imm1);
 573         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 574     '''
 575     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 576                             { "code": sbfxCode,
 577                               "predicate_test": predicateTest }, [])
 578     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 579     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 580     exec_output += PredOpExecute.subst(sbfxIop)
 581
 582     bfcCode = '''
 583         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 584     '''
 585     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 586                            { "code": bfcCode,
 587                              "predicate_test": predicateTest }, [])
 588     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 589     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 590     exec_output += PredOpExecute.subst(bfcIop)
 591
 592     bfiCode = '''
 593         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 594         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 595     '''
 596     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 597                            { "code": bfiCode,
 598                              "predicate_test": predicateTest }, [])
 599     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 600     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 601     exec_output += PredOpExecute.subst(bfiIop)
 602
 603     mrc15code = '''
 604     CPSR cpsr = Cpsr;
 605     if (cpsr.mode == MODE_USER)
 606 #if FULL_SYSTEM
 607         return new UndefinedInstruction;
 608 #else
 609         return new UndefinedInstruction(false, mnemonic);
 610 #endif
 611     Dest = MiscOp1;
 612     '''
 613
 614     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 615                              { "code": mrc15code,
 616                                "predicate_test": predicateTest }, [])
 617     header_output += RegRegOpDeclare.subst(mrc15Iop)
 618     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 619     exec_output += PredOpExecute.subst(mrc15Iop)
 620
 621
 622     mcr15code = '''
 623     CPSR cpsr = Cpsr;
 624     if (cpsr.mode == MODE_USER)
 625 #if FULL_SYSTEM
 626         return new UndefinedInstruction;
 627 #else
 628         return new UndefinedInstruction(false, mnemonic);
 629 #endif
 630     MiscDest = Op1;
 631     '''
 632     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 633                              { "code": mcr15code,
 634                                "predicate_test": predicateTest },
 635                                ["IsSerializeAfter","IsNonSpeculative"])
 636     header_output += RegRegOpDeclare.subst(mcr15Iop)
 637     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 638     exec_output += PredOpExecute.subst(mcr15Iop)
 639
 640     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 641                                  { "code": "Dest = MiscOp1;",
 642                                    "predicate_test": predicateTest }, [])
 643     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 644     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 645     exec_output += PredOpExecute.subst(mrc15UserIop)
 646
 647     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 648                                  { "code": "MiscDest = Op1",
 649                                    "predicate_test": predicateTest },
 650                                    ["IsSerializeAfter","IsNonSpeculative"])
 651     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 652     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 653     exec_output += PredOpExecute.subst(mcr15UserIop)
 654
 655     enterxCode = '''
 656         NextThumb = true;
 657         NextJazelle = true;
 658     '''
 659     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 660                               { "code": enterxCode,
 661                                 "predicate_test": predicateTest }, [])
 662     header_output += BasicDeclare.subst(enterxIop)
 663     decoder_output += BasicConstructor.subst(enterxIop)
 664     exec_output += PredOpExecute.subst(enterxIop)
 665
 666     leavexCode = '''
 667         NextThumb = true;
 668         NextJazelle = false;
 669     '''
 670     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 671                               { "code": leavexCode,
 672                                 "predicate_test": predicateTest }, [])
 673     header_output += BasicDeclare.subst(leavexIop)
 674     decoder_output += BasicConstructor.subst(leavexIop)
 675     exec_output += PredOpExecute.subst(leavexIop)
 676
 677     setendCode = '''
 678         CPSR cpsr = Cpsr;
 679         cpsr.e = imm;
 680         Cpsr = cpsr;
 681     '''
 682     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 683                               { "code": setendCode,
 684                                 "predicate_test": predicateTest },
 685                               ["IsSerializeAfter","IsNonSpeculative"])
 686     header_output += ImmOpDeclare.subst(setendIop)
 687     decoder_output += ImmOpConstructor.subst(setendIop)
 688     exec_output += PredOpExecute.subst(setendIop)
 689
 690     clrexCode = '''
 691         unsigned memAccessFlags = Request::CLEAR_LL |
 692             ArmISA::TLB::AlignWord | Request::LLSC;
 693         fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
 694     '''
 695     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 696                              { "code": clrexCode,
 697                                "predicate_test": predicateTest },[])
 698     header_output += ClrexDeclare.subst(clrexIop)
 699     decoder_output += BasicConstructor.subst(clrexIop)
 700     exec_output += PredOpExecute.subst(clrexIop)
 701     exec_output += ClrexInitiateAcc.subst(clrexIop)
 702     exec_output += ClrexCompleteAcc.subst(clrexIop)
 703
 704     isbCode = '''
 705         fault = new FlushPipe;
 706     '''
 707     isbIop = InstObjParams("isb", "Isb", "PredOp",
 708                              {"code": isbCode,
 709                                "predicate_test": predicateTest},
 710                                 ['IsSerializeAfter'])
 711     header_output += BasicDeclare.subst(isbIop)
 712     decoder_output += BasicConstructor.subst(isbIop)
 713     exec_output += PredOpExecute.subst(isbIop)
 714
 715     dsbCode = '''
 716         fault = new FlushPipe;
 717     '''
 718     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 719                              {"code": dsbCode,
 720                                "predicate_test": predicateTest},
 721                               ['IsMemBarrier', 'IsSerializeAfter'])
 722     header_output += BasicDeclare.subst(dsbIop)
 723     decoder_output += BasicConstructor.subst(dsbIop)
 724     exec_output += PredOpExecute.subst(dsbIop)
 725
 726     dmbCode = '''
 727     '''
 728     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 729                              {"code": dmbCode,
 730                                "predicate_test": predicateTest},
 731                                ['IsMemBarrier'])
 732     header_output += BasicDeclare.subst(dmbIop)
 733     decoder_output += BasicConstructor.subst(dmbIop)
 734     exec_output += PredOpExecute.subst(dmbIop)
 735
 736     dbgCode = '''
 737     '''
 738     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 739                              {"code": dbgCode,
 740                                "predicate_test": predicateTest})
 741     header_output += BasicDeclare.subst(dbgIop)
 742     decoder_output += BasicConstructor.subst(dbgIop)
 743     exec_output += PredOpExecute.subst(dbgIop)
 744
 745     cpsCode = '''
 746     uint32_t mode = bits(imm, 4, 0);
 747     uint32_t f = bits(imm, 5);
 748     uint32_t i = bits(imm, 6);
 749     uint32_t a = bits(imm, 7);
 750     bool setMode = bits(imm, 8);
 751     bool enable = bits(imm, 9);
 752     CPSR cpsr = Cpsr;
 753     SCTLR sctlr = Sctlr;
 754     if (cpsr.mode != MODE_USER) {
 755         if (enable) {
 756             if (f) cpsr.f = 0;
 757             if (i) cpsr.i = 0;
 758             if (a) cpsr.a = 0;
 759         } else {
 760             if (f && !sctlr.nmfi) cpsr.f = 1;
 761             if (i) cpsr.i = 1;
 762             if (a) cpsr.a = 1;
 763         }
 764         if (setMode) {
 765             cpsr.mode = mode;
 766         }
 767     }
 768     Cpsr = cpsr;
 769     '''
 770     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 771                            { "code": cpsCode,
 772                              "predicate_test": predicateTest },
 773                            ["IsSerializeAfter","IsNonSpeculative"])
 774     header_output += ImmOpDeclare.subst(cpsIop)
 775     decoder_output += ImmOpConstructor.subst(cpsIop)
 776     exec_output += PredOpExecute.subst(cpsIop)
 777 }};