3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Redistribution and use in source and binary forms, with or without
16 // modification, are permitted provided that the following conditions are
17 // met: redistributions of source code must retain the above copyright
18 // notice, this list of conditions and the following disclaimer;
19 // redistributions in binary form must reproduce the above copyright
20 // notice, this list of conditions and the following disclaimer in the
21 // documentation and/or other materials provided with the distribution;
22 // neither the name of the copyright holders nor the names of its
23 // contributors may be used to endorse or promote products derived from
24 // this software without specific prior written permission.
26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 // Authors: Gabe Black
44 fault = new SupervisorCall;
46 fault = new SupervisorCall(machInst);
50 svcIop = InstObjParams("svc", "Svc", "PredOp",
52 "predicate_test": predicateTest }, ["IsSyscall"])
53 header_output = BasicDeclare.subst(svcIop)
54 decoder_output = BasicConstructor.subst(svcIop)
55 exec_output = PredOpExecute.subst(svcIop)
61 header_output = decoder_output = exec_output = ""
63 mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
64 mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
65 { "code": mrsCpsrCode,
66 "predicate_test": predicateTest }, [])
67 header_output += MrsDeclare.subst(mrsCpsrIop)
68 decoder_output += MrsConstructor.subst(mrsCpsrIop)
69 exec_output += PredOpExecute.subst(mrsCpsrIop)
71 mrsSpsrCode = "Dest = Spsr"
72 mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
73 { "code": mrsSpsrCode,
74 "predicate_test": predicateTest }, [])
75 header_output += MrsDeclare.subst(mrsSpsrIop)
76 decoder_output += MrsConstructor.subst(mrsSpsrIop)
77 exec_output += PredOpExecute.subst(mrsSpsrIop)
82 cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
83 Cpsr = ~CondCodesMask & newCpsr;
84 CondCodes = CondCodesMask & newCpsr;
86 msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
87 { "code": msrCpsrRegCode,
88 "predicate_test": predicateTest }, [])
89 header_output += MsrRegDeclare.subst(msrCpsrRegIop)
90 decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
91 exec_output += PredOpExecute.subst(msrCpsrRegIop)
93 msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
94 msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
95 { "code": msrSpsrRegCode,
96 "predicate_test": predicateTest }, [])
97 header_output += MsrRegDeclare.subst(msrSpsrRegIop)
98 decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
99 exec_output += PredOpExecute.subst(msrSpsrRegIop)
104 cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
105 Cpsr = ~CondCodesMask & newCpsr;
106 CondCodes = CondCodesMask & newCpsr;
108 msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
109 { "code": msrCpsrImmCode,
110 "predicate_test": predicateTest }, [])
111 header_output += MsrImmDeclare.subst(msrCpsrImmIop)
112 decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
113 exec_output += PredOpExecute.subst(msrCpsrImmIop)
115 msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
116 msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
117 { "code": msrSpsrImmCode,
118 "predicate_test": predicateTest }, [])
119 header_output += MsrImmDeclare.subst(msrSpsrImmIop)
120 decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
121 exec_output += PredOpExecute.subst(msrSpsrImmIop)
125 Dest = swap_byte(val);
127 revIop = InstObjParams("rev", "Rev", "RegRegOp",
129 "predicate_test": predicateTest }, [])
130 header_output += RegRegOpDeclare.subst(revIop)
131 decoder_output += RegRegOpConstructor.subst(revIop)
132 exec_output += PredOpExecute.subst(revIop)
136 Dest = (bits(val, 15, 8) << 0) |
137 (bits(val, 7, 0) << 8) |
138 (bits(val, 31, 24) << 16) |
139 (bits(val, 23, 16) << 24);
141 rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
143 "predicate_test": predicateTest }, [])
144 header_output += RegRegOpDeclare.subst(rev16Iop)
145 decoder_output += RegRegOpConstructor.subst(rev16Iop)
146 exec_output += PredOpExecute.subst(rev16Iop)
150 Dest = sext<16>(swap_byte(val));
152 revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
154 "predicate_test": predicateTest }, [])
155 header_output += RegRegOpDeclare.subst(revshIop)
156 decoder_output += RegRegOpConstructor.subst(revshIop)
157 exec_output += PredOpExecute.subst(revshIop)
160 uint8_t *opBytes = (uint8_t *)&Op1;
162 uint8_t *destBytes = (uint8_t *)&resTemp;
163 // This reverses the bytes and bits of the input, or so says the
165 for (int i = 0; i < 4; i++) {
166 uint32_t temp = opBytes[i];
167 temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
168 destBytes[3 - i] = (temp * 0x10101) >> 16;
172 rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
174 "predicate_test": predicateTest }, [])
175 header_output += RegRegOpDeclare.subst(rbitIop)
176 decoder_output += RegRegOpConstructor.subst(rbitIop)
177 exec_output += PredOpExecute.subst(rbitIop)
180 Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
182 clzIop = InstObjParams("clz", "Clz", "RegRegOp",
184 "predicate_test": predicateTest }, [])
185 header_output += RegRegOpDeclare.subst(clzIop)
186 decoder_output += RegRegOpConstructor.subst(clzIop)
187 exec_output += PredOpExecute.subst(clzIop)
190 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
192 if (satInt(res, operand, imm))
193 CondCodes = CondCodes | (1 << 27);
195 CondCodes = CondCodes;
198 ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
200 "predicate_test": predicateTest }, [])
201 header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
202 decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
203 exec_output += PredOpExecute.subst(ssatIop)
206 int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
208 if (uSatInt(res, operand, imm))
209 CondCodes = CondCodes | (1 << 27);
211 CondCodes = CondCodes;
214 usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
216 "predicate_test": predicateTest }, [])
217 header_output += RegImmRegShiftOpDeclare.subst(usatIop)
218 decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
219 exec_output += PredOpExecute.subst(usatIop)
223 uint32_t resTemp = 0;
224 CondCodes = CondCodes;
225 int32_t argLow = sext<16>(bits(Op1, 15, 0));
226 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
227 if (satInt(res, argLow, imm))
228 CondCodes = CondCodes | (1 << 27);
229 replaceBits(resTemp, 15, 0, res);
230 if (satInt(res, argHigh, imm))
231 CondCodes = CondCodes | (1 << 27);
232 replaceBits(resTemp, 31, 16, res);
235 ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
236 { "code": ssat16Code,
237 "predicate_test": predicateTest }, [])
238 header_output += RegImmRegOpDeclare.subst(ssat16Iop)
239 decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
240 exec_output += PredOpExecute.subst(ssat16Iop)
244 uint32_t resTemp = 0;
245 CondCodes = CondCodes;
246 int32_t argLow = sext<16>(bits(Op1, 15, 0));
247 int32_t argHigh = sext<16>(bits(Op1, 31, 16));
248 if (uSatInt(res, argLow, imm))
249 CondCodes = CondCodes | (1 << 27);
250 replaceBits(resTemp, 15, 0, res);
251 if (uSatInt(res, argHigh, imm))
252 CondCodes = CondCodes | (1 << 27);
253 replaceBits(resTemp, 31, 16, res);
256 usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
257 { "code": usat16Code,
258 "predicate_test": predicateTest }, [])
259 header_output += RegImmRegOpDeclare.subst(usat16Iop)
260 decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
261 exec_output += PredOpExecute.subst(usat16Iop)
263 sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
265 "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
266 "predicate_test": predicateTest }, [])
267 header_output += RegImmRegOpDeclare.subst(sxtbIop)
268 decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
269 exec_output += PredOpExecute.subst(sxtbIop)
271 sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
274 Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
277 "predicate_test": predicateTest }, [])
278 header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
279 decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
280 exec_output += PredOpExecute.subst(sxtabIop)
283 uint32_t resTemp = 0;
284 replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
285 replaceBits(resTemp, 31, 16,
286 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
289 sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
290 { "code": sxtb16Code,
291 "predicate_test": predicateTest }, [])
292 header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
293 decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
294 exec_output += PredOpExecute.subst(sxtb16Iop)
297 uint32_t resTemp = 0;
298 replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
300 replaceBits(resTemp, 31, 16,
301 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
305 sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
306 { "code": sxtab16Code,
307 "predicate_test": predicateTest }, [])
308 header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
309 decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
310 exec_output += PredOpExecute.subst(sxtab16Iop)
313 uint64_t rotated = (uint32_t)Op1;
314 rotated = (rotated | (rotated << 32)) >> imm;
315 Dest = sext<16>((uint16_t)rotated);
317 sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
319 "predicate_test": predicateTest }, [])
320 header_output += RegImmRegOpDeclare.subst(sxthIop)
321 decoder_output += RegImmRegOpConstructor.subst(sxthIop)
322 exec_output += PredOpExecute.subst(sxthIop)
325 uint64_t rotated = (uint32_t)Op2;
326 rotated = (rotated | (rotated << 32)) >> imm;
327 Dest = sext<16>((uint16_t)rotated) + Op1;
329 sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
331 "predicate_test": predicateTest }, [])
332 header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
333 decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
334 exec_output += PredOpExecute.subst(sxtahIop)
336 uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
337 { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
338 "predicate_test": predicateTest }, [])
339 header_output += RegImmRegOpDeclare.subst(uxtbIop)
340 decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
341 exec_output += PredOpExecute.subst(uxtbIop)
343 uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
345 "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
346 "predicate_test": predicateTest }, [])
347 header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
348 decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
349 exec_output += PredOpExecute.subst(uxtabIop)
352 uint32_t resTemp = 0;
353 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
354 replaceBits(resTemp, 31, 16,
355 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
358 uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
359 { "code": uxtb16Code,
360 "predicate_test": predicateTest }, [])
361 header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
362 decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
363 exec_output += PredOpExecute.subst(uxtb16Iop)
366 uint32_t resTemp = 0;
367 replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
369 replaceBits(resTemp, 31, 16,
370 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
374 uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
375 { "code": uxtab16Code,
376 "predicate_test": predicateTest }, [])
377 header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
378 decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
379 exec_output += PredOpExecute.subst(uxtab16Iop)
382 uint64_t rotated = (uint32_t)Op1;
383 rotated = (rotated | (rotated << 32)) >> imm;
384 Dest = (uint16_t)rotated;
386 uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
388 "predicate_test": predicateTest }, [])
389 header_output += RegImmRegOpDeclare.subst(uxthIop)
390 decoder_output += RegImmRegOpConstructor.subst(uxthIop)
391 exec_output += PredOpExecute.subst(uxthIop)
394 uint64_t rotated = (uint32_t)Op2;
395 rotated = (rotated | (rotated << 32)) >> imm;
396 Dest = (uint16_t)rotated + Op1;
398 uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
400 "predicate_test": predicateTest }, [])
401 header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
402 decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
403 exec_output += PredOpExecute.subst(uxtahIop)
406 uint32_t resTemp = 0;
407 for (unsigned i = 0; i < 4; i++) {
410 replaceBits(resTemp, high, low,
411 bits(CondCodes, 16 + i) ?
412 bits(Op1, high, low) : bits(Op2, high, low));
416 selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
418 "predicate_test": predicateTest }, [])
419 header_output += RegRegRegOpDeclare.subst(selIop)
420 decoder_output += RegRegRegOpConstructor.subst(selIop)
421 exec_output += PredOpExecute.subst(selIop)
424 uint32_t resTemp = 0;
425 for (unsigned i = 0; i < 4; i++) {
428 int32_t diff = bits(Op1, high, low) -
429 bits(Op2, high, low);
430 resTemp += ((diff < 0) ? -diff : diff);
434 usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
436 "predicate_test": predicateTest }, [])
437 header_output += RegRegRegOpDeclare.subst(usad8Iop)
438 decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
439 exec_output += PredOpExecute.subst(usad8Iop)
442 uint32_t resTemp = 0;
443 for (unsigned i = 0; i < 4; i++) {
446 int32_t diff = bits(Op1, high, low) -
447 bits(Op2, high, low);
448 resTemp += ((diff < 0) ? -diff : diff);
450 Dest = Op3 + resTemp;
452 usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
453 { "code": usada8Code,
454 "predicate_test": predicateTest }, [])
455 header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
456 decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
457 exec_output += PredOpExecute.subst(usada8Iop)
459 bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
460 "return new PrefetchAbort(PC, ArmFault::DebugEvent);")
461 header_output += BasicDeclare.subst(bkptIop)
462 decoder_output += BasicConstructor.subst(bkptIop)
463 exec_output += BasicExecute.subst(bkptIop)
465 nopIop = InstObjParams("nop", "NopInst", "PredOp", \
466 { "code" : "", "predicate_test" : predicateTest })
467 header_output += BasicDeclare.subst(nopIop)
468 decoder_output += BasicConstructor.subst(nopIop)
469 exec_output += PredOpExecute.subst(nopIop)
471 itIop = InstObjParams("it", "ItInst", "PredOp", \
472 { "code" : "Itstate = machInst.newItstate;",
473 "predicate_test" : predicateTest })
474 header_output += BasicDeclare.subst(itIop)
475 decoder_output += BasicConstructor.subst(itIop)
476 exec_output += PredOpExecute.subst(itIop)
479 return new UndefinedInstruction;
481 return new UndefinedInstruction(machInst, true);
484 unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
485 { "code": unknownCode,
486 "predicate_test": predicateTest })
487 header_output += BasicDeclare.subst(unknownIop)
488 decoder_output += BasicConstructor.subst(unknownIop)
489 exec_output += PredOpExecute.subst(unknownIop)
492 Dest = bits(Op1, imm2, imm1);
494 ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
496 "predicate_test": predicateTest }, [])
497 header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
498 decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
499 exec_output += PredOpExecute.subst(ubfxIop)
502 int32_t resTemp = bits(Op1, imm2, imm1);
503 Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
505 sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
507 "predicate_test": predicateTest }, [])
508 header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
509 decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
510 exec_output += PredOpExecute.subst(sbfxIop)
513 Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
515 bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
517 "predicate_test": predicateTest }, [])
518 header_output += RegRegImmImmOpDeclare.subst(bfcIop)
519 decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
520 exec_output += PredOpExecute.subst(bfcIop)
523 uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
524 Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
526 bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
528 "predicate_test": predicateTest }, [])
529 header_output += RegRegImmImmOpDeclare.subst(bfiIop)
530 decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
531 exec_output += PredOpExecute.subst(bfiIop)
535 if (cpsr.mode == MODE_USER)
537 return new UndefinedInstruction;
539 return new UndefinedInstruction(false, mnemonic);
544 mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
546 "predicate_test": predicateTest }, [])
547 header_output += RegRegOpDeclare.subst(mrc15Iop)
548 decoder_output += RegRegOpConstructor.subst(mrc15Iop)
549 exec_output += PredOpExecute.subst(mrc15Iop)
554 if (cpsr.mode == MODE_USER)
556 return new UndefinedInstruction;
558 return new UndefinedInstruction(false, mnemonic);
562 mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
564 "predicate_test": predicateTest }, [])
565 header_output += RegRegOpDeclare.subst(mcr15Iop)
566 decoder_output += RegRegOpConstructor.subst(mcr15Iop)
567 exec_output += PredOpExecute.subst(mcr15Iop)
570 FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
572 enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
573 { "code": enterxCode,
574 "predicate_test": predicateTest }, [])
575 header_output += BasicDeclare.subst(enterxIop)
576 decoder_output += BasicConstructor.subst(enterxIop)
577 exec_output += PredOpExecute.subst(enterxIop)
580 FNPC = (NPC & ~(1ULL << PcJBitShift)) | (1ULL << PcTBitShift);
582 leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
583 { "code": leavexCode,
584 "predicate_test": predicateTest }, [])
585 header_output += BasicDeclare.subst(leavexIop)
586 decoder_output += BasicConstructor.subst(leavexIop)
587 exec_output += PredOpExecute.subst(leavexIop)
594 setendIop = InstObjParams("setend", "Setend", "ImmOp",
595 { "code": setendCode,
596 "predicate_test": predicateTest }, [])
597 header_output += ImmOpDeclare.subst(setendIop)
598 decoder_output += ImmOpConstructor.subst(setendIop)
599 exec_output += PredOpExecute.subst(setendIop)
602 uint32_t mode = bits(imm, 4, 0);
603 uint32_t f = bits(imm, 5);
604 uint32_t i = bits(imm, 6);
605 uint32_t a = bits(imm, 7);
606 bool setMode = bits(imm, 8);
607 bool enable = bits(imm, 9);
610 if (cpsr.mode != MODE_USER) {
616 if (f && !sctlr.nmfi) cpsr.f = 1;
626 cpsIop = InstObjParams("cps", "Cps", "ImmOp",
628 "predicate_test": predicateTest }, [])
629 header_output += ImmOpDeclare.subst(cpsIop)
630 decoder_output += ImmOpConstructor.subst(cpsIop)
631 exec_output += PredOpExecute.subst(cpsIop)