src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
  64     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  65                                { "code": mrsCpsrCode,
  66                                  "predicate_test": predicateTest }, [])
  67     header_output += MrsDeclare.subst(mrsCpsrIop)
  68     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  69     exec_output += PredOpExecute.subst(mrsCpsrIop)
  70
  71     mrsSpsrCode = "Dest = Spsr"
  72     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  73                                { "code": mrsSpsrCode,
  74                                  "predicate_test": predicateTest }, [])
  75     header_output += MrsDeclare.subst(mrsSpsrIop)
  76     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  77     exec_output += PredOpExecute.subst(mrsSpsrIop)
  78
  79     msrCpsrRegCode = '''
  80         uint32_t newCpsr =
  81             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false);
  82         Cpsr = ~CondCodesMask & newCpsr;
  83         CondCodes = CondCodesMask & newCpsr;
  84     '''
  85     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
  86                                   { "code": msrCpsrRegCode,
  87                                     "predicate_test": predicateTest }, [])
  88     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
  89     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
  90     exec_output += PredOpExecute.subst(msrCpsrRegIop)
  91
  92     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
  93     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
  94                                   { "code": msrSpsrRegCode,
  95                                     "predicate_test": predicateTest }, [])
  96     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
  97     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
  98     exec_output += PredOpExecute.subst(msrSpsrRegIop)
  99
 100     msrCpsrImmCode = '''
 101         uint32_t newCpsr =
 102             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false);
 103         Cpsr = ~CondCodesMask & newCpsr;
 104         CondCodes = CondCodesMask & newCpsr;
 105     '''
 106     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 107                                   { "code": msrCpsrImmCode,
 108                                     "predicate_test": predicateTest }, [])
 109     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 110     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 111     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 112
 113     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 114     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 115                                   { "code": msrSpsrImmCode,
 116                                     "predicate_test": predicateTest }, [])
 117     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 118     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 119     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 120
 121     revCode = '''
 122     uint32_t val = Op1;
 123     Dest = swap_byte(val);
 124     '''
 125     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 126                            { "code": revCode,
 127                              "predicate_test": predicateTest }, [])
 128     header_output += RegRegOpDeclare.subst(revIop)
 129     decoder_output += RegRegOpConstructor.subst(revIop)
 130     exec_output += PredOpExecute.subst(revIop)
 131
 132     rev16Code = '''
 133     uint32_t val = Op1;
 134     Dest = (bits(val, 15, 8) << 0) |
 135            (bits(val, 7, 0) << 8) |
 136            (bits(val, 31, 24) << 16) |
 137            (bits(val, 23, 16) << 24);
 138     '''
 139     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 140                              { "code": rev16Code,
 141                                "predicate_test": predicateTest }, [])
 142     header_output += RegRegOpDeclare.subst(rev16Iop)
 143     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 144     exec_output += PredOpExecute.subst(rev16Iop)
 145
 146     revshCode = '''
 147     uint16_t val = Op1;
 148     Dest = sext<16>(swap_byte(val));
 149     '''
 150     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 151                              { "code": revshCode,
 152                                "predicate_test": predicateTest }, [])
 153     header_output += RegRegOpDeclare.subst(revshIop)
 154     decoder_output += RegRegOpConstructor.subst(revshIop)
 155     exec_output += PredOpExecute.subst(revshIop)
 156
 157     rbitCode = '''
 158     uint8_t *opBytes = (uint8_t *)&Op1;
 159     uint32_t resTemp;
 160     uint8_t *destBytes = (uint8_t *)&resTemp;
 161     // This reverses the bytes and bits of the input, or so says the
 162     // internet.
 163     for (int i = 0; i < 4; i++) {
 164         uint32_t temp = opBytes[i];
 165         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 166         destBytes[3 - i] = (temp * 0x10101) >> 16;
 167     }
 168     Dest = resTemp;
 169     '''
 170     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 171                             { "code": rbitCode,
 172                               "predicate_test": predicateTest }, [])
 173     header_output += RegRegOpDeclare.subst(rbitIop)
 174     decoder_output += RegRegOpConstructor.subst(rbitIop)
 175     exec_output += PredOpExecute.subst(rbitIop)
 176
 177     clzCode = '''
 178         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 179     '''
 180     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 181                            { "code": clzCode,
 182                              "predicate_test": predicateTest }, [])
 183     header_output += RegRegOpDeclare.subst(clzIop)
 184     decoder_output += RegRegOpConstructor.subst(clzIop)
 185     exec_output += PredOpExecute.subst(clzIop)
 186
 187     ssatCode = '''
 188         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 189         int32_t res;
 190         if (satInt(res, operand, imm))
 191             CondCodes = CondCodes | (1 << 27);
 192         else
 193             CondCodes = CondCodes;
 194         Dest = res;
 195     '''
 196     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 197                             { "code": ssatCode,
 198                               "predicate_test": predicateTest }, [])
 199     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 200     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 201     exec_output += PredOpExecute.subst(ssatIop)
 202
 203     usatCode = '''
 204         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 205         int32_t res;
 206         if (uSatInt(res, operand, imm))
 207             CondCodes = CondCodes | (1 << 27);
 208         else
 209             CondCodes = CondCodes;
 210         Dest = res;
 211     '''
 212     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 213                             { "code": usatCode,
 214                               "predicate_test": predicateTest }, [])
 215     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 216     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 217     exec_output += PredOpExecute.subst(usatIop)
 218
 219     ssat16Code = '''
 220         int32_t res;
 221         uint32_t resTemp = 0;
 222         CondCodes = CondCodes;
 223         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 224         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 225         if (satInt(res, argLow, imm))
 226             CondCodes = CondCodes | (1 << 27);
 227         replaceBits(resTemp, 15, 0, res);
 228         if (satInt(res, argHigh, imm))
 229             CondCodes = CondCodes | (1 << 27);
 230         replaceBits(resTemp, 31, 16, res);
 231         Dest = resTemp;
 232     '''
 233     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 234                               { "code": ssat16Code,
 235                                 "predicate_test": predicateTest }, [])
 236     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 237     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 238     exec_output += PredOpExecute.subst(ssat16Iop)
 239
 240     usat16Code = '''
 241         int32_t res;
 242         uint32_t resTemp = 0;
 243         CondCodes = CondCodes;
 244         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 245         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 246         if (uSatInt(res, argLow, imm))
 247             CondCodes = CondCodes | (1 << 27);
 248         replaceBits(resTemp, 15, 0, res);
 249         if (uSatInt(res, argHigh, imm))
 250             CondCodes = CondCodes | (1 << 27);
 251         replaceBits(resTemp, 31, 16, res);
 252         Dest = resTemp;
 253     '''
 254     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 255                               { "code": usat16Code,
 256                                 "predicate_test": predicateTest }, [])
 257     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 258     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 259     exec_output += PredOpExecute.subst(usat16Iop)
 260
 261     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 262                             { "code":
 263                               "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
 264                               "predicate_test": predicateTest }, [])
 265     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 266     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 267     exec_output += PredOpExecute.subst(sxtbIop)
 268
 269     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 270                              { "code":
 271                                '''
 272                                    Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
 273                                           Op1;
 274                                ''',
 275                                "predicate_test": predicateTest }, [])
 276     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 277     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 278     exec_output += PredOpExecute.subst(sxtabIop)
 279
 280     sxtb16Code = '''
 281     uint32_t resTemp = 0;
 282     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 283     replaceBits(resTemp, 31, 16,
 284                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 285     Dest = resTemp;
 286     '''
 287     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 288                               { "code": sxtb16Code,
 289                                 "predicate_test": predicateTest }, [])
 290     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 291     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 292     exec_output += PredOpExecute.subst(sxtb16Iop)
 293
 294     sxtab16Code = '''
 295     uint32_t resTemp = 0;
 296     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 297                                         bits(Op1, 15, 0));
 298     replaceBits(resTemp, 31, 16,
 299                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 300                 bits(Op1, 31, 16));
 301     Dest = resTemp;
 302     '''
 303     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 304                                { "code": sxtab16Code,
 305                                  "predicate_test": predicateTest }, [])
 306     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 307     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 308     exec_output += PredOpExecute.subst(sxtab16Iop)
 309
 310     sxthCode = '''
 311     uint64_t rotated = (uint32_t)Op1;
 312     rotated = (rotated | (rotated << 32)) >> imm;
 313     Dest = sext<16>((uint16_t)rotated);
 314     '''
 315     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 316                               { "code": sxthCode,
 317                                 "predicate_test": predicateTest }, [])
 318     header_output += RegImmRegOpDeclare.subst(sxthIop)
 319     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 320     exec_output += PredOpExecute.subst(sxthIop)
 321
 322     sxtahCode = '''
 323     uint64_t rotated = (uint32_t)Op2;
 324     rotated = (rotated | (rotated << 32)) >> imm;
 325     Dest = sext<16>((uint16_t)rotated) + Op1;
 326     '''
 327     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 328                              { "code": sxtahCode,
 329                                "predicate_test": predicateTest }, [])
 330     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 331     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 332     exec_output += PredOpExecute.subst(sxtahIop)
 333
 334     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 335                             { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
 336                               "predicate_test": predicateTest }, [])
 337     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 338     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 339     exec_output += PredOpExecute.subst(uxtbIop)
 340
 341     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 342                              { "code":
 343                                "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
 344                                "predicate_test": predicateTest }, [])
 345     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 346     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 347     exec_output += PredOpExecute.subst(uxtabIop)
 348
 349     uxtb16Code = '''
 350     uint32_t resTemp = 0;
 351     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 352     replaceBits(resTemp, 31, 16,
 353                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 354     Dest = resTemp;
 355     '''
 356     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 357                               { "code": uxtb16Code,
 358                                 "predicate_test": predicateTest }, [])
 359     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 360     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 361     exec_output += PredOpExecute.subst(uxtb16Iop)
 362
 363     uxtab16Code = '''
 364     uint32_t resTemp = 0;
 365     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 366                                         bits(Op1, 15, 0));
 367     replaceBits(resTemp, 31, 16,
 368                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 369                 bits(Op1, 31, 16));
 370     Dest = resTemp;
 371     '''
 372     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 373                                { "code": uxtab16Code,
 374                                  "predicate_test": predicateTest }, [])
 375     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 376     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 377     exec_output += PredOpExecute.subst(uxtab16Iop)
 378
 379     uxthCode = '''
 380     uint64_t rotated = (uint32_t)Op1;
 381     rotated = (rotated | (rotated << 32)) >> imm;
 382     Dest = (uint16_t)rotated;
 383     '''
 384     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 385                               { "code": uxthCode,
 386                                 "predicate_test": predicateTest }, [])
 387     header_output += RegImmRegOpDeclare.subst(uxthIop)
 388     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 389     exec_output += PredOpExecute.subst(uxthIop)
 390
 391     uxtahCode = '''
 392     uint64_t rotated = (uint32_t)Op2;
 393     rotated = (rotated | (rotated << 32)) >> imm;
 394     Dest = (uint16_t)rotated + Op1;
 395     '''
 396     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 397                              { "code": uxtahCode,
 398                                "predicate_test": predicateTest }, [])
 399     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 400     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 401     exec_output += PredOpExecute.subst(uxtahIop)
 402
 403     selCode = '''
 404         uint32_t resTemp = 0;
 405         for (unsigned i = 0; i < 4; i++) {
 406             int low = i * 8;
 407             int high = low + 7;
 408             replaceBits(resTemp, high, low,
 409                         bits(CondCodes, 16 + i) ?
 410                             bits(Op1, high, low) : bits(Op2, high, low));
 411         }
 412         Dest = resTemp;
 413     '''
 414     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 415                            { "code": selCode,
 416                              "predicate_test": predicateTest }, [])
 417     header_output += RegRegRegOpDeclare.subst(selIop)
 418     decoder_output += RegRegRegOpConstructor.subst(selIop)
 419     exec_output += PredOpExecute.subst(selIop)
 420
 421     usad8Code = '''
 422         uint32_t resTemp = 0;
 423         for (unsigned i = 0; i < 4; i++) {
 424             int low = i * 8;
 425             int high = low + 7;
 426             int32_t diff = bits(Op1, high, low) -
 427                            bits(Op2, high, low);
 428             resTemp += ((diff < 0) ? -diff : diff);
 429         }
 430         Dest = resTemp;
 431     '''
 432     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 433                              { "code": usad8Code,
 434                                "predicate_test": predicateTest }, [])
 435     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 436     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 437     exec_output += PredOpExecute.subst(usad8Iop)
 438
 439     usada8Code = '''
 440         uint32_t resTemp = 0;
 441         for (unsigned i = 0; i < 4; i++) {
 442             int low = i * 8;
 443             int high = low + 7;
 444             int32_t diff = bits(Op1, high, low) -
 445                            bits(Op2, high, low);
 446             resTemp += ((diff < 0) ? -diff : diff);
 447         }
 448         Dest = Op3 + resTemp;
 449     '''
 450     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 451                               { "code": usada8Code,
 452                                 "predicate_test": predicateTest }, [])
 453     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 454     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 455     exec_output += PredOpExecute.subst(usada8Iop)
 456
 457     nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", [])
 458     header_output += BasicDeclare.subst(nopIop)
 459     decoder_output += BasicConstructor.subst(nopIop)
 460     exec_output += BasicExecute.subst(nopIop)
 461
 462     ubfxCode = '''
 463         Dest = bits(Op1, imm2, imm1);
 464     '''
 465     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 466                             { "code": ubfxCode,
 467                               "predicate_test": predicateTest }, [])
 468     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 469     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 470     exec_output += PredOpExecute.subst(ubfxIop)
 471
 472     sbfxCode = '''
 473         int32_t resTemp = bits(Op1, imm2, imm1);
 474         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 475     '''
 476     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 477                             { "code": sbfxCode,
 478                               "predicate_test": predicateTest }, [])
 479     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 480     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 481     exec_output += PredOpExecute.subst(sbfxIop)
 482
 483     bfcCode = '''
 484         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 485     '''
 486     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 487                            { "code": bfcCode,
 488                              "predicate_test": predicateTest }, [])
 489     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 490     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 491     exec_output += PredOpExecute.subst(bfcIop)
 492
 493     bfiCode = '''
 494         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 495         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 496     '''
 497     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 498                            { "code": bfiCode,
 499                              "predicate_test": predicateTest }, [])
 500     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 501     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 502     exec_output += PredOpExecute.subst(bfiIop)
 503
 504     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 505                              { "code": "Dest = MiscOp1;",
 506                                "predicate_test": predicateTest }, [])
 507     header_output += RegRegOpDeclare.subst(mrc15Iop)
 508     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 509     exec_output += PredOpExecute.subst(mrc15Iop)
 510
 511     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 512                              { "code": "MiscDest = Op1;",
 513                                "predicate_test": predicateTest }, [])
 514     header_output += RegRegOpDeclare.subst(mcr15Iop)
 515     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 516     exec_output += PredOpExecute.subst(mcr15Iop)
 517
 518     enterxCode = '''
 519         FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
 520     '''
 521     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 522                               { "code": enterxCode,
 523                                 "predicate_test": predicateTest }, [])
 524     header_output += BasicDeclare.subst(enterxIop)
 525     decoder_output += BasicConstructor.subst(enterxIop)
 526     exec_output += PredOpExecute.subst(enterxIop)
 527
 528     leavexCode = '''
 529         FNPC = (NPC & ~(1ULL << PcJBitShift)) | (1ULL << PcTBitShift);
 530     '''
 531     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 532                               { "code": leavexCode,
 533                                 "predicate_test": predicateTest }, [])
 534     header_output += BasicDeclare.subst(leavexIop)
 535     decoder_output += BasicConstructor.subst(leavexIop)
 536     exec_output += PredOpExecute.subst(leavexIop)
 537
 538     setendCode = '''
 539         CPSR cpsr = Cpsr;
 540         cpsr.e = imm;
 541         Cpsr = cpsr;
 542     '''
 543     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 544                               { "code": setendCode,
 545                                 "predicate_test": predicateTest }, [])
 546     header_output += ImmOpDeclare.subst(setendIop)
 547     decoder_output += ImmOpConstructor.subst(setendIop)
 548     exec_output += PredOpExecute.subst(setendIop)
 549
 550     cpsCode = '''
 551     uint32_t mode = bits(imm, 4, 0);
 552     uint32_t f = bits(imm, 5);
 553     uint32_t i = bits(imm, 6);
 554     uint32_t a = bits(imm, 7);
 555     bool setMode = bits(imm, 8);
 556     bool enable = bits(imm, 9);
 557     CPSR cpsr = Cpsr;
 558     if (cpsr.mode != MODE_USER) {
 559         if (enable) {
 560             if (f) cpsr.f = 0;
 561             if (i) cpsr.i = 0;
 562             if (a) cpsr.a = 0;
 563         } else {
 564             if (f) cpsr.f = 1;
 565             if (i) cpsr.i = 1;
 566             if (a) cpsr.a = 1;
 567         }
 568         if (setMode) {
 569             cpsr.mode = mode;
 570         }
 571     }
 572     Cpsr = cpsr;
 573     '''
 574     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 575                            { "code": cpsCode,
 576                              "predicate_test": predicateTest }, [])
 577     header_output += ImmOpDeclare.subst(cpsIop)
 578     decoder_output += ImmOpConstructor.subst(cpsIop)
 579     exec_output += PredOpExecute.subst(cpsIop)
 580 }};