src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = '''
  64         CPSR cpsr = Cpsr;
  65         cpsr.nz = CondCodesNZ;
  66         cpsr.c = CondCodesC;
  67         cpsr.v = CondCodesV;
  68         cpsr.ge = CondCodesGE;
  69         Dest = cpsr & 0xF8FF03DF
  70     '''
  71
  72     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  73                                { "code": mrsCpsrCode,
  74                                  "predicate_test": condPredicateTest },
  75                                ["IsSerializeBefore"])
  76     header_output += MrsDeclare.subst(mrsCpsrIop)
  77     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  78     exec_output += PredOpExecute.subst(mrsCpsrIop)
  79
  80     mrsSpsrCode = "Dest = Spsr"
  81     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  82                                { "code": mrsSpsrCode,
  83                                  "predicate_test": predicateTest },
  84                                ["IsSerializeBefore"])
  85     header_output += MrsDeclare.subst(mrsSpsrIop)
  86     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  87     exec_output += PredOpExecute.subst(mrsSpsrIop)
  88
  89     msrCpsrRegCode = '''
  90         SCTLR sctlr = Sctlr;
  91         CPSR old_cpsr = Cpsr;
  92         old_cpsr.nz = CondCodesNZ;
  93         old_cpsr.c = CondCodesC;
  94         old_cpsr.v = CondCodesV;
  95         old_cpsr.ge = CondCodesGE;
  96
  97         CPSR new_cpsr =
  98             cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
  99         Cpsr = ~CondCodesMask & new_cpsr;
 100         CondCodesNZ = new_cpsr.nz;
 101         CondCodesC = new_cpsr.c;
 102         CondCodesV = new_cpsr.v;
 103         CondCodesGE = new_cpsr.ge;
 104     '''
 105     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
 106                                   { "code": msrCpsrRegCode,
 107                                     "predicate_test": condPredicateTest },
 108                                   ["IsSerializeAfter","IsNonSpeculative"])
 109     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
 110     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
 111     exec_output += PredOpExecute.subst(msrCpsrRegIop)
 112
 113     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
 114     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 115                                   { "code": msrSpsrRegCode,
 116                                     "predicate_test": predicateTest },
 117                                   ["IsSerializeAfter","IsNonSpeculative"])
 118     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 119     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 120     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 121
 122     msrCpsrImmCode = '''
 123         SCTLR sctlr = Sctlr;
 124         CPSR old_cpsr = Cpsr;
 125         old_cpsr.nz = CondCodesNZ;
 126         old_cpsr.c = CondCodesC;
 127         old_cpsr.v = CondCodesV;
 128         old_cpsr.ge = CondCodesGE;
 129         CPSR new_cpsr =
 130             cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
 131         Cpsr = ~CondCodesMask & new_cpsr;
 132         CondCodesNZ = new_cpsr.nz;
 133         CondCodesC = new_cpsr.c;
 134         CondCodesV = new_cpsr.v;
 135         CondCodesGE = new_cpsr.ge;
 136     '''
 137     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 138                                   { "code": msrCpsrImmCode,
 139                                     "predicate_test": condPredicateTest },
 140                                   ["IsSerializeAfter","IsNonSpeculative"])
 141     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 142     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 143     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 144
 145     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 146     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 147                                   { "code": msrSpsrImmCode,
 148                                     "predicate_test": predicateTest },
 149                                   ["IsSerializeAfter","IsNonSpeculative"])
 150     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 151     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 152     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 153
 154     revCode = '''
 155     uint32_t val = Op1;
 156     Dest = swap_byte(val);
 157     '''
 158     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 159                            { "code": revCode,
 160                              "predicate_test": predicateTest }, [])
 161     header_output += RegRegOpDeclare.subst(revIop)
 162     decoder_output += RegRegOpConstructor.subst(revIop)
 163     exec_output += PredOpExecute.subst(revIop)
 164
 165     rev16Code = '''
 166     uint32_t val = Op1;
 167     Dest = (bits(val, 15, 8) << 0) |
 168            (bits(val, 7, 0) << 8) |
 169            (bits(val, 31, 24) << 16) |
 170            (bits(val, 23, 16) << 24);
 171     '''
 172     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 173                              { "code": rev16Code,
 174                                "predicate_test": predicateTest }, [])
 175     header_output += RegRegOpDeclare.subst(rev16Iop)
 176     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 177     exec_output += PredOpExecute.subst(rev16Iop)
 178
 179     revshCode = '''
 180     uint16_t val = Op1;
 181     Dest = sext<16>(swap_byte(val));
 182     '''
 183     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 184                              { "code": revshCode,
 185                                "predicate_test": predicateTest }, [])
 186     header_output += RegRegOpDeclare.subst(revshIop)
 187     decoder_output += RegRegOpConstructor.subst(revshIop)
 188     exec_output += PredOpExecute.subst(revshIop)
 189
 190     rbitCode = '''
 191     uint8_t *opBytes = (uint8_t *)&Op1;
 192     uint32_t resTemp;
 193     uint8_t *destBytes = (uint8_t *)&resTemp;
 194     // This reverses the bytes and bits of the input, or so says the
 195     // internet.
 196     for (int i = 0; i < 4; i++) {
 197         uint32_t temp = opBytes[i];
 198         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 199         destBytes[3 - i] = (temp * 0x10101) >> 16;
 200     }
 201     Dest = resTemp;
 202     '''
 203     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 204                             { "code": rbitCode,
 205                               "predicate_test": predicateTest }, [])
 206     header_output += RegRegOpDeclare.subst(rbitIop)
 207     decoder_output += RegRegOpConstructor.subst(rbitIop)
 208     exec_output += PredOpExecute.subst(rbitIop)
 209
 210     clzCode = '''
 211         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 212     '''
 213     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 214                            { "code": clzCode,
 215                              "predicate_test": predicateTest }, [])
 216     header_output += RegRegOpDeclare.subst(clzIop)
 217     decoder_output += RegRegOpConstructor.subst(clzIop)
 218     exec_output += PredOpExecute.subst(clzIop)
 219
 220     ssatCode = '''
 221         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 222         int32_t res;
 223         if (satInt(res, operand, imm))
 224             CpsrQ = 1 << 27;
 225         Dest = res;
 226     '''
 227     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 228                             { "code": ssatCode,
 229                               "predicate_test": pickPredicate(ssatCode) }, [])
 230     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 231     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 232     exec_output += PredOpExecute.subst(ssatIop)
 233
 234     usatCode = '''
 235         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 236         int32_t res;
 237         if (uSatInt(res, operand, imm))
 238             CpsrQ = 1 << 27;
 239         Dest = res;
 240     '''
 241     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 242                             { "code": usatCode,
 243                               "predicate_test": pickPredicate(usatCode) }, [])
 244     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 245     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 246     exec_output += PredOpExecute.subst(usatIop)
 247
 248     ssat16Code = '''
 249         int32_t res;
 250         uint32_t resTemp = 0;
 251         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 252         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 253         if (satInt(res, argLow, imm))
 254             CpsrQ = 1 << 27;
 255         replaceBits(resTemp, 15, 0, res);
 256         if (satInt(res, argHigh, imm))
 257             CpsrQ = 1 << 27;
 258         replaceBits(resTemp, 31, 16, res);
 259         Dest = resTemp;
 260     '''
 261     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 262                               { "code": ssat16Code,
 263                                 "predicate_test": pickPredicate(ssat16Code) }, [])
 264     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 265     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 266     exec_output += PredOpExecute.subst(ssat16Iop)
 267
 268     usat16Code = '''
 269         int32_t res;
 270         uint32_t resTemp = 0;
 271         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 272         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 273         if (uSatInt(res, argLow, imm))
 274             CpsrQ = 1 << 27;
 275         replaceBits(resTemp, 15, 0, res);
 276         if (uSatInt(res, argHigh, imm))
 277             CpsrQ = 1 << 27;
 278         replaceBits(resTemp, 31, 16, res);
 279         Dest = resTemp;
 280     '''
 281     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 282                               { "code": usat16Code,
 283                                 "predicate_test": pickPredicate(usat16Code) }, [])
 284     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 285     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 286     exec_output += PredOpExecute.subst(usat16Iop)
 287
 288     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 289                             { "code":
 290                               "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
 291                               "predicate_test": predicateTest }, [])
 292     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 293     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 294     exec_output += PredOpExecute.subst(sxtbIop)
 295
 296     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 297                              { "code":
 298                                '''
 299                                    Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
 300                                           Op1;
 301                                ''',
 302                                "predicate_test": predicateTest }, [])
 303     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 304     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 305     exec_output += PredOpExecute.subst(sxtabIop)
 306
 307     sxtb16Code = '''
 308     uint32_t resTemp = 0;
 309     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 310     replaceBits(resTemp, 31, 16,
 311                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 312     Dest = resTemp;
 313     '''
 314     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 315                               { "code": sxtb16Code,
 316                                 "predicate_test": predicateTest }, [])
 317     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 318     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 319     exec_output += PredOpExecute.subst(sxtb16Iop)
 320
 321     sxtab16Code = '''
 322     uint32_t resTemp = 0;
 323     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 324                                         bits(Op1, 15, 0));
 325     replaceBits(resTemp, 31, 16,
 326                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 327                 bits(Op1, 31, 16));
 328     Dest = resTemp;
 329     '''
 330     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 331                                { "code": sxtab16Code,
 332                                  "predicate_test": predicateTest }, [])
 333     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 334     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 335     exec_output += PredOpExecute.subst(sxtab16Iop)
 336
 337     sxthCode = '''
 338     uint64_t rotated = (uint32_t)Op1;
 339     rotated = (rotated | (rotated << 32)) >> imm;
 340     Dest = sext<16>((uint16_t)rotated);
 341     '''
 342     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 343                               { "code": sxthCode,
 344                                 "predicate_test": predicateTest }, [])
 345     header_output += RegImmRegOpDeclare.subst(sxthIop)
 346     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 347     exec_output += PredOpExecute.subst(sxthIop)
 348
 349     sxtahCode = '''
 350     uint64_t rotated = (uint32_t)Op2;
 351     rotated = (rotated | (rotated << 32)) >> imm;
 352     Dest = sext<16>((uint16_t)rotated) + Op1;
 353     '''
 354     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 355                              { "code": sxtahCode,
 356                                "predicate_test": predicateTest }, [])
 357     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 358     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 359     exec_output += PredOpExecute.subst(sxtahIop)
 360
 361     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 362                             { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
 363                               "predicate_test": predicateTest }, [])
 364     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 365     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 366     exec_output += PredOpExecute.subst(uxtbIop)
 367
 368     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 369                              { "code":
 370                                "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
 371                                "predicate_test": predicateTest }, [])
 372     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 373     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 374     exec_output += PredOpExecute.subst(uxtabIop)
 375
 376     uxtb16Code = '''
 377     uint32_t resTemp = 0;
 378     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 379     replaceBits(resTemp, 31, 16,
 380                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 381     Dest = resTemp;
 382     '''
 383     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 384                               { "code": uxtb16Code,
 385                                 "predicate_test": predicateTest }, [])
 386     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 387     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 388     exec_output += PredOpExecute.subst(uxtb16Iop)
 389
 390     uxtab16Code = '''
 391     uint32_t resTemp = 0;
 392     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 393                                         bits(Op1, 15, 0));
 394     replaceBits(resTemp, 31, 16,
 395                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 396                 bits(Op1, 31, 16));
 397     Dest = resTemp;
 398     '''
 399     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 400                                { "code": uxtab16Code,
 401                                  "predicate_test": predicateTest }, [])
 402     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 403     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 404     exec_output += PredOpExecute.subst(uxtab16Iop)
 405
 406     uxthCode = '''
 407     uint64_t rotated = (uint32_t)Op1;
 408     rotated = (rotated | (rotated << 32)) >> imm;
 409     Dest = (uint16_t)rotated;
 410     '''
 411     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 412                               { "code": uxthCode,
 413                                 "predicate_test": predicateTest }, [])
 414     header_output += RegImmRegOpDeclare.subst(uxthIop)
 415     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 416     exec_output += PredOpExecute.subst(uxthIop)
 417
 418     uxtahCode = '''
 419     uint64_t rotated = (uint32_t)Op2;
 420     rotated = (rotated | (rotated << 32)) >> imm;
 421     Dest = (uint16_t)rotated + Op1;
 422     '''
 423     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 424                              { "code": uxtahCode,
 425                                "predicate_test": predicateTest }, [])
 426     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 427     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 428     exec_output += PredOpExecute.subst(uxtahIop)
 429
 430     selCode = '''
 431         uint32_t resTemp = 0;
 432         for (unsigned i = 0; i < 4; i++) {
 433             int low = i * 8;
 434             int high = low + 7;
 435             replaceBits(resTemp, high, low,
 436                         bits(CondCodesGE, i) ?
 437                             bits(Op1, high, low) : bits(Op2, high, low));
 438         }
 439         Dest = resTemp;
 440     '''
 441     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 442                            { "code": selCode,
 443                              "predicate_test": predicateTest }, [])
 444     header_output += RegRegRegOpDeclare.subst(selIop)
 445     decoder_output += RegRegRegOpConstructor.subst(selIop)
 446     exec_output += PredOpExecute.subst(selIop)
 447
 448     usad8Code = '''
 449         uint32_t resTemp = 0;
 450         for (unsigned i = 0; i < 4; i++) {
 451             int low = i * 8;
 452             int high = low + 7;
 453             int32_t diff = bits(Op1, high, low) -
 454                            bits(Op2, high, low);
 455             resTemp += ((diff < 0) ? -diff : diff);
 456         }
 457         Dest = resTemp;
 458     '''
 459     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 460                              { "code": usad8Code,
 461                                "predicate_test": predicateTest }, [])
 462     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 463     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 464     exec_output += PredOpExecute.subst(usad8Iop)
 465
 466     usada8Code = '''
 467         uint32_t resTemp = 0;
 468         for (unsigned i = 0; i < 4; i++) {
 469             int low = i * 8;
 470             int high = low + 7;
 471             int32_t diff = bits(Op1, high, low) -
 472                            bits(Op2, high, low);
 473             resTemp += ((diff < 0) ? -diff : diff);
 474         }
 475         Dest = Op3 + resTemp;
 476     '''
 477     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 478                               { "code": usada8Code,
 479                                 "predicate_test": predicateTest }, [])
 480     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 481     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 482     exec_output += PredOpExecute.subst(usada8Iop)
 483
 484     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 485     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 486     header_output += BasicDeclare.subst(bkptIop)
 487     decoder_output += BasicConstructor.subst(bkptIop)
 488     exec_output += BasicExecute.subst(bkptIop)
 489
 490     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 491             { "code" : "", "predicate_test" : predicateTest },
 492             ['IsNop'])
 493     header_output += BasicDeclare.subst(nopIop)
 494     decoder_output += BasicConstructor.subst(nopIop)
 495     exec_output += PredOpExecute.subst(nopIop)
 496
 497     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 498             { "code" : "", "predicate_test" : predicateTest })
 499     header_output += BasicDeclare.subst(yieldIop)
 500     decoder_output += BasicConstructor.subst(yieldIop)
 501     exec_output += PredOpExecute.subst(yieldIop)
 502
 503     wfeCode = '''
 504 #if FULL_SYSTEM
 505     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
 506     if (SevMailbox == 1) {
 507         SevMailbox = 0;
 508         PseudoInst::quiesceSkip(xc->tcBase());
 509     } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
 510         PseudoInst::quiesceSkip(xc->tcBase());
 511     } else {
 512         PseudoInst::quiesce(xc->tcBase());
 513     }
 514 #endif
 515     '''
 516     wfePredFixUpCode = '''
 517 #if FULL_SYSTEM
 518     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
 519     // and SEV interrupts
 520     SevMailbox = 1;
 521 #endif
 522     '''
 523     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 524             { "code" : wfeCode,
 525               "pred_fixup" : wfePredFixUpCode,
 526               "predicate_test" : predicateTest },
 527             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 528     header_output += BasicDeclare.subst(wfeIop)
 529     decoder_output += BasicConstructor.subst(wfeIop)
 530     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 531
 532     wfiCode = '''
 533 #if FULL_SYSTEM
 534     // WFI doesn't sleep if interrupts are pending (masked or not)
 535     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
 536         PseudoInst::quiesceSkip(xc->tcBase());
 537     } else {
 538         PseudoInst::quiesce(xc->tcBase());
 539     }
 540 #endif
 541     '''
 542     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 543             { "code" : wfiCode, "predicate_test" : predicateTest },
 544             ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
 545     header_output += BasicDeclare.subst(wfiIop)
 546     decoder_output += BasicConstructor.subst(wfiIop)
 547     exec_output += QuiescePredOpExecute.subst(wfiIop)
 548
 549     sevCode = '''
 550 #if FULL_SYSTEM
 551     SevMailbox = 1;
 552     System *sys = xc->tcBase()->getSystemPtr();
 553     for (int x = 0; x < sys->numContexts(); x++) {
 554         ThreadContext *oc = sys->getThreadContext(x);
 555         if (oc == xc->tcBase())
 556             continue;
 557         // Wake CPU with interrupt if they were sleeping
 558         if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 559             // Post Interrupt and wake cpu if needed
 560             oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
 561         }
 562     }
 563 #endif
 564     '''
 565     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 566             { "code" : sevCode, "predicate_test" : predicateTest },
 567             ["IsNonSpeculative", "IsSquashAfter"])
 568     header_output += BasicDeclare.subst(sevIop)
 569     decoder_output += BasicConstructor.subst(sevIop)
 570     exec_output += PredOpExecute.subst(sevIop)
 571
 572     itIop = InstObjParams("it", "ItInst", "PredOp", \
 573             { "code" : ";",
 574               "predicate_test" : predicateTest },
 575             ["IsNonSpeculative", "IsSerializeAfter"])
 576     header_output += BasicDeclare.subst(itIop)
 577     decoder_output += BasicConstructor.subst(itIop)
 578     exec_output += PredOpExecute.subst(itIop)
 579     unknownCode = '''
 580 #if FULL_SYSTEM
 581             return new UndefinedInstruction;
 582 #else
 583             return new UndefinedInstruction(machInst, true);
 584 #endif
 585     '''
 586     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 587                                { "code": unknownCode,
 588                                  "predicate_test": predicateTest })
 589     header_output += BasicDeclare.subst(unknownIop)
 590     decoder_output += BasicConstructor.subst(unknownIop)
 591     exec_output += PredOpExecute.subst(unknownIop)
 592
 593     ubfxCode = '''
 594         Dest = bits(Op1, imm2, imm1);
 595     '''
 596     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 597                             { "code": ubfxCode,
 598                               "predicate_test": predicateTest }, [])
 599     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 600     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 601     exec_output += PredOpExecute.subst(ubfxIop)
 602
 603     sbfxCode = '''
 604         int32_t resTemp = bits(Op1, imm2, imm1);
 605         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 606     '''
 607     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 608                             { "code": sbfxCode,
 609                               "predicate_test": predicateTest }, [])
 610     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 611     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 612     exec_output += PredOpExecute.subst(sbfxIop)
 613
 614     bfcCode = '''
 615         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 616     '''
 617     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 618                            { "code": bfcCode,
 619                              "predicate_test": predicateTest }, [])
 620     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 621     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 622     exec_output += PredOpExecute.subst(bfcIop)
 623
 624     bfiCode = '''
 625         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 626         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 627     '''
 628     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 629                            { "code": bfiCode,
 630                              "predicate_test": predicateTest }, [])
 631     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 632     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 633     exec_output += PredOpExecute.subst(bfiIop)
 634
 635     mrc15code = '''
 636     CPSR cpsr = Cpsr;
 637     if (cpsr.mode == MODE_USER)
 638 #if FULL_SYSTEM
 639         return new UndefinedInstruction;
 640 #else
 641         return new UndefinedInstruction(false, mnemonic);
 642 #endif
 643     Dest = MiscOp1;
 644     '''
 645
 646     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 647                              { "code": mrc15code,
 648                                "predicate_test": predicateTest }, [])
 649     header_output += RegRegOpDeclare.subst(mrc15Iop)
 650     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 651     exec_output += PredOpExecute.subst(mrc15Iop)
 652
 653
 654     mcr15code = '''
 655     CPSR cpsr = Cpsr;
 656     if (cpsr.mode == MODE_USER)
 657 #if FULL_SYSTEM
 658         return new UndefinedInstruction;
 659 #else
 660         return new UndefinedInstruction(false, mnemonic);
 661 #endif
 662     MiscDest = Op1;
 663     '''
 664     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 665                              { "code": mcr15code,
 666                                "predicate_test": predicateTest },
 667                                ["IsSerializeAfter","IsNonSpeculative"])
 668     header_output += RegRegOpDeclare.subst(mcr15Iop)
 669     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 670     exec_output += PredOpExecute.subst(mcr15Iop)
 671
 672     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 673                                  { "code": "Dest = MiscOp1;",
 674                                    "predicate_test": predicateTest }, [])
 675     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 676     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 677     exec_output += PredOpExecute.subst(mrc15UserIop)
 678
 679     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 680                                  { "code": "MiscDest = Op1",
 681                                    "predicate_test": predicateTest },
 682                                    ["IsSerializeAfter","IsNonSpeculative"])
 683     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 684     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 685     exec_output += PredOpExecute.subst(mcr15UserIop)
 686
 687     enterxCode = '''
 688         NextThumb = true;
 689         NextJazelle = true;
 690     '''
 691     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 692                               { "code": enterxCode,
 693                                 "predicate_test": predicateTest }, [])
 694     header_output += BasicDeclare.subst(enterxIop)
 695     decoder_output += BasicConstructor.subst(enterxIop)
 696     exec_output += PredOpExecute.subst(enterxIop)
 697
 698     leavexCode = '''
 699         NextThumb = true;
 700         NextJazelle = false;
 701     '''
 702     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 703                               { "code": leavexCode,
 704                                 "predicate_test": predicateTest }, [])
 705     header_output += BasicDeclare.subst(leavexIop)
 706     decoder_output += BasicConstructor.subst(leavexIop)
 707     exec_output += PredOpExecute.subst(leavexIop)
 708
 709     setendCode = '''
 710         CPSR cpsr = Cpsr;
 711         cpsr.e = imm;
 712         Cpsr = cpsr;
 713     '''
 714     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 715                               { "code": setendCode,
 716                                 "predicate_test": predicateTest },
 717                               ["IsSerializeAfter","IsNonSpeculative"])
 718     header_output += ImmOpDeclare.subst(setendIop)
 719     decoder_output += ImmOpConstructor.subst(setendIop)
 720     exec_output += PredOpExecute.subst(setendIop)
 721
 722     clrexCode = '''
 723         LLSCLock = 0;
 724     '''
 725     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 726                              { "code": clrexCode,
 727                                "predicate_test": predicateTest },[])
 728     header_output += BasicDeclare.subst(clrexIop)
 729     decoder_output += BasicConstructor.subst(clrexIop)
 730     exec_output += PredOpExecute.subst(clrexIop)
 731
 732     isbCode = '''
 733         fault = new FlushPipe;
 734     '''
 735     isbIop = InstObjParams("isb", "Isb", "PredOp",
 736                              {"code": isbCode,
 737                                "predicate_test": predicateTest},
 738                                 ['IsSerializeAfter'])
 739     header_output += BasicDeclare.subst(isbIop)
 740     decoder_output += BasicConstructor.subst(isbIop)
 741     exec_output += PredOpExecute.subst(isbIop)
 742
 743     dsbCode = '''
 744         fault = new FlushPipe;
 745     '''
 746     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 747                              {"code": dsbCode,
 748                                "predicate_test": predicateTest},
 749                               ['IsMemBarrier', 'IsSerializeAfter'])
 750     header_output += BasicDeclare.subst(dsbIop)
 751     decoder_output += BasicConstructor.subst(dsbIop)
 752     exec_output += PredOpExecute.subst(dsbIop)
 753
 754     dmbCode = '''
 755     '''
 756     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 757                              {"code": dmbCode,
 758                                "predicate_test": predicateTest},
 759                                ['IsMemBarrier'])
 760     header_output += BasicDeclare.subst(dmbIop)
 761     decoder_output += BasicConstructor.subst(dmbIop)
 762     exec_output += PredOpExecute.subst(dmbIop)
 763
 764     dbgCode = '''
 765     '''
 766     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 767                              {"code": dbgCode,
 768                                "predicate_test": predicateTest})
 769     header_output += BasicDeclare.subst(dbgIop)
 770     decoder_output += BasicConstructor.subst(dbgIop)
 771     exec_output += PredOpExecute.subst(dbgIop)
 772
 773     cpsCode = '''
 774     uint32_t mode = bits(imm, 4, 0);
 775     uint32_t f = bits(imm, 5);
 776     uint32_t i = bits(imm, 6);
 777     uint32_t a = bits(imm, 7);
 778     bool setMode = bits(imm, 8);
 779     bool enable = bits(imm, 9);
 780     CPSR cpsr = Cpsr;
 781     SCTLR sctlr = Sctlr;
 782     if (cpsr.mode != MODE_USER) {
 783         if (enable) {
 784             if (f) cpsr.f = 0;
 785             if (i) cpsr.i = 0;
 786             if (a) cpsr.a = 0;
 787         } else {
 788             if (f && !sctlr.nmfi) cpsr.f = 1;
 789             if (i) cpsr.i = 1;
 790             if (a) cpsr.a = 1;
 791         }
 792         if (setMode) {
 793             cpsr.mode = mode;
 794         }
 795     }
 796     Cpsr = cpsr;
 797     '''
 798     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 799                            { "code": cpsCode,
 800                              "predicate_test": predicateTest },
 801                            ["IsSerializeAfter","IsNonSpeculative"])
 802     header_output += ImmOpDeclare.subst(cpsIop)
 803     decoder_output += ImmOpConstructor.subst(cpsIop)
 804     exec_output += PredOpExecute.subst(cpsIop)
 805 }};