src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43 #if FULL_SYSTEM
  44     fault = new SupervisorCall;
  45 #else
  46     fault = new SupervisorCall(machInst);
  47 #endif
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest }, ["IsSyscall"])
  53     header_output = BasicDeclare.subst(svcIop)
  54     decoder_output = BasicConstructor.subst(svcIop)
  55     exec_output = PredOpExecute.subst(svcIop)
  56
  57 }};
  58
  59 let {{
  60
  61     header_output = decoder_output = exec_output = ""
  62
  63     mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
  64     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  65                                { "code": mrsCpsrCode,
  66                                  "predicate_test": condPredicateTest },
  67                                ["IsSerializeAfter"])
  68     header_output += MrsDeclare.subst(mrsCpsrIop)
  69     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  70     exec_output += PredOpExecute.subst(mrsCpsrIop)
  71
  72     mrsSpsrCode = "Dest = Spsr"
  73     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  74                                { "code": mrsSpsrCode,
  75                                  "predicate_test": predicateTest },
  76                                ["IsSerializeAfter"])
  77     header_output += MrsDeclare.subst(mrsSpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  79     exec_output += PredOpExecute.subst(mrsSpsrIop)
  80
  81     msrCpsrRegCode = '''
  82         SCTLR sctlr = Sctlr;
  83         uint32_t newCpsr =
  84             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
  85         Cpsr = ~CondCodesMask & newCpsr;
  86         CondCodes = CondCodesMask & newCpsr;
  87     '''
  88     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
  89                                   { "code": msrCpsrRegCode,
  90                                     "predicate_test": condPredicateTest },
  91                                   ["IsSerializeAfter","IsNonSpeculative"])
  92     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
  93     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
  94     exec_output += PredOpExecute.subst(msrCpsrRegIop)
  95
  96     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
  97     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
  98                                   { "code": msrSpsrRegCode,
  99                                     "predicate_test": predicateTest },
 100                                   ["IsSerializeAfter","IsNonSpeculative"])
 101     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 102     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 103     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 104
 105     msrCpsrImmCode = '''
 106         SCTLR sctlr = Sctlr;
 107         uint32_t newCpsr =
 108             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
 109         Cpsr = ~CondCodesMask & newCpsr;
 110         CondCodes = CondCodesMask & newCpsr;
 111     '''
 112     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 113                                   { "code": msrCpsrImmCode,
 114                                     "predicate_test": condPredicateTest },
 115                                   ["IsSerializeAfter","IsNonSpeculative"])
 116     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 117     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 118     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 119
 120     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 121     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 122                                   { "code": msrSpsrImmCode,
 123                                     "predicate_test": predicateTest },
 124                                   ["IsSerializeAfter","IsNonSpeculative"])
 125     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 126     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 127     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 128
 129     revCode = '''
 130     uint32_t val = Op1;
 131     Dest = swap_byte(val);
 132     '''
 133     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 134                            { "code": revCode,
 135                              "predicate_test": predicateTest }, [])
 136     header_output += RegRegOpDeclare.subst(revIop)
 137     decoder_output += RegRegOpConstructor.subst(revIop)
 138     exec_output += PredOpExecute.subst(revIop)
 139
 140     rev16Code = '''
 141     uint32_t val = Op1;
 142     Dest = (bits(val, 15, 8) << 0) |
 143            (bits(val, 7, 0) << 8) |
 144            (bits(val, 31, 24) << 16) |
 145            (bits(val, 23, 16) << 24);
 146     '''
 147     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 148                              { "code": rev16Code,
 149                                "predicate_test": predicateTest }, [])
 150     header_output += RegRegOpDeclare.subst(rev16Iop)
 151     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 152     exec_output += PredOpExecute.subst(rev16Iop)
 153
 154     revshCode = '''
 155     uint16_t val = Op1;
 156     Dest = sext<16>(swap_byte(val));
 157     '''
 158     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 159                              { "code": revshCode,
 160                                "predicate_test": predicateTest }, [])
 161     header_output += RegRegOpDeclare.subst(revshIop)
 162     decoder_output += RegRegOpConstructor.subst(revshIop)
 163     exec_output += PredOpExecute.subst(revshIop)
 164
 165     rbitCode = '''
 166     uint8_t *opBytes = (uint8_t *)&Op1;
 167     uint32_t resTemp;
 168     uint8_t *destBytes = (uint8_t *)&resTemp;
 169     // This reverses the bytes and bits of the input, or so says the
 170     // internet.
 171     for (int i = 0; i < 4; i++) {
 172         uint32_t temp = opBytes[i];
 173         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 174         destBytes[3 - i] = (temp * 0x10101) >> 16;
 175     }
 176     Dest = resTemp;
 177     '''
 178     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 179                             { "code": rbitCode,
 180                               "predicate_test": predicateTest }, [])
 181     header_output += RegRegOpDeclare.subst(rbitIop)
 182     decoder_output += RegRegOpConstructor.subst(rbitIop)
 183     exec_output += PredOpExecute.subst(rbitIop)
 184
 185     clzCode = '''
 186         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 187     '''
 188     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 189                            { "code": clzCode,
 190                              "predicate_test": predicateTest }, [])
 191     header_output += RegRegOpDeclare.subst(clzIop)
 192     decoder_output += RegRegOpConstructor.subst(clzIop)
 193     exec_output += PredOpExecute.subst(clzIop)
 194
 195     ssatCode = '''
 196         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 197         int32_t res;
 198         if (satInt(res, operand, imm))
 199             CondCodes = CondCodes | (1 << 27);
 200         else
 201             CondCodes = CondCodes;
 202         Dest = res;
 203     '''
 204     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 205                             { "code": ssatCode,
 206                               "predicate_test": condPredicateTest }, [])
 207     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 208     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 209     exec_output += PredOpExecute.subst(ssatIop)
 210
 211     usatCode = '''
 212         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 213         int32_t res;
 214         if (uSatInt(res, operand, imm))
 215             CondCodes = CondCodes | (1 << 27);
 216         else
 217             CondCodes = CondCodes;
 218         Dest = res;
 219     '''
 220     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 221                             { "code": usatCode,
 222                               "predicate_test": condPredicateTest }, [])
 223     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 224     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 225     exec_output += PredOpExecute.subst(usatIop)
 226
 227     ssat16Code = '''
 228         int32_t res;
 229         uint32_t resTemp = 0;
 230         CondCodes = CondCodes;
 231         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 232         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 233         if (satInt(res, argLow, imm))
 234             CondCodes = CondCodes | (1 << 27);
 235         replaceBits(resTemp, 15, 0, res);
 236         if (satInt(res, argHigh, imm))
 237             CondCodes = CondCodes | (1 << 27);
 238         replaceBits(resTemp, 31, 16, res);
 239         Dest = resTemp;
 240     '''
 241     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 242                               { "code": ssat16Code,
 243                                 "predicate_test": condPredicateTest }, [])
 244     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 245     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 246     exec_output += PredOpExecute.subst(ssat16Iop)
 247
 248     usat16Code = '''
 249         int32_t res;
 250         uint32_t resTemp = 0;
 251         CondCodes = CondCodes;
 252         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 253         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 254         if (uSatInt(res, argLow, imm))
 255             CondCodes = CondCodes | (1 << 27);
 256         replaceBits(resTemp, 15, 0, res);
 257         if (uSatInt(res, argHigh, imm))
 258             CondCodes = CondCodes | (1 << 27);
 259         replaceBits(resTemp, 31, 16, res);
 260         Dest = resTemp;
 261     '''
 262     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 263                               { "code": usat16Code,
 264                                 "predicate_test": condPredicateTest }, [])
 265     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 266     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 267     exec_output += PredOpExecute.subst(usat16Iop)
 268
 269     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 270                             { "code":
 271                               "Dest = sext<8>((uint8_t)(Op1.ud >> imm));",
 272                               "predicate_test": predicateTest }, [])
 273     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 274     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 275     exec_output += PredOpExecute.subst(sxtbIop)
 276
 277     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 278                              { "code":
 279                                '''
 280                                    Dest = sext<8>((uint8_t)(Op2.ud >> imm)) +
 281                                           Op1;
 282                                ''',
 283                                "predicate_test": predicateTest }, [])
 284     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 285     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 286     exec_output += PredOpExecute.subst(sxtabIop)
 287
 288     sxtb16Code = '''
 289     uint32_t resTemp = 0;
 290     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 291     replaceBits(resTemp, 31, 16,
 292                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 293     Dest = resTemp;
 294     '''
 295     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 296                               { "code": sxtb16Code,
 297                                 "predicate_test": predicateTest }, [])
 298     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 299     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 300     exec_output += PredOpExecute.subst(sxtb16Iop)
 301
 302     sxtab16Code = '''
 303     uint32_t resTemp = 0;
 304     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 305                                         bits(Op1, 15, 0));
 306     replaceBits(resTemp, 31, 16,
 307                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 308                 bits(Op1, 31, 16));
 309     Dest = resTemp;
 310     '''
 311     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 312                                { "code": sxtab16Code,
 313                                  "predicate_test": predicateTest }, [])
 314     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 315     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 316     exec_output += PredOpExecute.subst(sxtab16Iop)
 317
 318     sxthCode = '''
 319     uint64_t rotated = (uint32_t)Op1;
 320     rotated = (rotated | (rotated << 32)) >> imm;
 321     Dest = sext<16>((uint16_t)rotated);
 322     '''
 323     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 324                               { "code": sxthCode,
 325                                 "predicate_test": predicateTest }, [])
 326     header_output += RegImmRegOpDeclare.subst(sxthIop)
 327     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 328     exec_output += PredOpExecute.subst(sxthIop)
 329
 330     sxtahCode = '''
 331     uint64_t rotated = (uint32_t)Op2;
 332     rotated = (rotated | (rotated << 32)) >> imm;
 333     Dest = sext<16>((uint16_t)rotated) + Op1;
 334     '''
 335     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 336                              { "code": sxtahCode,
 337                                "predicate_test": predicateTest }, [])
 338     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 339     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 340     exec_output += PredOpExecute.subst(sxtahIop)
 341
 342     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 343                             { "code": "Dest = (uint8_t)(Op1.ud >> imm);",
 344                               "predicate_test": predicateTest }, [])
 345     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 346     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 347     exec_output += PredOpExecute.subst(uxtbIop)
 348
 349     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 350                              { "code":
 351                                "Dest = (uint8_t)(Op2.ud >> imm) + Op1;",
 352                                "predicate_test": predicateTest }, [])
 353     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 354     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 355     exec_output += PredOpExecute.subst(uxtabIop)
 356
 357     uxtb16Code = '''
 358     uint32_t resTemp = 0;
 359     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 360     replaceBits(resTemp, 31, 16,
 361                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 362     Dest = resTemp;
 363     '''
 364     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 365                               { "code": uxtb16Code,
 366                                 "predicate_test": predicateTest }, [])
 367     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 368     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 369     exec_output += PredOpExecute.subst(uxtb16Iop)
 370
 371     uxtab16Code = '''
 372     uint32_t resTemp = 0;
 373     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 374                                         bits(Op1, 15, 0));
 375     replaceBits(resTemp, 31, 16,
 376                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 377                 bits(Op1, 31, 16));
 378     Dest = resTemp;
 379     '''
 380     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 381                                { "code": uxtab16Code,
 382                                  "predicate_test": predicateTest }, [])
 383     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 384     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 385     exec_output += PredOpExecute.subst(uxtab16Iop)
 386
 387     uxthCode = '''
 388     uint64_t rotated = (uint32_t)Op1;
 389     rotated = (rotated | (rotated << 32)) >> imm;
 390     Dest = (uint16_t)rotated;
 391     '''
 392     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 393                               { "code": uxthCode,
 394                                 "predicate_test": predicateTest }, [])
 395     header_output += RegImmRegOpDeclare.subst(uxthIop)
 396     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 397     exec_output += PredOpExecute.subst(uxthIop)
 398
 399     uxtahCode = '''
 400     uint64_t rotated = (uint32_t)Op2;
 401     rotated = (rotated | (rotated << 32)) >> imm;
 402     Dest = (uint16_t)rotated + Op1;
 403     '''
 404     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 405                              { "code": uxtahCode,
 406                                "predicate_test": predicateTest }, [])
 407     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 408     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 409     exec_output += PredOpExecute.subst(uxtahIop)
 410
 411     selCode = '''
 412         uint32_t resTemp = 0;
 413         for (unsigned i = 0; i < 4; i++) {
 414             int low = i * 8;
 415             int high = low + 7;
 416             replaceBits(resTemp, high, low,
 417                         bits(CondCodes, 16 + i) ?
 418                             bits(Op1, high, low) : bits(Op2, high, low));
 419         }
 420         Dest = resTemp;
 421     '''
 422     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 423                            { "code": selCode,
 424                              "predicate_test": condPredicateTest }, [])
 425     header_output += RegRegRegOpDeclare.subst(selIop)
 426     decoder_output += RegRegRegOpConstructor.subst(selIop)
 427     exec_output += PredOpExecute.subst(selIop)
 428
 429     usad8Code = '''
 430         uint32_t resTemp = 0;
 431         for (unsigned i = 0; i < 4; i++) {
 432             int low = i * 8;
 433             int high = low + 7;
 434             int32_t diff = bits(Op1, high, low) -
 435                            bits(Op2, high, low);
 436             resTemp += ((diff < 0) ? -diff : diff);
 437         }
 438         Dest = resTemp;
 439     '''
 440     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 441                              { "code": usad8Code,
 442                                "predicate_test": predicateTest }, [])
 443     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 444     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 445     exec_output += PredOpExecute.subst(usad8Iop)
 446
 447     usada8Code = '''
 448         uint32_t resTemp = 0;
 449         for (unsigned i = 0; i < 4; i++) {
 450             int low = i * 8;
 451             int high = low + 7;
 452             int32_t diff = bits(Op1, high, low) -
 453                            bits(Op2, high, low);
 454             resTemp += ((diff < 0) ? -diff : diff);
 455         }
 456         Dest = Op3 + resTemp;
 457     '''
 458     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 459                               { "code": usada8Code,
 460                                 "predicate_test": predicateTest }, [])
 461     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 462     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 463     exec_output += PredOpExecute.subst(usada8Iop)
 464
 465     bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
 466             "return new PrefetchAbort(PC, ArmFault::DebugEvent);")
 467     header_output += BasicDeclare.subst(bkptIop)
 468     decoder_output += BasicConstructor.subst(bkptIop)
 469     exec_output += BasicExecute.subst(bkptIop)
 470
 471     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 472             { "code" : "", "predicate_test" : predicateTest })
 473     header_output += BasicDeclare.subst(nopIop)
 474     decoder_output += BasicConstructor.subst(nopIop)
 475     exec_output += PredOpExecute.subst(nopIop)
 476
 477     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 478             { "code" : "", "predicate_test" : predicateTest })
 479     header_output += BasicDeclare.subst(yieldIop)
 480     decoder_output += BasicConstructor.subst(yieldIop)
 481     exec_output += PredOpExecute.subst(yieldIop)
 482
 483     wfeCode = '''
 484 #if FULL_SYSTEM
 485     if (SevMailbox)
 486         SevMailbox = 0;
 487     else
 488         PseudoInst::quiesce(xc->tcBase());
 489 #endif
 490     '''
 491     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 492             { "code" : wfeCode, "predicate_test" : predicateTest },
 493             ["IsNonSpeculative", "IsQuiesce"])
 494     header_output += BasicDeclare.subst(wfeIop)
 495     decoder_output += BasicConstructor.subst(wfeIop)
 496     exec_output += PredOpExecute.subst(wfeIop)
 497
 498     wfiCode = '''
 499 #if FULL_SYSTEM
 500     PseudoInst::quiesce(xc->tcBase());
 501 #endif
 502     '''
 503     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 504             { "code" : wfiCode, "predicate_test" : predicateTest },
 505             ["IsNonSpeculative", "IsQuiesce"])
 506     header_output += BasicDeclare.subst(wfiIop)
 507     decoder_output += BasicConstructor.subst(wfiIop)
 508     exec_output += PredOpExecute.subst(wfiIop)
 509
 510     sevCode = '''
 511     // Need a way for O3 to not scoreboard these accesses as pipe flushes.
 512     System *sys = xc->tcBase()->getSystemPtr();
 513     for (int x = 0; x < sys->numContexts(); x++) {
 514         ThreadContext *oc = sys->getThreadContext(x);
 515         oc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
 516     }
 517     '''
 518     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 519             { "code" : sevCode, "predicate_test" : predicateTest },
 520             ["IsNonSpeculative", "IsQuiesce"])
 521     header_output += BasicDeclare.subst(sevIop)
 522     decoder_output += BasicConstructor.subst(sevIop)
 523     exec_output += PredOpExecute.subst(sevIop)
 524
 525     itIop = InstObjParams("it", "ItInst", "PredOp", \
 526             { "code" : "Itstate = machInst.newItstate;",
 527               "predicate_test" : predicateTest })
 528     header_output += BasicDeclare.subst(itIop)
 529     decoder_output += BasicConstructor.subst(itIop)
 530     exec_output += PredOpExecute.subst(itIop)
 531     unknownCode = '''
 532 #if FULL_SYSTEM
 533             return new UndefinedInstruction;
 534 #else
 535             return new UndefinedInstruction(machInst, true);
 536 #endif
 537     '''
 538     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 539                                { "code": unknownCode,
 540                                  "predicate_test": predicateTest })
 541     header_output += BasicDeclare.subst(unknownIop)
 542     decoder_output += BasicConstructor.subst(unknownIop)
 543     exec_output += PredOpExecute.subst(unknownIop)
 544
 545     ubfxCode = '''
 546         Dest = bits(Op1, imm2, imm1);
 547     '''
 548     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 549                             { "code": ubfxCode,
 550                               "predicate_test": predicateTest }, [])
 551     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 552     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 553     exec_output += PredOpExecute.subst(ubfxIop)
 554
 555     sbfxCode = '''
 556         int32_t resTemp = bits(Op1, imm2, imm1);
 557         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 558     '''
 559     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 560                             { "code": sbfxCode,
 561                               "predicate_test": predicateTest }, [])
 562     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 563     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 564     exec_output += PredOpExecute.subst(sbfxIop)
 565
 566     bfcCode = '''
 567         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 568     '''
 569     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 570                            { "code": bfcCode,
 571                              "predicate_test": predicateTest }, [])
 572     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 573     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 574     exec_output += PredOpExecute.subst(bfcIop)
 575
 576     bfiCode = '''
 577         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 578         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 579     '''
 580     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 581                            { "code": bfiCode,
 582                              "predicate_test": predicateTest }, [])
 583     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 584     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 585     exec_output += PredOpExecute.subst(bfiIop)
 586
 587     mrc15code = '''
 588     CPSR cpsr = Cpsr;
 589     if (cpsr.mode == MODE_USER)
 590 #if FULL_SYSTEM
 591         return new UndefinedInstruction;
 592 #else
 593         return new UndefinedInstruction(false, mnemonic);
 594 #endif
 595     Dest = MiscOp1;
 596     '''
 597
 598     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 599                              { "code": mrc15code,
 600                                "predicate_test": predicateTest }, [])
 601     header_output += RegRegOpDeclare.subst(mrc15Iop)
 602     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 603     exec_output += PredOpExecute.subst(mrc15Iop)
 604
 605
 606     mcr15code = '''
 607     CPSR cpsr = Cpsr;
 608     if (cpsr.mode == MODE_USER)
 609 #if FULL_SYSTEM
 610         return new UndefinedInstruction;
 611 #else
 612         return new UndefinedInstruction(false, mnemonic);
 613 #endif
 614     MiscDest = Op1;
 615     '''
 616     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 617                              { "code": mcr15code,
 618                                "predicate_test": predicateTest },
 619                                ["IsSerializeAfter","IsNonSpeculative"])
 620     header_output += RegRegOpDeclare.subst(mcr15Iop)
 621     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 622     exec_output += PredOpExecute.subst(mcr15Iop)
 623
 624     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 625                                  { "code": "Dest = MiscOp1;",
 626                                    "predicate_test": predicateTest }, [])
 627     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 628     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 629     exec_output += PredOpExecute.subst(mrc15UserIop)
 630
 631     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 632                                  { "code": "MiscDest = Op1",
 633                                    "predicate_test": predicateTest },
 634                                    ["IsSerializeAfter","IsNonSpeculative"])
 635     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 636     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 637     exec_output += PredOpExecute.subst(mcr15UserIop)
 638
 639     enterxCode = '''
 640         FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift);
 641     '''
 642     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 643                               { "code": enterxCode,
 644                                 "predicate_test": predicateTest }, [])
 645     header_output += BasicDeclare.subst(enterxIop)
 646     decoder_output += BasicConstructor.subst(enterxIop)
 647     exec_output += PredOpExecute.subst(enterxIop)
 648
 649     leavexCode = '''
 650         FNPC = (NPC & ~(1ULL << PcJBitShift)) | (1ULL << PcTBitShift);
 651     '''
 652     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 653                               { "code": leavexCode,
 654                                 "predicate_test": predicateTest }, [])
 655     header_output += BasicDeclare.subst(leavexIop)
 656     decoder_output += BasicConstructor.subst(leavexIop)
 657     exec_output += PredOpExecute.subst(leavexIop)
 658
 659     setendCode = '''
 660         CPSR cpsr = Cpsr;
 661         cpsr.e = imm;
 662         Cpsr = cpsr;
 663     '''
 664     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 665                               { "code": setendCode,
 666                                 "predicate_test": predicateTest }, [])
 667     header_output += ImmOpDeclare.subst(setendIop)
 668     decoder_output += ImmOpConstructor.subst(setendIop)
 669     exec_output += PredOpExecute.subst(setendIop)
 670
 671     clrexCode = '''
 672         unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
 673         fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
 674     '''
 675     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 676                              { "code": clrexCode,
 677                                "predicate_test": predicateTest },[])
 678     header_output += ClrexDeclare.subst(clrexIop)
 679     decoder_output += BasicConstructor.subst(clrexIop)
 680     exec_output += PredOpExecute.subst(clrexIop)
 681     exec_output += ClrexInitiateAcc.subst(clrexIop)
 682     exec_output += ClrexCompleteAcc.subst(clrexIop)
 683
 684     isbCode = '''
 685     '''
 686     isbIop = InstObjParams("isb", "Isb", "PredOp",
 687                              {"code": isbCode,
 688                                "predicate_test": predicateTest}, ['IsSerializing'])
 689     header_output += BasicDeclare.subst(isbIop)
 690     decoder_output += BasicConstructor.subst(isbIop)
 691     exec_output += PredOpExecute.subst(isbIop)
 692
 693     dsbCode = '''
 694     '''
 695     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 696                              {"code": dsbCode,
 697                                "predicate_test": predicateTest},['IsMemBarrier'])
 698     header_output += BasicDeclare.subst(dsbIop)
 699     decoder_output += BasicConstructor.subst(dsbIop)
 700     exec_output += PredOpExecute.subst(dsbIop)
 701
 702     dmbCode = '''
 703     '''
 704     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 705                              {"code": dmbCode,
 706                                "predicate_test": predicateTest},['IsMemBarrier'])
 707     header_output += BasicDeclare.subst(dmbIop)
 708     decoder_output += BasicConstructor.subst(dmbIop)
 709     exec_output += PredOpExecute.subst(dmbIop)
 710
 711     cpsCode = '''
 712     uint32_t mode = bits(imm, 4, 0);
 713     uint32_t f = bits(imm, 5);
 714     uint32_t i = bits(imm, 6);
 715     uint32_t a = bits(imm, 7);
 716     bool setMode = bits(imm, 8);
 717     bool enable = bits(imm, 9);
 718     CPSR cpsr = Cpsr;
 719     SCTLR sctlr = Sctlr;
 720     if (cpsr.mode != MODE_USER) {
 721         if (enable) {
 722             if (f) cpsr.f = 0;
 723             if (i) cpsr.i = 0;
 724             if (a) cpsr.a = 0;
 725         } else {
 726             if (f && !sctlr.nmfi) cpsr.f = 1;
 727             if (i) cpsr.i = 1;
 728             if (a) cpsr.a = 1;
 729         }
 730         if (setMode) {
 731             cpsr.mode = mode;
 732         }
 733     }
 734     Cpsr = cpsr;
 735     '''
 736     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 737                            { "code": cpsCode,
 738                              "predicate_test": predicateTest },
 739                            ["IsSerializeAfter","IsNonSpeculative"])
 740     header_output += ImmOpDeclare.subst(cpsIop)
 741     decoder_output += ImmOpConstructor.subst(cpsIop)
 742     exec_output += PredOpExecute.subst(cpsIop)
 743 }};