src/arch/arm/isa/insts/misc.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010-2012 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41
  42     svcCode = '''
  43     if (FullSystem) {
  44         fault = new SupervisorCall;
  45     } else {
  46         fault = new SupervisorCall(machInst);
  47     }
  48     '''
  49
  50     svcIop = InstObjParams("svc", "Svc", "PredOp",
  51                            { "code": svcCode,
  52                              "predicate_test": predicateTest },
  53                            ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
  54     header_output = BasicDeclare.subst(svcIop)
  55     decoder_output = BasicConstructor.subst(svcIop)
  56     exec_output = PredOpExecute.subst(svcIop)
  57
  58 }};
  59
  60 let {{
  61
  62     header_output = decoder_output = exec_output = ""
  63
  64     mrsCpsrCode = '''
  65         CPSR cpsr = Cpsr;
  66         cpsr.nz = CondCodesNZ;
  67         cpsr.c = CondCodesC;
  68         cpsr.v = CondCodesV;
  69         cpsr.ge = CondCodesGE;
  70         Dest = cpsr & 0xF8FF03DF
  71     '''
  72
  73     mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
  74                                { "code": mrsCpsrCode,
  75                                  "predicate_test": condPredicateTest },
  76                                ["IsSerializeBefore"])
  77     header_output += MrsDeclare.subst(mrsCpsrIop)
  78     decoder_output += MrsConstructor.subst(mrsCpsrIop)
  79     exec_output += PredOpExecute.subst(mrsCpsrIop)
  80
  81     mrsSpsrCode = "Dest = Spsr"
  82     mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
  83                                { "code": mrsSpsrCode,
  84                                  "predicate_test": predicateTest },
  85                                ["IsSerializeBefore"])
  86     header_output += MrsDeclare.subst(mrsSpsrIop)
  87     decoder_output += MrsConstructor.subst(mrsSpsrIop)
  88     exec_output += PredOpExecute.subst(mrsSpsrIop)
  89
  90     msrCpsrRegCode = '''
  91         SCTLR sctlr = Sctlr;
  92         CPSR old_cpsr = Cpsr;
  93         old_cpsr.nz = CondCodesNZ;
  94         old_cpsr.c = CondCodesC;
  95         old_cpsr.v = CondCodesV;
  96         old_cpsr.ge = CondCodesGE;
  97
  98         CPSR new_cpsr =
  99             cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
 100         Cpsr = ~CondCodesMask & new_cpsr;
 101         CondCodesNZ = new_cpsr.nz;
 102         CondCodesC = new_cpsr.c;
 103         CondCodesV = new_cpsr.v;
 104         CondCodesGE = new_cpsr.ge;
 105     '''
 106     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
 107                                   { "code": msrCpsrRegCode,
 108                                     "predicate_test": condPredicateTest },
 109                                   ["IsSerializeAfter","IsNonSpeculative"])
 110     header_output += MsrRegDeclare.subst(msrCpsrRegIop)
 111     decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
 112     exec_output += PredOpExecute.subst(msrCpsrRegIop)
 113
 114     msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
 115     msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
 116                                   { "code": msrSpsrRegCode,
 117                                     "predicate_test": predicateTest },
 118                                   ["IsSerializeAfter","IsNonSpeculative"])
 119     header_output += MsrRegDeclare.subst(msrSpsrRegIop)
 120     decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
 121     exec_output += PredOpExecute.subst(msrSpsrRegIop)
 122
 123     msrCpsrImmCode = '''
 124         SCTLR sctlr = Sctlr;
 125         CPSR old_cpsr = Cpsr;
 126         old_cpsr.nz = CondCodesNZ;
 127         old_cpsr.c = CondCodesC;
 128         old_cpsr.v = CondCodesV;
 129         old_cpsr.ge = CondCodesGE;
 130         CPSR new_cpsr =
 131             cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
 132         Cpsr = ~CondCodesMask & new_cpsr;
 133         CondCodesNZ = new_cpsr.nz;
 134         CondCodesC = new_cpsr.c;
 135         CondCodesV = new_cpsr.v;
 136         CondCodesGE = new_cpsr.ge;
 137     '''
 138     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
 139                                   { "code": msrCpsrImmCode,
 140                                     "predicate_test": condPredicateTest },
 141                                   ["IsSerializeAfter","IsNonSpeculative"])
 142     header_output += MsrImmDeclare.subst(msrCpsrImmIop)
 143     decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
 144     exec_output += PredOpExecute.subst(msrCpsrImmIop)
 145
 146     msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
 147     msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
 148                                   { "code": msrSpsrImmCode,
 149                                     "predicate_test": predicateTest },
 150                                   ["IsSerializeAfter","IsNonSpeculative"])
 151     header_output += MsrImmDeclare.subst(msrSpsrImmIop)
 152     decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
 153     exec_output += PredOpExecute.subst(msrSpsrImmIop)
 154
 155     revCode = '''
 156     uint32_t val = Op1;
 157     Dest = swap_byte(val);
 158     '''
 159     revIop = InstObjParams("rev", "Rev", "RegRegOp",
 160                            { "code": revCode,
 161                              "predicate_test": predicateTest }, [])
 162     header_output += RegRegOpDeclare.subst(revIop)
 163     decoder_output += RegRegOpConstructor.subst(revIop)
 164     exec_output += PredOpExecute.subst(revIop)
 165
 166     rev16Code = '''
 167     uint32_t val = Op1;
 168     Dest = (bits(val, 15, 8) << 0) |
 169            (bits(val, 7, 0) << 8) |
 170            (bits(val, 31, 24) << 16) |
 171            (bits(val, 23, 16) << 24);
 172     '''
 173     rev16Iop = InstObjParams("rev16", "Rev16", "RegRegOp",
 174                              { "code": rev16Code,
 175                                "predicate_test": predicateTest }, [])
 176     header_output += RegRegOpDeclare.subst(rev16Iop)
 177     decoder_output += RegRegOpConstructor.subst(rev16Iop)
 178     exec_output += PredOpExecute.subst(rev16Iop)
 179
 180     revshCode = '''
 181     uint16_t val = Op1;
 182     Dest = sext<16>(swap_byte(val));
 183     '''
 184     revshIop = InstObjParams("revsh", "Revsh", "RegRegOp",
 185                              { "code": revshCode,
 186                                "predicate_test": predicateTest }, [])
 187     header_output += RegRegOpDeclare.subst(revshIop)
 188     decoder_output += RegRegOpConstructor.subst(revshIop)
 189     exec_output += PredOpExecute.subst(revshIop)
 190
 191     rbitCode = '''
 192     uint8_t *opBytes = (uint8_t *)&Op1;
 193     uint32_t resTemp;
 194     uint8_t *destBytes = (uint8_t *)&resTemp;
 195     // This reverses the bytes and bits of the input, or so says the
 196     // internet.
 197     for (int i = 0; i < 4; i++) {
 198         uint32_t temp = opBytes[i];
 199         temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440);
 200         destBytes[3 - i] = (temp * 0x10101) >> 16;
 201     }
 202     Dest = resTemp;
 203     '''
 204     rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp",
 205                             { "code": rbitCode,
 206                               "predicate_test": predicateTest }, [])
 207     header_output += RegRegOpDeclare.subst(rbitIop)
 208     decoder_output += RegRegOpConstructor.subst(rbitIop)
 209     exec_output += PredOpExecute.subst(rbitIop)
 210
 211     clzCode = '''
 212         Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
 213     '''
 214     clzIop = InstObjParams("clz", "Clz", "RegRegOp",
 215                            { "code": clzCode,
 216                              "predicate_test": predicateTest }, [])
 217     header_output += RegRegOpDeclare.subst(clzIop)
 218     decoder_output += RegRegOpConstructor.subst(clzIop)
 219     exec_output += PredOpExecute.subst(clzIop)
 220
 221     ssatCode = '''
 222         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 223         int32_t res;
 224         if (satInt(res, operand, imm))
 225             CpsrQ = 1 << 27;
 226         Dest = res;
 227     '''
 228     ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
 229                             { "code": ssatCode,
 230                               "predicate_test": pickPredicate(ssatCode) }, [])
 231     header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
 232     decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
 233     exec_output += PredOpExecute.subst(ssatIop)
 234
 235     usatCode = '''
 236         int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
 237         int32_t res;
 238         if (uSatInt(res, operand, imm))
 239             CpsrQ = 1 << 27;
 240         Dest = res;
 241     '''
 242     usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
 243                             { "code": usatCode,
 244                               "predicate_test": pickPredicate(usatCode) }, [])
 245     header_output += RegImmRegShiftOpDeclare.subst(usatIop)
 246     decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
 247     exec_output += PredOpExecute.subst(usatIop)
 248
 249     ssat16Code = '''
 250         int32_t res;
 251         uint32_t resTemp = 0;
 252         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 253         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 254         if (satInt(res, argLow, imm))
 255             CpsrQ = 1 << 27;
 256         replaceBits(resTemp, 15, 0, res);
 257         if (satInt(res, argHigh, imm))
 258             CpsrQ = 1 << 27;
 259         replaceBits(resTemp, 31, 16, res);
 260         Dest = resTemp;
 261     '''
 262     ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
 263                               { "code": ssat16Code,
 264                                 "predicate_test": pickPredicate(ssat16Code) }, [])
 265     header_output += RegImmRegOpDeclare.subst(ssat16Iop)
 266     decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
 267     exec_output += PredOpExecute.subst(ssat16Iop)
 268
 269     usat16Code = '''
 270         int32_t res;
 271         uint32_t resTemp = 0;
 272         int32_t argLow = sext<16>(bits(Op1, 15, 0));
 273         int32_t argHigh = sext<16>(bits(Op1, 31, 16));
 274         if (uSatInt(res, argLow, imm))
 275             CpsrQ = 1 << 27;
 276         replaceBits(resTemp, 15, 0, res);
 277         if (uSatInt(res, argHigh, imm))
 278             CpsrQ = 1 << 27;
 279         replaceBits(resTemp, 31, 16, res);
 280         Dest = resTemp;
 281     '''
 282     usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
 283                               { "code": usat16Code,
 284                                 "predicate_test": pickPredicate(usat16Code) }, [])
 285     header_output += RegImmRegOpDeclare.subst(usat16Iop)
 286     decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
 287     exec_output += PredOpExecute.subst(usat16Iop)
 288
 289     sxtbIop = InstObjParams("sxtb", "Sxtb", "RegImmRegOp",
 290                             { "code":
 291                               "Dest = sext<8>((uint8_t)(Op1_ud >> imm));",
 292                               "predicate_test": predicateTest }, [])
 293     header_output += RegImmRegOpDeclare.subst(sxtbIop)
 294     decoder_output += RegImmRegOpConstructor.subst(sxtbIop)
 295     exec_output += PredOpExecute.subst(sxtbIop)
 296
 297     sxtabIop = InstObjParams("sxtab", "Sxtab", "RegRegRegImmOp",
 298                              { "code":
 299                                '''
 300                                    Dest = sext<8>((uint8_t)(Op2_ud >> imm)) +
 301                                           Op1;
 302                                ''',
 303                                "predicate_test": predicateTest }, [])
 304     header_output += RegRegRegImmOpDeclare.subst(sxtabIop)
 305     decoder_output += RegRegRegImmOpConstructor.subst(sxtabIop)
 306     exec_output += PredOpExecute.subst(sxtabIop)
 307
 308     sxtb16Code = '''
 309     uint32_t resTemp = 0;
 310     replaceBits(resTemp, 15, 0, sext<8>(bits(Op1, imm + 7, imm)));
 311     replaceBits(resTemp, 31, 16,
 312                 sext<8>(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 313     Dest = resTemp;
 314     '''
 315     sxtb16Iop = InstObjParams("sxtb16", "Sxtb16", "RegImmRegOp",
 316                               { "code": sxtb16Code,
 317                                 "predicate_test": predicateTest }, [])
 318     header_output += RegImmRegOpDeclare.subst(sxtb16Iop)
 319     decoder_output += RegImmRegOpConstructor.subst(sxtb16Iop)
 320     exec_output += PredOpExecute.subst(sxtb16Iop)
 321
 322     sxtab16Code = '''
 323     uint32_t resTemp = 0;
 324     replaceBits(resTemp, 15, 0, sext<8>(bits(Op2, imm + 7, imm)) +
 325                                         bits(Op1, 15, 0));
 326     replaceBits(resTemp, 31, 16,
 327                 sext<8>(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 328                 bits(Op1, 31, 16));
 329     Dest = resTemp;
 330     '''
 331     sxtab16Iop = InstObjParams("sxtab16", "Sxtab16", "RegRegRegImmOp",
 332                                { "code": sxtab16Code,
 333                                  "predicate_test": predicateTest }, [])
 334     header_output += RegRegRegImmOpDeclare.subst(sxtab16Iop)
 335     decoder_output += RegRegRegImmOpConstructor.subst(sxtab16Iop)
 336     exec_output += PredOpExecute.subst(sxtab16Iop)
 337
 338     sxthCode = '''
 339     uint64_t rotated = (uint32_t)Op1;
 340     rotated = (rotated | (rotated << 32)) >> imm;
 341     Dest = sext<16>((uint16_t)rotated);
 342     '''
 343     sxthIop = InstObjParams("sxth", "Sxth", "RegImmRegOp",
 344                               { "code": sxthCode,
 345                                 "predicate_test": predicateTest }, [])
 346     header_output += RegImmRegOpDeclare.subst(sxthIop)
 347     decoder_output += RegImmRegOpConstructor.subst(sxthIop)
 348     exec_output += PredOpExecute.subst(sxthIop)
 349
 350     sxtahCode = '''
 351     uint64_t rotated = (uint32_t)Op2;
 352     rotated = (rotated | (rotated << 32)) >> imm;
 353     Dest = sext<16>((uint16_t)rotated) + Op1;
 354     '''
 355     sxtahIop = InstObjParams("sxtah", "Sxtah", "RegRegRegImmOp",
 356                              { "code": sxtahCode,
 357                                "predicate_test": predicateTest }, [])
 358     header_output += RegRegRegImmOpDeclare.subst(sxtahIop)
 359     decoder_output += RegRegRegImmOpConstructor.subst(sxtahIop)
 360     exec_output += PredOpExecute.subst(sxtahIop)
 361
 362     uxtbIop = InstObjParams("uxtb", "Uxtb", "RegImmRegOp",
 363                             { "code": "Dest = (uint8_t)(Op1_ud >> imm);",
 364                               "predicate_test": predicateTest }, [])
 365     header_output += RegImmRegOpDeclare.subst(uxtbIop)
 366     decoder_output += RegImmRegOpConstructor.subst(uxtbIop)
 367     exec_output += PredOpExecute.subst(uxtbIop)
 368
 369     uxtabIop = InstObjParams("uxtab", "Uxtab", "RegRegRegImmOp",
 370                              { "code":
 371                                "Dest = (uint8_t)(Op2_ud >> imm) + Op1;",
 372                                "predicate_test": predicateTest }, [])
 373     header_output += RegRegRegImmOpDeclare.subst(uxtabIop)
 374     decoder_output += RegRegRegImmOpConstructor.subst(uxtabIop)
 375     exec_output += PredOpExecute.subst(uxtabIop)
 376
 377     uxtb16Code = '''
 378     uint32_t resTemp = 0;
 379     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op1, imm + 7, imm)));
 380     replaceBits(resTemp, 31, 16,
 381                 (uint8_t)(bits(Op1, (imm + 23) % 32, (imm + 16) % 32)));
 382     Dest = resTemp;
 383     '''
 384     uxtb16Iop = InstObjParams("uxtb16", "Uxtb16", "RegImmRegOp",
 385                               { "code": uxtb16Code,
 386                                 "predicate_test": predicateTest }, [])
 387     header_output += RegImmRegOpDeclare.subst(uxtb16Iop)
 388     decoder_output += RegImmRegOpConstructor.subst(uxtb16Iop)
 389     exec_output += PredOpExecute.subst(uxtb16Iop)
 390
 391     uxtab16Code = '''
 392     uint32_t resTemp = 0;
 393     replaceBits(resTemp, 15, 0, (uint8_t)(bits(Op2, imm + 7, imm)) +
 394                                         bits(Op1, 15, 0));
 395     replaceBits(resTemp, 31, 16,
 396                 (uint8_t)(bits(Op2, (imm + 23) % 32, (imm + 16) % 32)) +
 397                 bits(Op1, 31, 16));
 398     Dest = resTemp;
 399     '''
 400     uxtab16Iop = InstObjParams("uxtab16", "Uxtab16", "RegRegRegImmOp",
 401                                { "code": uxtab16Code,
 402                                  "predicate_test": predicateTest }, [])
 403     header_output += RegRegRegImmOpDeclare.subst(uxtab16Iop)
 404     decoder_output += RegRegRegImmOpConstructor.subst(uxtab16Iop)
 405     exec_output += PredOpExecute.subst(uxtab16Iop)
 406
 407     uxthCode = '''
 408     uint64_t rotated = (uint32_t)Op1;
 409     rotated = (rotated | (rotated << 32)) >> imm;
 410     Dest = (uint16_t)rotated;
 411     '''
 412     uxthIop = InstObjParams("uxth", "Uxth", "RegImmRegOp",
 413                               { "code": uxthCode,
 414                                 "predicate_test": predicateTest }, [])
 415     header_output += RegImmRegOpDeclare.subst(uxthIop)
 416     decoder_output += RegImmRegOpConstructor.subst(uxthIop)
 417     exec_output += PredOpExecute.subst(uxthIop)
 418
 419     uxtahCode = '''
 420     uint64_t rotated = (uint32_t)Op2;
 421     rotated = (rotated | (rotated << 32)) >> imm;
 422     Dest = (uint16_t)rotated + Op1;
 423     '''
 424     uxtahIop = InstObjParams("uxtah", "Uxtah", "RegRegRegImmOp",
 425                              { "code": uxtahCode,
 426                                "predicate_test": predicateTest }, [])
 427     header_output += RegRegRegImmOpDeclare.subst(uxtahIop)
 428     decoder_output += RegRegRegImmOpConstructor.subst(uxtahIop)
 429     exec_output += PredOpExecute.subst(uxtahIop)
 430
 431     selCode = '''
 432         uint32_t resTemp = 0;
 433         for (unsigned i = 0; i < 4; i++) {
 434             int low = i * 8;
 435             int high = low + 7;
 436             replaceBits(resTemp, high, low,
 437                         bits(CondCodesGE, i) ?
 438                             bits(Op1, high, low) : bits(Op2, high, low));
 439         }
 440         Dest = resTemp;
 441     '''
 442     selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
 443                            { "code": selCode,
 444                              "predicate_test": predicateTest }, [])
 445     header_output += RegRegRegOpDeclare.subst(selIop)
 446     decoder_output += RegRegRegOpConstructor.subst(selIop)
 447     exec_output += PredOpExecute.subst(selIop)
 448
 449     usad8Code = '''
 450         uint32_t resTemp = 0;
 451         for (unsigned i = 0; i < 4; i++) {
 452             int low = i * 8;
 453             int high = low + 7;
 454             int32_t diff = bits(Op1, high, low) -
 455                            bits(Op2, high, low);
 456             resTemp += ((diff < 0) ? -diff : diff);
 457         }
 458         Dest = resTemp;
 459     '''
 460     usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
 461                              { "code": usad8Code,
 462                                "predicate_test": predicateTest }, [])
 463     header_output += RegRegRegOpDeclare.subst(usad8Iop)
 464     decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
 465     exec_output += PredOpExecute.subst(usad8Iop)
 466
 467     usada8Code = '''
 468         uint32_t resTemp = 0;
 469         for (unsigned i = 0; i < 4; i++) {
 470             int low = i * 8;
 471             int high = low + 7;
 472             int32_t diff = bits(Op1, high, low) -
 473                            bits(Op2, high, low);
 474             resTemp += ((diff < 0) ? -diff : diff);
 475         }
 476         Dest = Op3 + resTemp;
 477     '''
 478     usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
 479                               { "code": usada8Code,
 480                                 "predicate_test": predicateTest }, [])
 481     header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
 482     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
 483     exec_output += PredOpExecute.subst(usada8Iop)
 484
 485     bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
 486     bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode)
 487     header_output += BasicDeclare.subst(bkptIop)
 488     decoder_output += BasicConstructor.subst(bkptIop)
 489     exec_output += BasicExecute.subst(bkptIop)
 490
 491     nopIop = InstObjParams("nop", "NopInst", "PredOp", \
 492             { "code" : "", "predicate_test" : predicateTest },
 493             ['IsNop'])
 494     header_output += BasicDeclare.subst(nopIop)
 495     decoder_output += BasicConstructor.subst(nopIop)
 496     exec_output += PredOpExecute.subst(nopIop)
 497
 498     yieldIop = InstObjParams("yield", "YieldInst", "PredOp", \
 499             { "code" : "", "predicate_test" : predicateTest })
 500     header_output += BasicDeclare.subst(yieldIop)
 501     decoder_output += BasicConstructor.subst(yieldIop)
 502     exec_output += PredOpExecute.subst(yieldIop)
 503
 504     wfeCode = '''
 505     // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending
 506     if (SevMailbox == 1) {
 507         SevMailbox = 0;
 508         PseudoInst::quiesceSkip(xc->tcBase());
 509     } else if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkInterrupts(xc->tcBase())) {
 510         PseudoInst::quiesceSkip(xc->tcBase());
 511     } else {
 512         PseudoInst::quiesce(xc->tcBase());
 513     }
 514     '''
 515     wfePredFixUpCode = '''
 516     // WFE is predicated false, reset SevMailbox to reduce spurious sleeps
 517     // and SEV interrupts
 518     SevMailbox = 1;
 519     '''
 520     wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \
 521             { "code" : wfeCode,
 522               "pred_fixup" : wfePredFixUpCode,
 523               "predicate_test" : predicateTest },
 524             ["IsNonSpeculative", "IsQuiesce",
 525              "IsSerializeAfter", "IsUnverifiable"])
 526     header_output += BasicDeclare.subst(wfeIop)
 527     decoder_output += BasicConstructor.subst(wfeIop)
 528     exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
 529
 530     wfiCode = '''
 531     // WFI doesn't sleep if interrupts are pending (masked or not)
 532     if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) {
 533         PseudoInst::quiesceSkip(xc->tcBase());
 534     } else {
 535         PseudoInst::quiesce(xc->tcBase());
 536     }
 537     '''
 538     wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
 539             { "code" : wfiCode, "predicate_test" : predicateTest },
 540             ["IsNonSpeculative", "IsQuiesce",
 541              "IsSerializeAfter", "IsUnverifiable"])
 542     header_output += BasicDeclare.subst(wfiIop)
 543     decoder_output += BasicConstructor.subst(wfiIop)
 544     exec_output += QuiescePredOpExecute.subst(wfiIop)
 545
 546     sevCode = '''
 547     SevMailbox = 1;
 548     System *sys = xc->tcBase()->getSystemPtr();
 549     for (int x = 0; x < sys->numContexts(); x++) {
 550         ThreadContext *oc = sys->getThreadContext(x);
 551         if (oc == xc->tcBase())
 552             continue;
 553         // Wake CPU with interrupt if they were sleeping
 554         if (oc->readMiscReg(MISCREG_SEV_MAILBOX) == 0) {
 555             // Post Interrupt and wake cpu if needed
 556             oc->getCpuPtr()->postInterrupt(INT_SEV, 0);
 557         }
 558     }
 559     '''
 560     sevIop = InstObjParams("sev", "SevInst", "PredOp", \
 561             { "code" : sevCode, "predicate_test" : predicateTest },
 562             ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
 563     header_output += BasicDeclare.subst(sevIop)
 564     decoder_output += BasicConstructor.subst(sevIop)
 565     exec_output += PredOpExecute.subst(sevIop)
 566
 567     itIop = InstObjParams("it", "ItInst", "PredOp", \
 568             { "code" : ";",
 569               "predicate_test" : predicateTest }, [])
 570     header_output += BasicDeclare.subst(itIop)
 571     decoder_output += BasicConstructor.subst(itIop)
 572     exec_output += PredOpExecute.subst(itIop)
 573     unknownCode = '''
 574     if (FullSystem)
 575         return new UndefinedInstruction;
 576     else
 577         return new UndefinedInstruction(machInst, true);
 578     '''
 579     unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
 580                                { "code": unknownCode,
 581                                  "predicate_test": predicateTest })
 582     header_output += BasicDeclare.subst(unknownIop)
 583     decoder_output += BasicConstructor.subst(unknownIop)
 584     exec_output += PredOpExecute.subst(unknownIop)
 585
 586     ubfxCode = '''
 587         Dest = bits(Op1, imm2, imm1);
 588     '''
 589     ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
 590                             { "code": ubfxCode,
 591                               "predicate_test": predicateTest }, [])
 592     header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
 593     decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
 594     exec_output += PredOpExecute.subst(ubfxIop)
 595
 596     sbfxCode = '''
 597         int32_t resTemp = bits(Op1, imm2, imm1);
 598         Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
 599     '''
 600     sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
 601                             { "code": sbfxCode,
 602                               "predicate_test": predicateTest }, [])
 603     header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
 604     decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
 605     exec_output += PredOpExecute.subst(sbfxIop)
 606
 607     bfcCode = '''
 608         Dest = Op1 & ~(mask(imm2 - imm1 + 1) << imm1);
 609     '''
 610     bfcIop = InstObjParams("bfc", "Bfc", "RegRegImmImmOp",
 611                            { "code": bfcCode,
 612                              "predicate_test": predicateTest }, [])
 613     header_output += RegRegImmImmOpDeclare.subst(bfcIop)
 614     decoder_output += RegRegImmImmOpConstructor.subst(bfcIop)
 615     exec_output += PredOpExecute.subst(bfcIop)
 616
 617     bfiCode = '''
 618         uint32_t bitMask = (mask(imm2 - imm1 + 1) << imm1);
 619         Dest = ((Op1 << imm1) & bitMask) | (Dest & ~bitMask);
 620     '''
 621     bfiIop = InstObjParams("bfi", "Bfi", "RegRegImmImmOp",
 622                            { "code": bfiCode,
 623                              "predicate_test": predicateTest }, [])
 624     header_output += RegRegImmImmOpDeclare.subst(bfiIop)
 625     decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
 626     exec_output += PredOpExecute.subst(bfiIop)
 627
 628     mrc14code = '''
 629     CPSR cpsr = Cpsr;
 630     if (cpsr.mode == MODE_USER) {
 631         if (FullSystem)
 632             return new UndefinedInstruction;
 633         else
 634             return new UndefinedInstruction(false, mnemonic);
 635     }
 636     Dest = MiscOp1;
 637     '''
 638
 639     mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp",
 640                              { "code": mrc14code,
 641                                "predicate_test": predicateTest }, [])
 642     header_output += RegRegOpDeclare.subst(mrc14Iop)
 643     decoder_output += RegRegOpConstructor.subst(mrc14Iop)
 644     exec_output += PredOpExecute.subst(mrc14Iop)
 645
 646
 647     mcr14code = '''
 648     CPSR cpsr = Cpsr;
 649     if (cpsr.mode == MODE_USER) {
 650         if (FullSystem)
 651             return new UndefinedInstruction;
 652         else
 653             return new UndefinedInstruction(false, mnemonic);
 654     }
 655     MiscDest = Op1;
 656     '''
 657     mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp",
 658                              { "code": mcr14code,
 659                                "predicate_test": predicateTest },
 660                                ["IsSerializeAfter","IsNonSpeculative"])
 661     header_output += RegRegOpDeclare.subst(mcr14Iop)
 662     decoder_output += RegRegOpConstructor.subst(mcr14Iop)
 663     exec_output += PredOpExecute.subst(mcr14Iop)
 664
 665     mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp",
 666                                  { "code": "Dest = MiscOp1;",
 667                                    "predicate_test": predicateTest }, [])
 668     header_output += RegRegOpDeclare.subst(mrc14UserIop)
 669     decoder_output += RegRegOpConstructor.subst(mrc14UserIop)
 670     exec_output += PredOpExecute.subst(mrc14UserIop)
 671
 672     mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp",
 673                                  { "code": "MiscDest = Op1",
 674                                    "predicate_test": predicateTest },
 675                                    ["IsSerializeAfter","IsNonSpeculative"])
 676     header_output += RegRegOpDeclare.subst(mcr14UserIop)
 677     decoder_output += RegRegOpConstructor.subst(mcr14UserIop)
 678     exec_output += PredOpExecute.subst(mcr14UserIop)
 679
 680     mrc15code = '''
 681     CPSR cpsr = Cpsr;
 682     if (cpsr.mode == MODE_USER) {
 683         if (FullSystem)
 684             return new UndefinedInstruction;
 685         else
 686             return new UndefinedInstruction(false, mnemonic);
 687     }
 688     Dest = MiscOp1;
 689     '''
 690
 691     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
 692                              { "code": mrc15code,
 693                                "predicate_test": predicateTest }, [])
 694     header_output += RegRegOpDeclare.subst(mrc15Iop)
 695     decoder_output += RegRegOpConstructor.subst(mrc15Iop)
 696     exec_output += PredOpExecute.subst(mrc15Iop)
 697
 698
 699     mcr15code = '''
 700     CPSR cpsr = Cpsr;
 701     if (cpsr.mode == MODE_USER) {
 702         if (FullSystem)
 703             return new UndefinedInstruction;
 704         else
 705             return new UndefinedInstruction(false, mnemonic);
 706     }
 707     MiscDest = Op1;
 708     '''
 709     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
 710                              { "code": mcr15code,
 711                                "predicate_test": predicateTest },
 712                                ["IsSerializeAfter","IsNonSpeculative"])
 713     header_output += RegRegOpDeclare.subst(mcr15Iop)
 714     decoder_output += RegRegOpConstructor.subst(mcr15Iop)
 715     exec_output += PredOpExecute.subst(mcr15Iop)
 716
 717     mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp",
 718                                  { "code": "Dest = MiscOp1;",
 719                                    "predicate_test": predicateTest }, [])
 720     header_output += RegRegOpDeclare.subst(mrc15UserIop)
 721     decoder_output += RegRegOpConstructor.subst(mrc15UserIop)
 722     exec_output += PredOpExecute.subst(mrc15UserIop)
 723
 724     mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
 725                                  { "code": "MiscDest = Op1",
 726                                    "predicate_test": predicateTest },
 727                                    ["IsSerializeAfter","IsNonSpeculative"])
 728     header_output += RegRegOpDeclare.subst(mcr15UserIop)
 729     decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
 730     exec_output += PredOpExecute.subst(mcr15UserIop)
 731
 732     enterxCode = '''
 733         NextThumb = true;
 734         NextJazelle = true;
 735     '''
 736     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
 737                               { "code": enterxCode,
 738                                 "predicate_test": predicateTest }, [])
 739     header_output += BasicDeclare.subst(enterxIop)
 740     decoder_output += BasicConstructor.subst(enterxIop)
 741     exec_output += PredOpExecute.subst(enterxIop)
 742
 743     leavexCode = '''
 744         NextThumb = true;
 745         NextJazelle = false;
 746     '''
 747     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
 748                               { "code": leavexCode,
 749                                 "predicate_test": predicateTest }, [])
 750     header_output += BasicDeclare.subst(leavexIop)
 751     decoder_output += BasicConstructor.subst(leavexIop)
 752     exec_output += PredOpExecute.subst(leavexIop)
 753
 754     setendCode = '''
 755         CPSR cpsr = Cpsr;
 756         cpsr.e = imm;
 757         Cpsr = cpsr;
 758     '''
 759     setendIop = InstObjParams("setend", "Setend", "ImmOp",
 760                               { "code": setendCode,
 761                                 "predicate_test": predicateTest },
 762                               ["IsSerializeAfter","IsNonSpeculative"])
 763     header_output += ImmOpDeclare.subst(setendIop)
 764     decoder_output += ImmOpConstructor.subst(setendIop)
 765     exec_output += PredOpExecute.subst(setendIop)
 766
 767     clrexCode = '''
 768         LLSCLock = 0;
 769     '''
 770     clrexIop = InstObjParams("clrex", "Clrex","PredOp",
 771                              { "code": clrexCode,
 772                                "predicate_test": predicateTest },[])
 773     header_output += BasicDeclare.subst(clrexIop)
 774     decoder_output += BasicConstructor.subst(clrexIop)
 775     exec_output += PredOpExecute.subst(clrexIop)
 776
 777     isbCode = '''
 778         fault = new FlushPipe;
 779     '''
 780     isbIop = InstObjParams("isb", "Isb", "PredOp",
 781                              {"code": isbCode,
 782                                "predicate_test": predicateTest},
 783                                 ['IsSerializeAfter'])
 784     header_output += BasicDeclare.subst(isbIop)
 785     decoder_output += BasicConstructor.subst(isbIop)
 786     exec_output += PredOpExecute.subst(isbIop)
 787
 788     dsbCode = '''
 789         fault = new FlushPipe;
 790     '''
 791     dsbIop = InstObjParams("dsb", "Dsb", "PredOp",
 792                              {"code": dsbCode,
 793                                "predicate_test": predicateTest},
 794                               ['IsMemBarrier', 'IsSerializeAfter'])
 795     header_output += BasicDeclare.subst(dsbIop)
 796     decoder_output += BasicConstructor.subst(dsbIop)
 797     exec_output += PredOpExecute.subst(dsbIop)
 798
 799     dmbCode = '''
 800     '''
 801     dmbIop = InstObjParams("dmb", "Dmb", "PredOp",
 802                              {"code": dmbCode,
 803                                "predicate_test": predicateTest},
 804                                ['IsMemBarrier'])
 805     header_output += BasicDeclare.subst(dmbIop)
 806     decoder_output += BasicConstructor.subst(dmbIop)
 807     exec_output += PredOpExecute.subst(dmbIop)
 808
 809     dbgCode = '''
 810     '''
 811     dbgIop = InstObjParams("dbg", "Dbg", "PredOp",
 812                              {"code": dbgCode,
 813                                "predicate_test": predicateTest})
 814     header_output += BasicDeclare.subst(dbgIop)
 815     decoder_output += BasicConstructor.subst(dbgIop)
 816     exec_output += PredOpExecute.subst(dbgIop)
 817
 818     cpsCode = '''
 819     uint32_t mode = bits(imm, 4, 0);
 820     uint32_t f = bits(imm, 5);
 821     uint32_t i = bits(imm, 6);
 822     uint32_t a = bits(imm, 7);
 823     bool setMode = bits(imm, 8);
 824     bool enable = bits(imm, 9);
 825     CPSR cpsr = Cpsr;
 826     SCTLR sctlr = Sctlr;
 827     if (cpsr.mode != MODE_USER) {
 828         if (enable) {
 829             if (f) cpsr.f = 0;
 830             if (i) cpsr.i = 0;
 831             if (a) cpsr.a = 0;
 832         } else {
 833             if (f && !sctlr.nmfi) cpsr.f = 1;
 834             if (i) cpsr.i = 1;
 835             if (a) cpsr.a = 1;
 836         }
 837         if (setMode) {
 838             cpsr.mode = mode;
 839         }
 840     }
 841     Cpsr = cpsr;
 842     '''
 843     cpsIop = InstObjParams("cps", "Cps", "ImmOp",
 844                            { "code": cpsCode,
 845                              "predicate_test": predicateTest },
 846                            ["IsSerializeAfter","IsNonSpeculative"])
 847     header_output += ImmOpDeclare.subst(cpsIop)
 848     decoder_output += ImmOpConstructor.subst(cpsIop)
 849     exec_output += PredOpExecute.subst(cpsIop)
 850 }};