src/arch/arm/isa/insts/misc64.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2011-2013, 2016-2018 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
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  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37
  38 let {{
  39     svcCode = '''
  40     fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
  41     '''
  42
  43     svcIop = InstObjParams("svc", "Svc64", "ImmOp64",
  44                            svcCode, ["IsSyscall", "IsNonSpeculative",
  45                                      "IsSerializeAfter"])
  46     header_output = ImmOp64Declare.subst(svcIop)
  47     decoder_output = ImmOp64Constructor.subst(svcIop)
  48     exec_output = BasicExecute.subst(svcIop)
  49
  50     hvcCode = '''
  51     SCR scr = Scr64;
  52     HCR hcr = Hcr64;
  53     CPSR cpsr = Cpsr;
  54
  55     auto tc = xc->tcBase();
  56     ExceptionLevel pstate_EL = (ExceptionLevel)(uint8_t)(cpsr.el);
  57
  58     bool unalloc_encod = !ArmSystem::haveEL(tc, EL2) || pstate_EL == EL0 ||
  59                          (pstate_EL == EL1 && inSecureState(tc));
  60
  61     bool hvc_enable = ArmSystem::haveEL(tc, EL3) ?
  62         scr.hce : !hcr.hcd;
  63
  64     if (unalloc_encod || !hvc_enable) {
  65         fault = undefinedFault64(tc, pstate_EL);
  66     } else {
  67         fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5));
  68     }
  69     '''
  70
  71     hvcIop = InstObjParams("hvc", "Hvc64", "ImmOp64",
  72                            hvcCode, ["IsSyscall", "IsNonSpeculative",
  73                                      "IsSerializeAfter"])
  74     header_output += ImmOp64Declare.subst(hvcIop)
  75     decoder_output += ImmOp64Constructor.subst(hvcIop)
  76     exec_output += BasicExecute.subst(hvcIop)
  77
  78     # @todo: extend to take into account Virtualization.
  79     smcCode = '''
  80     SCR scr = Scr64;
  81     CPSR cpsr = Cpsr;
  82
  83     if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) {
  84         fault = disabledFault();
  85     } else {
  86         fault = std::make_shared<SecureMonitorCall>(machInst);
  87     }
  88     '''
  89
  90     smcIop = InstObjParams("smc", "Smc64", "ImmOp64",
  91                            smcCode, ["IsNonSpeculative", "IsSerializeAfter"])
  92     header_output += ImmOp64Declare.subst(smcIop)
  93     decoder_output += ImmOp64Constructor.subst(smcIop)
  94     exec_output += BasicExecute.subst(smcIop)
  95
  96     def subst(templateBase, iop):
  97         global header_output, decoder_output, exec_output
  98         header_output += eval(templateBase + "Declare").subst(iop)
  99         decoder_output += eval(templateBase + "Constructor").subst(iop)
 100         exec_output += BasicExecute.subst(iop)
 101
 102     bfmMaskCode = '''
 103     uint64_t bitMask;
 104     int diff = imm2 - imm1;
 105     if (imm1 <= imm2) {
 106         bitMask = mask(diff + 1);
 107     } else {
 108         bitMask = mask(imm2 + 1);
 109         bitMask = (bitMask >> imm1) | (bitMask << (intWidth - imm1));
 110         diff += intWidth;
 111     }
 112     uint64_t topBits M5_VAR_USED = ~mask(diff+1);
 113     uint64_t result = imm1 == 0 ? Op164 :
 114                       (Op164 >> imm1) | (Op164 << (intWidth - imm1));
 115     result &= bitMask;
 116     '''
 117
 118     bfmCode = bfmMaskCode + 'Dest64 = result | (Dest64 & ~bitMask);'
 119     bfmIop = InstObjParams("bfm", "Bfm64", "RegRegImmImmOp64", bfmCode);
 120     subst("RegRegImmImmOp64", bfmIop)
 121
 122     ubfmCode = bfmMaskCode + 'Dest64 = result;'
 123     ubfmIop = InstObjParams("ubfm", "Ubfm64", "RegRegImmImmOp64", ubfmCode);
 124     subst("RegRegImmImmOp64", ubfmIop)
 125
 126     sbfmCode = bfmMaskCode + \
 127         'Dest64 = result | (bits(Op164, imm2) ? topBits : 0);'
 128     sbfmIop = InstObjParams("sbfm", "Sbfm64", "RegRegImmImmOp64", sbfmCode);
 129     subst("RegRegImmImmOp64", sbfmIop)
 130
 131     extrCode = '''
 132         if (imm == 0) {
 133             Dest64 = Op264;
 134         } else {
 135             Dest64 = (Op164 << (intWidth - imm)) | (Op264 >> imm);
 136         }
 137     '''
 138     extrIop = InstObjParams("extr", "Extr64", "RegRegRegImmOp64", extrCode);
 139     subst("RegRegRegImmOp64", extrIop);
 140
 141     unknownCode = '''
 142             return std::make_shared<UndefinedInstruction>(machInst, true);
 143     '''
 144     unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64",
 145                                  unknownCode)
 146     header_output += BasicDeclare.subst(unknown64Iop)
 147     decoder_output += BasicConstructor64.subst(unknown64Iop)
 148     exec_output += BasicExecute.subst(unknown64Iop)
 149
 150     isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", "",
 151                            ['IsSquashAfter'])
 152     header_output += BasicDeclare.subst(isbIop)
 153     decoder_output += BasicConstructor64.subst(isbIop)
 154     exec_output += BasicExecute.subst(isbIop)
 155
 156     dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
 157                            ['IsMemBarrier', 'IsSerializeAfter'])
 158     header_output += BasicDeclare.subst(dsbIop)
 159     decoder_output += BasicConstructor64.subst(dsbIop)
 160     exec_output += BasicExecute.subst(dsbIop)
 161
 162     dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
 163                            ['IsMemBarrier'])
 164     header_output += BasicDeclare.subst(dmbIop)
 165     decoder_output += BasicConstructor64.subst(dmbIop)
 166     exec_output += BasicExecute.subst(dmbIop)
 167
 168     clrexIop = InstObjParams("clrex", "Clrex64", "ArmStaticInst",
 169                              "LLSCLock = 0;")
 170     header_output += BasicDeclare.subst(clrexIop)
 171     decoder_output += BasicConstructor64.subst(clrexIop)
 172     exec_output += BasicExecute.subst(clrexIop)
 173
 174
 175     brkCode = '''
 176     fault = std::make_shared<SoftwareBreakpoint>(machInst,
 177                                                  bits(machInst, 20, 5));
 178     '''
 179
 180     brkIop = InstObjParams("brk", "Brk64", "ImmOp64",
 181                            brkCode, ["IsSerializeAfter"])
 182     header_output += ImmOp64Declare.subst(brkIop)
 183     decoder_output += ImmOp64Constructor.subst(brkIop)
 184     exec_output += BasicExecute.subst(brkIop)
 185
 186     hltCode = '''
 187     ThreadContext *tc = xc->tcBase();
 188     if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) {
 189         X0 = ArmSystem::callSemihosting64(tc, X0 & mask(32), X1);
 190     } else {
 191         // HLT instructions aren't implemented, so treat them as undefined
 192         // instructions.
 193         fault = std::make_shared<UndefinedInstruction>(
 194             machInst, false, mnemonic);
 195     }
 196
 197     '''
 198
 199     hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64",
 200                            hltCode, ["IsNonSpeculative"])
 201     header_output += ImmOp64Declare.subst(hltIop)
 202     decoder_output += SemihostConstructor64.subst(hltIop)
 203     exec_output += BasicExecute.subst(hltIop)
 204 }};