src/arch/arm/isa/operands.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007-2008 The Florida State University
   4 // All rights reserved.
   5 //
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   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
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  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  28 //
  29 // Authors: Stephen Hines
  30
  31 def operand_types {{
  32     'sb' : ('signed int', 8),
  33     'ub' : ('unsigned int', 8),
  34     'sh' : ('signed int', 16),
  35     'uh' : ('unsigned int', 16),
  36     'sw' : ('signed int', 32),
  37     'uw' : ('unsigned int', 32),
  38     'ud' : ('unsigned int', 64),
  39     'sf' : ('float', 32),
  40     'df' : ('float', 64)
  41 }};
  42
  43 def operands {{
  44     #General Purpose Integer Reg Operands
  45     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
  46     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
  47     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
  48     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
  49     'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5),
  50
  51     'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
  52     'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
  53     'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
  54     'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
  55     'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
  56     'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
  57     'Ignore': ('IntReg', 'uw', '16', 'IsInteger', 99),
  58
  59     #General Purpose Floating Point Reg Operands
  60     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
  61     'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
  62     'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
  63
  64     #Memory Operand
  65     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
  66
  67     'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
  68     'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
  69     'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
  70     'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
  71
  72 }};