src/arch/arm/isa/operands.isa

   1 // -*- mode:c++ -*-
   2 // Copyright (c) 2010 ARM Limited
   3 // All rights reserved
   4 //
   5 // The license below extends only to copyright in the software and shall
   6 // not be construed as granting a license to any other intellectual
   7 // property including but not limited to intellectual property relating
   8 // to a hardware implementation of the functionality of the software
   9 // licensed hereunder.  You may use the software subject to the license
  10 // terms below provided that you ensure that this notice is replicated
  11 // unmodified and in its entirety in all distributions of the software,
  12 // modified or unmodified, in source code or in binary form.
  13 //
  14 // Copyright (c) 2007-2008 The Florida State University
  15 // All rights reserved.
  16 //
  17 // Redistribution and use in source and binary forms, with or without
  18 // modification, are permitted provided that the following conditions are
  19 // met: redistributions of source code must retain the above copyright
  20 // notice, this list of conditions and the following disclaimer;
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  22 // notice, this list of conditions and the following disclaimer in the
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  26 // this software without specific prior written permission.
  27 //
  28 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  31 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  38 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 //
  40 // Authors: Stephen Hines
  41
  42 def operand_types {{
  43     'sb' : ('signed int', 8),
  44     'ub' : ('unsigned int', 8),
  45     'sh' : ('signed int', 16),
  46     'uh' : ('unsigned int', 16),
  47     'sw' : ('signed int', 32),
  48     'uw' : ('unsigned int', 32),
  49     'ud' : ('unsigned int', 64),
  50     'sf' : ('float', 32),
  51     'df' : ('float', 64)
  52 }};
  53
  54 let {{
  55     maybePCRead = '''
  56         ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
  57          xc->%(func)s(this, %(op_idx)s))
  58     '''
  59     maybeAlignedPCRead = '''
  60         ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
  61          xc->%(func)s(this, %(op_idx)s))
  62     '''
  63     maybePCWrite = '''
  64         ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
  65          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
  66     '''
  67     maybeIWPCWrite = '''
  68         ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
  69          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
  70     '''
  71     maybeAIWPCWrite = '''
  72         if (%(reg_idx)s == PCReg) {
  73             bool thumb = THUMB;
  74             if (thumb) {
  75                 setNextPC(xc, %(final_val)s);
  76             } else {
  77                 setIWNextPC(xc, %(final_val)s);
  78             }
  79         } else {
  80             xc->%(func)s(this, %(op_idx)s, %(final_val)s);
  81         }
  82     '''
  83
  84     readNPC = 'xc->readNextPC() & ~PcModeMask'
  85     writeNPC = 'setNextPC(xc, %(final_val)s)'
  86     writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
  87     forceNPC = 'xc->setNextPC(%(final_val)s)'
  88 }};
  89
  90 def operands {{
  91     #Abstracted integer reg operands
  92     'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
  93              maybePCRead, maybePCWrite),
  94     'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
  95     'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
  96     'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
  97     'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
  98     'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
  99     'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
 100                maybePCRead, maybePCWrite),
 101     'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
 102               maybePCRead, maybePCWrite),
 103     'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
 104     'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
 105     'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
 106     'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
 107     'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
 108     'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
 109                maybePCRead, maybeIWPCWrite),
 110     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
 111                 maybePCRead, maybeAIWPCWrite),
 112     'SpMode': ('IntReg', 'uw',
 113                'intRegInMode((OperatingMode)regMode, INTREG_SP)',
 114                'IsInteger', 2),
 115     'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
 116     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
 117              maybeAlignedPCRead, maybePCWrite),
 118     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
 119               maybePCRead, maybePCWrite),
 120     'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
 121               maybePCRead, maybePCWrite),
 122     'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
 123     'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
 124     'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
 125     'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
 126     'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
 127     'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
 128     'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
 129               maybePCRead, maybePCWrite),
 130     'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
 131     'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
 132     'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
 133     'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
 134     'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
 135     'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
 136               maybePCRead, maybePCWrite),
 137     'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
 138               maybePCRead, maybePCWrite),
 139     'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
 140               maybePCRead, maybePCWrite),
 141     'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
 142               maybePCRead, maybePCWrite),
 143     'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
 144               maybePCRead, maybePCWrite),
 145     'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
 146               maybePCRead, maybePCWrite),
 147     #General Purpose Integer Reg Operands
 148     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
 149     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
 150     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
 151     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
 152     'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
 153     'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
 154
 155     'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
 156     'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
 157
 158     #Register fields for microops
 159     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
 160     'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
 161             maybePCRead, maybeIWPCWrite),
 162     'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
 163     'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
 164
 165     #General Purpose Floating Point Reg Operands
 166     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
 167     'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
 168     'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
 169
 170     #Memory Operand
 171     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
 172
 173     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
 174     'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
 175     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
 176     'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
 177     'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
 178     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
 179     'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
 180     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
 181             readNPC, writeNPC),
 182     'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
 183              readNPC, forceNPC),
 184     'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
 185               readNPC, writeIWNPC),
 186 }};