src/arch/arm/isa/operands.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2007-2008 The Florida State University
   4 // All rights reserved.
   5 //
   6 // Redistribution and use in source and binary forms, with or without
   7 // modification, are permitted provided that the following conditions are
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   9 // notice, this list of conditions and the following disclaimer;
  10 // redistributions in binary form must reproduce the above copyright
  11 // notice, this list of conditions and the following disclaimer in the
  12 // documentation and/or other materials provided with the distribution;
  13 // neither the name of the copyright holders nor the names of its
  14 // contributors may be used to endorse or promote products derived from
  15 // this software without specific prior written permission.
  16 //
  17 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  21 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  24 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  27 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 //
  29 // Authors: Stephen Hines
  30
  31 def operand_types {{
  32     'sb' : ('signed int', 8),
  33     'ub' : ('unsigned int', 8),
  34     'sh' : ('signed int', 16),
  35     'uh' : ('unsigned int', 16),
  36     'sw' : ('signed int', 32),
  37     'uw' : ('unsigned int', 32),
  38     'ud' : ('unsigned int', 64),
  39     'sf' : ('float', 32),
  40     'df' : ('float', 64)
  41 }};
  42
  43 let {{
  44     maybePCRead = '''
  45         ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
  46          xc->%(func)s(this, %(op_idx)s))
  47     '''
  48     maybePCWrite = '''
  49         ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
  50          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
  51     '''
  52 }};
  53
  54 def operands {{
  55     #General Purpose Integer Reg Operands
  56     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
  57     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
  58     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
  59     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
  60     'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
  61
  62     #Destination register for load/store double instructions
  63     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
  64     'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
  65
  66     'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
  67     'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
  68     'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
  69     'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
  70
  71     #Register fields for microops
  72     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
  73     'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
  74
  75     #General Purpose Floating Point Reg Operands
  76     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
  77     'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
  78     'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
  79
  80     #Memory Operand
  81     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
  82
  83     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
  84     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
  85     'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
  86     'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
  87     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
  88     'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
  89     'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
  90
  91 }};