src/arch/arm/isa/operands.isa

   1 // -*- mode:c++ -*-
   2 // Copyright (c) 2010 ARM Limited
   3 // All rights reserved
   4 //
   5 // The license below extends only to copyright in the software and shall
   6 // not be construed as granting a license to any other intellectual
   7 // property including but not limited to intellectual property relating
   8 // to a hardware implementation of the functionality of the software
   9 // licensed hereunder.  You may use the software subject to the license
  10 // terms below provided that you ensure that this notice is replicated
  11 // unmodified and in its entirety in all distributions of the software,
  12 // modified or unmodified, in source code or in binary form.
  13 //
  14 // Copyright (c) 2007-2008 The Florida State University
  15 // All rights reserved.
  16 //
  17 // Redistribution and use in source and binary forms, with or without
  18 // modification, are permitted provided that the following conditions are
  19 // met: redistributions of source code must retain the above copyright
  20 // notice, this list of conditions and the following disclaimer;
  21 // redistributions in binary form must reproduce the above copyright
  22 // notice, this list of conditions and the following disclaimer in the
  23 // documentation and/or other materials provided with the distribution;
  24 // neither the name of the copyright holders nor the names of its
  25 // contributors may be used to endorse or promote products derived from
  26 // this software without specific prior written permission.
  27 //
  28 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  31 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  38 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 //
  40 // Authors: Stephen Hines
  41
  42 def operand_types {{
  43     'sb' : ('signed int', 8),
  44     'ub' : ('unsigned int', 8),
  45     'sh' : ('signed int', 16),
  46     'uh' : ('unsigned int', 16),
  47     'sw' : ('signed int', 32),
  48     'uw' : ('unsigned int', 32),
  49     'ud' : ('unsigned int', 64),
  50     'sf' : ('float', 32),
  51     'df' : ('float', 64)
  52 }};
  53
  54 let {{
  55     maybePCRead = '''
  56         ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
  57          xc->%(func)s(this, %(op_idx)s))
  58     '''
  59     maybePCWrite = '''
  60         ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
  61          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
  62     '''
  63     maybeIWPCWrite = '''
  64         ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
  65          xc->%(func)s(this, %(op_idx)s, %(final_val)s))
  66     '''
  67     maybeAIWPCWrite = '''
  68         if (%(reg_idx)s == PCReg) {
  69             if (xc->readPC() & (ULL(1) << PcTBitShift)) {
  70                 setIWNextPC(xc, %(final_val)s);
  71             } else {
  72                 setNextPC(xc, %(final_val)s);
  73             }
  74         } else {
  75             xc->%(func)s(this, %(op_idx)s, %(final_val)s);
  76         }
  77     '''
  78
  79     readNPC = 'xc->readNextPC() & ~PcModeMask'
  80     writeNPC = 'setNextPC(xc, %(final_val)s)'
  81     writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
  82     forceNPC = 'xc->setNextPC(%(final_val)s)'
  83 }};
  84
  85 def operands {{
  86     #Abstracted integer reg operands
  87     'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
  88              maybePCRead, maybePCWrite),
  89     'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
  90                maybePCRead, maybeIWPCWrite),
  91     'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
  92                 maybePCRead, maybeAIWPCWrite),
  93     'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
  94              maybePCRead, maybePCWrite),
  95     'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
  96               maybePCRead, maybePCWrite),
  97     'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
  98               maybePCRead, maybePCWrite),
  99     'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
 100               maybePCRead, maybePCWrite),
 101     'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
 102               maybePCRead, maybePCWrite),
 103     'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
 104               maybePCRead, maybePCWrite),
 105     'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7,
 106               maybePCRead, maybePCWrite),
 107     'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8,
 108               maybePCRead, maybePCWrite),
 109     'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9,
 110               maybePCRead, maybePCWrite),
 111     #General Purpose Integer Reg Operands
 112     'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
 113     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
 114     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
 115     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
 116     'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
 117     'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
 118
 119     #Destination register for load/store double instructions
 120     'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
 121     'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
 122
 123     'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
 124     'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
 125
 126     #Register fields for microops
 127     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
 128     'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
 129     'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
 130
 131     #General Purpose Floating Point Reg Operands
 132     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
 133     'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
 134     'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
 135
 136     #Memory Operand
 137     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
 138
 139     'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
 140     'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
 141     'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
 142     'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
 143     'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
 144     'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
 145     'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
 146             readNPC, writeNPC),
 147     'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
 148              readNPC, forceNPC),
 149     'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
 150               readNPC, writeIWNPC),
 151 }};