src/arch/arm/isa/templates/macromem.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010-2014 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Copyright (c) 2007-2008 The Florida State University
  16 // All rights reserved.
  17 //
  18 // Redistribution and use in source and binary forms, with or without
  19 // modification, are permitted provided that the following conditions are
  20 // met: redistributions of source code must retain the above copyright
  21 // notice, this list of conditions and the following disclaimer;
  22 // redistributions in binary form must reproduce the above copyright
  23 // notice, this list of conditions and the following disclaimer in the
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  25 // neither the name of the copyright holders nor the names of its
  26 // contributors may be used to endorse or promote products derived from
  27 // this software without specific prior written permission.
  28 //
  29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 ////////////////////////////////////////////////////////////////////
  42 //
  43 // Load/store microops
  44 //
  45
  46 def template MicroMemDeclare {{
  47     class %(class_name)s : public %(base_class)s
  48     {
  49       public:
  50         %(class_name)s(ExtMachInst machInst,
  51                        RegIndex _ura, RegIndex _urb, bool _up,
  52                        uint8_t _imm);
  53         Fault execute(ExecContext *, Trace::InstRecord *) const override;
  54         Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
  55         Fault completeAcc(PacketPtr, ExecContext *,
  56                           Trace::InstRecord *) const override;
  57     };
  58 }};
  59
  60 def template MicroMemConstructor {{
  61     %(class_name)s::%(class_name)s(ExtMachInst machInst,
  62                                    RegIndex _ura,
  63                                    RegIndex _urb,
  64                                    bool _up,
  65                                    uint8_t _imm)
  66         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
  67                          _ura, _urb, _up, _imm)
  68     {
  69         %(constructor)s;
  70         if (!(condCode == COND_AL || condCode == COND_UC)) {
  71             for (int x = 0; x < _numDestRegs; x++) {
  72                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
  73             }
  74         }
  75     }
  76 }};
  77
  78
  79 def template MicroMemPairDeclare {{
  80     class %(class_name)s : public %(base_class)s
  81     {
  82       public:
  83         %(class_name)s(ExtMachInst machInst,
  84                        RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
  85                        bool _up, uint8_t _imm);
  86         Fault execute(ExecContext *, Trace::InstRecord *) const override;
  87         Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
  88         Fault completeAcc(PacketPtr, ExecContext *,
  89                           Trace::InstRecord *) const override;
  90     };
  91 }};
  92
  93 def template MicroMemPairConstructor {{
  94     %(class_name)s::%(class_name)s(ExtMachInst machInst,
  95                                    RegIndex _dreg1,
  96                                    RegIndex _dreg2,
  97                                    RegIndex _base,
  98                                    bool _up,
  99                                    uint8_t _imm)
 100         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 101                          _dreg1, _dreg2, _base, _up, _imm)
 102     {
 103         %(constructor)s;
 104         if (!(condCode == COND_AL || condCode == COND_UC)) {
 105             for (int x = 0; x < _numDestRegs; x++) {
 106                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 107             }
 108         }
 109     }
 110 }};
 111
 112 ////////////////////////////////////////////////////////////////////
 113 //
 114 // Neon load/store microops
 115 //
 116
 117 def template MicroNeonMemDeclare {{
 118     template <class Element>
 119     class %(class_name)s : public %(base_class)s
 120     {
 121       public:
 122         %(class_name)s(ExtMachInst machInst, RegIndex _dest,
 123                        RegIndex _ura, uint32_t _imm, unsigned extraMemFlags)
 124             : %(base_class)s("%(mnemonic)s", machInst,
 125                               %(op_class)s, _dest, _ura, _imm)
 126         {
 127             memAccessFlags |= extraMemFlags;
 128             %(constructor)s;
 129             if (!(condCode == COND_AL || condCode == COND_UC)) {
 130                 for (int x = 0; x < _numDestRegs; x++) {
 131                     setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 132                 }
 133             }
 134         }
 135
 136         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 137         Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
 138         Fault completeAcc(PacketPtr, ExecContext *,
 139                           Trace::InstRecord *) const override;
 140     };
 141 }};
 142
 143 ////////////////////////////////////////////////////////////////////
 144 //
 145 // PC   = Integer(ura)
 146 // CPSR = Integer(urb)
 147 //
 148
 149 def template MicroSetPCCPSRDeclare {{
 150     class %(class_name)s : public %(base_class)s
 151     {
 152       public:
 153         %(class_name)s(ExtMachInst machInst,
 154                        IntRegIndex _ura,
 155                        IntRegIndex _urb,
 156                        IntRegIndex _urc);
 157         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 158     };
 159 }};
 160
 161 def template MicroSetPCCPSRConstructor {{
 162     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 163                                    IntRegIndex _ura,
 164                                    IntRegIndex _urb,
 165                                    IntRegIndex _urc)
 166           : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 167                            _ura, _urb, _urc)
 168     {
 169         %(constructor)s;
 170         if (!(condCode == COND_AL || condCode == COND_UC)) {
 171             flags[IsCondControl] = true;
 172             for (int x = 0; x < _numDestRegs; x++) {
 173                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 174             }
 175         } else {
 176             flags[IsUncondControl] = true;
 177         }
 178     }
 179 }};
 180
 181 ////////////////////////////////////////////////////////////////////
 182 //
 183 // Integer = Integer op Integer microops
 184 //
 185
 186 def template MicroNeonMemExecDeclare {{
 187     template
 188     Fault %(class_name)s<%(targs)s>::execute(
 189             ExecContext *, Trace::InstRecord *) const;
 190     template
 191     Fault %(class_name)s<%(targs)s>::initiateAcc(
 192             ExecContext *, Trace::InstRecord *) const;
 193     template
 194     Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
 195             ExecContext *, Trace::InstRecord *) const;
 196 }};
 197
 198 def template MicroNeonExecDeclare {{
 199     template
 200     Fault %(class_name)s<%(targs)s>::execute(
 201             ExecContext *, Trace::InstRecord *) const;
 202 }};
 203
 204 ////////////////////////////////////////////////////////////////////
 205 //
 206 // Neon (de)interlacing microops
 207 //
 208
 209 def template MicroNeonMixDeclare {{
 210     template <class Element>
 211     class %(class_name)s : public %(base_class)s
 212     {
 213       public:
 214         %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
 215                        uint8_t _step) :
 216             %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 217                            _dest, _op1, _step)
 218         {
 219             %(constructor)s;
 220             if (!(condCode == COND_AL || condCode == COND_UC)) {
 221                 for (int x = 0; x < _numDestRegs; x++) {
 222                     setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 223                 }
 224             }
 225         }
 226
 227         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 228     };
 229 }};
 230
 231 def template MicroNeonMixExecute {{
 232     template <class Element>
 233     Fault %(class_name)s<Element>::execute(ExecContext *xc,
 234             Trace::InstRecord *traceData) const
 235     {
 236         Fault fault = NoFault;
 237         uint64_t resTemp = 0;
 238         resTemp = resTemp;
 239         %(op_decl)s;
 240         %(op_rd)s;
 241
 242         if (%(predicate_test)s)
 243         {
 244             %(code)s;
 245             if (fault == NoFault)
 246             {
 247                 %(op_wb)s;
 248             }
 249         } else {
 250             xc->setPredicate(false);
 251         }
 252
 253         return fault;
 254     }
 255 }};
 256
 257 ////////////////////////////////////////////////////////////////////
 258 //
 259 // Neon (un)packing microops using a particular lane
 260 //
 261
 262 def template MicroNeonMixLaneDeclare {{
 263     template <class Element>
 264     class %(class_name)s : public %(base_class)s
 265     {
 266       public:
 267         %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
 268                        uint8_t _step, unsigned _lane) :
 269             %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 270                            _dest, _op1, _step, _lane)
 271         {
 272             %(constructor)s;
 273             if (!(condCode == COND_AL || condCode == COND_UC)) {
 274                 for (int x = 0; x < _numDestRegs; x++) {
 275                     setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 276                 }
 277             }
 278         }
 279
 280         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 281     };
 282 }};
 283
 284 ////////////////////////////////////////////////////////////////////
 285 //
 286 // Integer = Integer
 287 //
 288
 289 def template MicroIntMovDeclare {{
 290     class %(class_name)s : public %(base_class)s
 291     {
 292       public:
 293         %(class_name)s(ExtMachInst machInst,
 294                        RegIndex _ura, RegIndex _urb);
 295         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 296     };
 297 }};
 298 def template MicroIntMovConstructor {{
 299     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 300                                    RegIndex _ura,
 301                                    RegIndex _urb)
 302         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 303                          _ura, _urb)
 304     {
 305         %(constructor)s;
 306         if (!(condCode == COND_AL || condCode == COND_UC)) {
 307             for (int x = 0; x < _numDestRegs; x++) {
 308                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 309             }
 310         }
 311     }
 312 }};
 313
 314 ////////////////////////////////////////////////////////////////////
 315 //
 316 // Integer = Integer op Immediate microops
 317 //
 318
 319 def template MicroIntImmDeclare {{
 320     class %(class_name)s : public %(base_class)s
 321     {
 322       public:
 323         %(class_name)s(ExtMachInst machInst,
 324                        RegIndex _ura, RegIndex _urb,
 325                        int32_t _imm);
 326         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 327     };
 328 }};
 329
 330 def template MicroIntImmConstructor {{
 331     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 332                                    RegIndex _ura,
 333                                    RegIndex _urb,
 334                                    int32_t _imm)
 335         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 336                          _ura, _urb, _imm)
 337     {
 338         %(constructor)s;
 339         if (!(condCode == COND_AL || condCode == COND_UC)) {
 340             for (int x = 0; x < _numDestRegs; x++) {
 341                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 342             }
 343         }
 344     }
 345 }};
 346
 347 def template MicroIntImmXConstructor {{
 348     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 349                                    RegIndex _ura,
 350                                    RegIndex _urb,
 351                                    int32_t _imm)
 352         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 353                          _ura, _urb, _imm)
 354     {
 355         %(constructor)s;
 356     }
 357 }};
 358
 359 def template MicroIntRegDeclare {{
 360     class %(class_name)s : public %(base_class)s
 361     {
 362       public:
 363         %(class_name)s(ExtMachInst machInst,
 364                        RegIndex _ura, RegIndex _urb, RegIndex _urc,
 365                        int32_t _shiftAmt, ArmShiftType _shiftType);
 366         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 367     };
 368 }};
 369
 370 def template MicroIntXERegConstructor {{
 371     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 372                                    RegIndex _ura, RegIndex _urb, RegIndex _urc,
 373                                    ArmExtendType _type, uint32_t _shiftAmt)
 374         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 375                          _ura, _urb, _urc, _type, _shiftAmt)
 376     {
 377         %(constructor)s;
 378     }
 379 }};
 380
 381 def template MicroIntXERegDeclare {{
 382     class %(class_name)s : public %(base_class)s
 383     {
 384       public:
 385         %(class_name)s(ExtMachInst machInst,
 386                        RegIndex _ura, RegIndex _urb, RegIndex _urc,
 387                        ArmExtendType _type, uint32_t _shiftAmt);
 388         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 389     };
 390 }};
 391
 392 def template MicroIntRegConstructor {{
 393     %(class_name)s::%(class_name)s(ExtMachInst machInst,
 394                                    RegIndex _ura, RegIndex _urb, RegIndex _urc,
 395                                    int32_t _shiftAmt, ArmShiftType _shiftType)
 396         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 397                          _ura, _urb, _urc, _shiftAmt, _shiftType)
 398     {
 399         %(constructor)s;
 400         if (!(condCode == COND_AL || condCode == COND_UC)) {
 401             for (int x = 0; x < _numDestRegs; x++) {
 402                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 403             }
 404         }
 405     }
 406 }};
 407
 408 ////////////////////////////////////////////////////////////////////
 409 //
 410 // Macro Memory-format instructions
 411 //
 412
 413 def template MacroMemDeclare {{
 414 /**
 415  * Static instructions class for a store multiple instruction
 416  */
 417 class %(class_name)s : public %(base_class)s
 418 {
 419     public:
 420         // Constructor
 421         %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
 422                 bool index, bool up, bool user, bool writeback, bool load,
 423                 uint32_t reglist);
 424 };
 425 }};
 426
 427 def template MacroMemConstructor {{
 428 %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
 429         bool index, bool up, bool user, bool writeback, bool load,
 430         uint32_t reglist)
 431     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
 432                      index, up, user, writeback, load, reglist)
 433 {
 434     %(constructor)s;
 435     if (!(condCode == COND_AL || condCode == COND_UC)) {
 436         for (int x = 0; x < _numDestRegs; x++) {
 437             setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 438         }
 439     }
 440 }
 441
 442 }};
 443
 444 def template BigFpMemImmDeclare {{
 445 class %(class_name)s : public %(base_class)s
 446 {
 447   public:
 448     // Constructor
 449     %(class_name)s(const char *mnemonic, ExtMachInst machInst,
 450                    bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
 451 };
 452 }};
 453
 454 def template BigFpMemImmConstructor {{
 455 %(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
 456         bool load, IntRegIndex dest, IntRegIndex base, int64_t imm)
 457     : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm)
 458 {
 459     %(constructor)s;
 460 }
 461 }};
 462
 463 def template BigFpMemRegDeclare {{
 464 class %(class_name)s : public %(base_class)s
 465 {
 466   public:
 467     // Constructor
 468     %(class_name)s(const char *mnemonic, ExtMachInst machInst,
 469                    bool load, IntRegIndex dest, IntRegIndex base,
 470                    IntRegIndex offset, ArmExtendType type, int64_t imm);
 471 };
 472 }};
 473
 474 def template BigFpMemRegConstructor {{
 475 %(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
 476         bool load, IntRegIndex dest, IntRegIndex base,
 477         IntRegIndex offset, ArmExtendType type, int64_t imm)
 478     : %(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base,
 479                      offset, type, imm)
 480 {
 481     %(constructor)s;
 482 }
 483 }};
 484
 485 def template BigFpMemLitDeclare {{
 486 class %(class_name)s : public %(base_class)s
 487 {
 488   public:
 489     // Constructor
 490     %(class_name)s(const char *mnemonic, ExtMachInst machInst,
 491                    IntRegIndex dest, int64_t imm);
 492 };
 493 }};
 494
 495 def template BigFpMemLitConstructor {{
 496 %(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
 497         IntRegIndex dest, int64_t imm)
 498     : %(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm)
 499 {
 500     %(constructor)s;
 501 }
 502 }};
 503
 504 def template PairMemDeclare {{
 505 class %(class_name)s : public %(base_class)s
 506 {
 507     public:
 508         // Constructor
 509         %(class_name)s(const char *mnemonic, ExtMachInst machInst,
 510                 uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
 511                 bool exclusive, bool acrel, uint32_t imm,
 512                 AddrMode mode, IntRegIndex rn, IntRegIndex rt,
 513                 IntRegIndex rt2);
 514 };
 515 }};
 516
 517 def template PairMemConstructor {{
 518 %(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
 519         uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
 520         bool exclusive, bool acrel, uint32_t imm, AddrMode mode,
 521         IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2)
 522     : %(base_class)s(mnemonic, machInst, %(op_class)s, size,
 523                      fp, load, noAlloc, signExt, exclusive, acrel,
 524                      imm, mode, rn, rt, rt2)
 525 {
 526     %(constructor)s;
 527 }
 528 }};
 529
 530 def template VMemMultDeclare {{
 531 class %(class_name)s : public %(base_class)s
 532 {
 533     public:
 534         // Constructor
 535         %(class_name)s(ExtMachInst machInst, unsigned width,
 536                 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
 537                 uint32_t size, uint32_t align, RegIndex rm);
 538 };
 539 }};
 540
 541 def template VMemMultConstructor {{
 542 %(class_name)s::%(class_name)s(ExtMachInst machInst, unsigned width,
 543         RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
 544         uint32_t size, uint32_t align, RegIndex rm)
 545     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, width,
 546                      rn, vd, regs, inc, size, align, rm)
 547 {
 548     %(constructor)s;
 549     if (!(condCode == COND_AL || condCode == COND_UC)) {
 550         for (int x = 0; x < _numDestRegs; x++) {
 551             setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 552         }
 553     }
 554 }
 555 }};
 556
 557 def template VMemSingleDeclare {{
 558 class %(class_name)s : public %(base_class)s
 559 {
 560     public:
 561         // Constructor
 562         %(class_name)s(ExtMachInst machInst, bool all, unsigned width,
 563                 RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
 564                 uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
 565 };
 566 }};
 567
 568 def template VMemSingleConstructor {{
 569 %(class_name)s::%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
 570         RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
 571         uint32_t size, uint32_t align, RegIndex rm, unsigned lane)
 572     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, all, width,
 573                      rn, vd, regs, inc, size, align, rm, lane)
 574 {
 575     %(constructor)s;
 576     if (!(condCode == COND_AL || condCode == COND_UC)) {
 577         for (int x = 0; x < _numDestRegs; x++) {
 578             setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 579         }
 580     }
 581 }
 582 }};
 583
 584 def template MacroVFPMemDeclare {{
 585 /**
 586  * Static instructions class for a store multiple instruction
 587  */
 588 class %(class_name)s : public %(base_class)s
 589 {
 590     public:
 591         // Constructor
 592         %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
 593                 RegIndex vd, bool single, bool up, bool writeback,
 594                 bool load, uint32_t offset);
 595 };
 596 }};
 597
 598 def template MacroVFPMemConstructor {{
 599 %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
 600         RegIndex vd, bool single, bool up, bool writeback, bool load,
 601         uint32_t offset)
 602     : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
 603                      vd, single, up, writeback, load, offset)
 604 {
 605     %(constructor)s;
 606     if (!(condCode == COND_AL || condCode == COND_UC)) {
 607         for (int x = 0; x < _numDestRegs; x++) {
 608             setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
 609         }
 610     }
 611 }
 612
 613 }};