3 // Copyright (c) 2010 ARM Limited
6 // The license below extends only to copyright in the software and shall
7 // not be construed as granting a license to any other intellectual
8 // property including but not limited to intellectual property relating
9 // to a hardware implementation of the functionality of the software
10 // licensed hereunder. You may use the software subject to the license
11 // terms below provided that you ensure that this notice is replicated
12 // unmodified and in its entirety in all distributions of the software,
13 // modified or unmodified, in source code or in binary form.
15 // Copyright (c) 2007-2008 The Florida State University
16 // All rights reserved.
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are
20 // met: redistributions of source code must retain the above copyright
21 // notice, this list of conditions and the following disclaimer;
22 // redistributions in binary form must reproduce the above copyright
23 // notice, this list of conditions and the following disclaimer in the
24 // documentation and/or other materials provided with the distribution;
25 // neither the name of the copyright holders nor the names of its
26 // contributors may be used to endorse or promote products derived from
27 // this software without specific prior written permission.
29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 // Authors: Stephen Hines
44 def template PanicExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
48 panic("Execute function executed when it shouldn't be!\n");
53 def template PanicInitiateAcc {{
54 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
55 Trace::InstRecord *traceData) const
57 panic("InitiateAcc function executed when it shouldn't be!\n");
62 def template PanicCompleteAcc {{
63 Fault %(class_name)s::completeAcc(PacketPtr pkt,
64 %(CPU_exec_context)s *xc,
65 Trace::InstRecord *traceData) const
67 panic("CompleteAcc function executed when it shouldn't be!\n");
73 def template SwapExecute {{
74 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
75 Trace::InstRecord *traceData) const
78 Fault fault = NoFault;
85 if (%(predicate_test)s)
89 if (fault == NoFault) {
90 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
94 if (fault == NoFault) {
98 if (fault == NoFault) {
102 xc->setPredicate(false);
109 def template SwapInitiateAcc {{
110 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
111 Trace::InstRecord *traceData) const
114 Fault fault = NoFault;
117 uint64_t memData = 0;
121 if (%(predicate_test)s)
125 if (fault == NoFault) {
126 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
130 xc->setPredicate(false);
137 def template SwapCompleteAcc {{
138 Fault %(class_name)s::completeAcc(PacketPtr pkt,
139 %(CPU_exec_context)s *xc,
140 Trace::InstRecord *traceData) const
142 Fault fault = NoFault;
147 if (%(predicate_test)s)
149 // ARM instructions will not have a pkt if the predicate is false
150 getMem(pkt, Mem, traceData);
151 uint64_t memData = Mem;
155 if (fault == NoFault) {
164 def template LoadExecute {{
165 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
166 Trace::InstRecord *traceData) const
169 Fault fault = NoFault;
175 if (%(predicate_test)s)
177 if (fault == NoFault) {
178 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
182 if (fault == NoFault) {
186 xc->setPredicate(false);
193 def template NeonLoadExecute {{
194 template <class Element>
195 Fault %(class_name)s<Element>::execute(
196 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
199 Fault fault = NoFault;
207 uint8_t *dataPtr = memUnion.bytes;
209 if (%(predicate_test)s)
211 if (fault == NoFault) {
212 fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
216 if (fault == NoFault) {
220 xc->setPredicate(false);
227 def template StoreExecute {{
228 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
229 Trace::InstRecord *traceData) const
232 Fault fault = NoFault;
238 if (%(predicate_test)s)
240 if (fault == NoFault) {
244 if (fault == NoFault) {
245 fault = writeMemAtomic(xc, traceData, Mem, EA,
246 memAccessFlags, NULL);
249 if (fault == NoFault) {
253 xc->setPredicate(false);
260 def template NeonStoreExecute {{
261 template <class Element>
262 Fault %(class_name)s<Element>::execute(
263 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
266 Fault fault = NoFault;
274 uint8_t *dataPtr = memUnion.bytes;
276 if (%(predicate_test)s)
278 if (fault == NoFault) {
282 if (fault == NoFault) {
283 fault = xc->writeMem(dataPtr, %(size)d, EA,
284 memAccessFlags, NULL);
287 if (fault == NoFault) {
291 xc->setPredicate(false);
298 def template StoreExExecute {{
299 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
300 Trace::InstRecord *traceData) const
303 Fault fault = NoFault;
309 if (%(predicate_test)s)
311 if (fault == NoFault) {
315 uint64_t writeResult;
317 if (fault == NoFault) {
318 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
322 if (fault == NoFault) {
326 if (fault == NoFault) {
330 xc->setPredicate(false);
337 def template StoreExInitiateAcc {{
338 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
339 Trace::InstRecord *traceData) const
342 Fault fault = NoFault;
348 if (%(predicate_test)s)
350 if (fault == NoFault) {
354 if (fault == NoFault) {
355 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
359 xc->setPredicate(false);
366 def template StoreInitiateAcc {{
367 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
368 Trace::InstRecord *traceData) const
371 Fault fault = NoFault;
377 if (%(predicate_test)s)
379 if (fault == NoFault) {
383 if (fault == NoFault) {
384 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
388 xc->setPredicate(false);
395 def template NeonStoreInitiateAcc {{
396 template <class Element>
397 Fault %(class_name)s<Element>::initiateAcc(
398 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
401 Fault fault = NoFault;
408 if (%(predicate_test)s)
411 if (fault == NoFault) {
415 if (fault == NoFault) {
416 fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
417 memAccessFlags, NULL);
420 xc->setPredicate(false);
427 def template LoadInitiateAcc {{
428 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
429 Trace::InstRecord *traceData) const
432 Fault fault = NoFault;
438 if (%(predicate_test)s)
440 if (fault == NoFault) {
441 fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
444 xc->setPredicate(false);
451 def template NeonLoadInitiateAcc {{
452 template <class Element>
453 Fault %(class_name)s<Element>::initiateAcc(
454 %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
457 Fault fault = NoFault;
465 uint8_t *dataPtr = memUnion.bytes;
467 if (%(predicate_test)s)
469 if (fault == NoFault) {
470 fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
473 xc->setPredicate(false);
480 def template LoadCompleteAcc {{
481 Fault %(class_name)s::completeAcc(PacketPtr pkt,
482 %(CPU_exec_context)s *xc,
483 Trace::InstRecord *traceData) const
485 Fault fault = NoFault;
490 if (%(predicate_test)s)
492 // ARM instructions will not have a pkt if the predicate is false
493 getMem(pkt, Mem, traceData);
495 if (fault == NoFault) {
499 if (fault == NoFault) {
508 def template NeonLoadCompleteAcc {{
509 template <class Element>
510 Fault %(class_name)s<Element>::completeAcc(
511 PacketPtr pkt, %(CPU_exec_context)s *xc,
512 Trace::InstRecord *traceData) const
514 Fault fault = NoFault;
520 if (%(predicate_test)s)
522 // ARM instructions will not have a pkt if the predicate is false
523 MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
525 if (fault == NoFault) {
529 if (fault == NoFault) {
538 def template StoreCompleteAcc {{
539 Fault %(class_name)s::completeAcc(PacketPtr pkt,
540 %(CPU_exec_context)s *xc,
541 Trace::InstRecord *traceData) const
547 def template NeonStoreCompleteAcc {{
548 template <class Element>
549 Fault %(class_name)s<Element>::completeAcc(
550 PacketPtr pkt, %(CPU_exec_context)s *xc,
551 Trace::InstRecord *traceData) const
557 def template StoreExCompleteAcc {{
558 Fault %(class_name)s::completeAcc(PacketPtr pkt,
559 %(CPU_exec_context)s *xc,
560 Trace::InstRecord *traceData) const
562 Fault fault = NoFault;
567 if (%(predicate_test)s)
569 uint64_t writeResult = pkt->req->getExtraData();
572 if (fault == NoFault) {
581 def template RfeDeclare {{
583 * Static instruction class for "%(mnemonic)s".
585 class %(class_name)s : public %(base_class)s
590 %(class_name)s(ExtMachInst machInst,
591 uint32_t _base, int _mode, bool _wb);
595 %(InitiateAccDeclare)s
597 %(CompleteAccDeclare)s
601 def template SrsDeclare {{
603 * Static instruction class for "%(mnemonic)s".
605 class %(class_name)s : public %(base_class)s
610 %(class_name)s(ExtMachInst machInst,
611 uint32_t _regMode, int _mode, bool _wb);
615 %(InitiateAccDeclare)s
617 %(CompleteAccDeclare)s
621 def template SwapDeclare {{
623 * Static instruction class for "%(mnemonic)s".
625 class %(class_name)s : public %(base_class)s
630 %(class_name)s(ExtMachInst machInst,
631 uint32_t _dest, uint32_t _op1, uint32_t _base);
635 %(InitiateAccDeclare)s
637 %(CompleteAccDeclare)s
641 def template LoadStoreDImmDeclare {{
643 * Static instruction class for "%(mnemonic)s".
645 class %(class_name)s : public %(base_class)s
650 %(class_name)s(ExtMachInst machInst,
651 uint32_t _dest, uint32_t _dest2,
652 uint32_t _base, bool _add, int32_t _imm);
656 %(InitiateAccDeclare)s
658 %(CompleteAccDeclare)s
662 def template StoreExDImmDeclare {{
664 * Static instruction class for "%(mnemonic)s".
666 class %(class_name)s : public %(base_class)s
671 %(class_name)s(ExtMachInst machInst,
672 uint32_t _result, uint32_t _dest, uint32_t _dest2,
673 uint32_t _base, bool _add, int32_t _imm);
677 %(InitiateAccDeclare)s
679 %(CompleteAccDeclare)s
683 def template LoadStoreImmDeclare {{
685 * Static instruction class for "%(mnemonic)s".
687 class %(class_name)s : public %(base_class)s
692 %(class_name)s(ExtMachInst machInst,
693 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
697 %(InitiateAccDeclare)s
699 %(CompleteAccDeclare)s
703 def template StoreExImmDeclare {{
705 * Static instruction class for "%(mnemonic)s".
707 class %(class_name)s : public %(base_class)s
712 %(class_name)s(ExtMachInst machInst,
713 uint32_t _result, uint32_t _dest, uint32_t _base,
714 bool _add, int32_t _imm);
718 %(InitiateAccDeclare)s
720 %(CompleteAccDeclare)s
724 def template StoreDRegDeclare {{
726 * Static instruction class for "%(mnemonic)s".
728 class %(class_name)s : public %(base_class)s
733 %(class_name)s(ExtMachInst machInst,
734 uint32_t _dest, uint32_t _dest2,
735 uint32_t _base, bool _add,
736 int32_t _shiftAmt, uint32_t _shiftType,
741 %(InitiateAccDeclare)s
743 %(CompleteAccDeclare)s
747 def template StoreRegDeclare {{
749 * Static instruction class for "%(mnemonic)s".
751 class %(class_name)s : public %(base_class)s
756 %(class_name)s(ExtMachInst machInst,
757 uint32_t _dest, uint32_t _base, bool _add,
758 int32_t _shiftAmt, uint32_t _shiftType,
763 %(InitiateAccDeclare)s
765 %(CompleteAccDeclare)s
769 def template LoadDRegDeclare {{
771 * Static instruction class for "%(mnemonic)s".
773 class %(class_name)s : public %(base_class)s
778 %(class_name)s(ExtMachInst machInst,
779 uint32_t _dest, uint32_t _dest2,
780 uint32_t _base, bool _add,
781 int32_t _shiftAmt, uint32_t _shiftType,
786 %(InitiateAccDeclare)s
788 %(CompleteAccDeclare)s
792 def template LoadRegDeclare {{
794 * Static instruction class for "%(mnemonic)s".
796 class %(class_name)s : public %(base_class)s
801 %(class_name)s(ExtMachInst machInst,
802 uint32_t _dest, uint32_t _base, bool _add,
803 int32_t _shiftAmt, uint32_t _shiftType,
808 %(InitiateAccDeclare)s
810 %(CompleteAccDeclare)s
814 def template LoadImmDeclare {{
816 * Static instruction class for "%(mnemonic)s".
818 class %(class_name)s : public %(base_class)s
823 %(class_name)s(ExtMachInst machInst,
824 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
828 %(InitiateAccDeclare)s
830 %(CompleteAccDeclare)s
834 def template InitiateAccDeclare {{
835 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
838 def template CompleteAccDeclare {{
839 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
842 def template RfeConstructor {{
843 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
844 uint32_t _base, int _mode, bool _wb)
845 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
846 (IntRegIndex)_base, (AddrMode)_mode, _wb)
849 if (!(condCode == COND_AL || condCode == COND_UC)) {
850 for (int x = 0; x < _numDestRegs; x++) {
851 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
855 uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d];
857 uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb);
858 uops[uopIdx]->setDelayedCommit();
860 uops[++uopIdx] = new %(wb_decl)s;
861 uops[uopIdx]->setDelayedCommit();
864 uops[++uopIdx] = new %(pc_decl)s;
866 uops[uopIdx]->setLastMicroop();
871 def template SrsConstructor {{
872 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
873 uint32_t _regMode, int _mode, bool _wb)
874 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
875 (OperatingMode)_regMode, (AddrMode)_mode, _wb)
878 if (!(condCode == COND_AL || condCode == COND_UC)) {
879 for (int x = 0; x < _numDestRegs; x++) {
880 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
884 assert(numMicroops >= 2);
885 uops = new StaticInstPtr[numMicroops];
886 uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
887 uops[0]->setDelayedCommit();
888 uops[1] = new %(wb_decl)s;
889 uops[1]->setLastMicroop();
894 def template SwapConstructor {{
895 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
896 uint32_t _dest, uint32_t _op1, uint32_t _base)
897 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
898 (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
901 if (!(condCode == COND_AL || condCode == COND_UC)) {
902 for (int x = 0; x < _numDestRegs; x++) {
903 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
909 def template LoadStoreDImmConstructor {{
910 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
911 uint32_t _dest, uint32_t _dest2,
912 uint32_t _base, bool _add, int32_t _imm)
913 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
914 (IntRegIndex)_dest, (IntRegIndex)_dest2,
915 (IntRegIndex)_base, _add, _imm)
918 if (!(condCode == COND_AL || condCode == COND_UC)) {
919 for (int x = 0; x < _numDestRegs; x++) {
920 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
924 assert(numMicroops >= 2);
925 uops = new StaticInstPtr[numMicroops];
926 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
927 uops[0]->setDelayedCommit();
928 uops[1] = new %(wb_decl)s;
929 uops[1]->setLastMicroop();
934 def template StoreExDImmConstructor {{
935 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
936 uint32_t _result, uint32_t _dest, uint32_t _dest2,
937 uint32_t _base, bool _add, int32_t _imm)
938 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
939 (IntRegIndex)_result,
940 (IntRegIndex)_dest, (IntRegIndex)_dest2,
941 (IntRegIndex)_base, _add, _imm)
944 if (!(condCode == COND_AL || condCode == COND_UC)) {
945 for (int x = 0; x < _numDestRegs; x++) {
946 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
950 assert(numMicroops >= 2);
951 uops = new StaticInstPtr[numMicroops];
952 uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
954 uops[0]->setDelayedCommit();
955 uops[1] = new %(wb_decl)s;
956 uops[1]->setLastMicroop();
961 def template LoadStoreImmConstructor {{
962 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
963 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
964 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
965 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
968 if (!(condCode == COND_AL || condCode == COND_UC)) {
969 for (int x = 0; x < _numDestRegs; x++) {
970 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
974 assert(numMicroops >= 2);
975 uops = new StaticInstPtr[numMicroops];
976 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
977 uops[0]->setDelayedCommit();
978 uops[1] = new %(wb_decl)s;
979 uops[1]->setLastMicroop();
984 def template StoreExImmConstructor {{
985 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
986 uint32_t _result, uint32_t _dest, uint32_t _base,
987 bool _add, int32_t _imm)
988 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
989 (IntRegIndex)_result, (IntRegIndex)_dest,
990 (IntRegIndex)_base, _add, _imm)
993 if (!(condCode == COND_AL || condCode == COND_UC)) {
994 for (int x = 0; x < _numDestRegs; x++) {
995 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
999 assert(numMicroops >= 2);
1000 uops = new StaticInstPtr[numMicroops];
1001 uops[0] = new %(acc_name)s(machInst, _result, _dest,
1003 uops[0]->setDelayedCommit();
1004 uops[1] = new %(wb_decl)s;
1005 uops[1]->setLastMicroop();
1010 def template StoreDRegConstructor {{
1011 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1012 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1013 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1014 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1015 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1016 (IntRegIndex)_base, _add,
1017 _shiftAmt, (ArmShiftType)_shiftType,
1018 (IntRegIndex)_index)
1021 if (!(condCode == COND_AL || condCode == COND_UC)) {
1022 for (int x = 0; x < _numDestRegs; x++) {
1023 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1027 assert(numMicroops >= 2);
1028 uops = new StaticInstPtr[numMicroops];
1029 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1030 _shiftAmt, _shiftType, _index);
1031 uops[0]->setDelayedCommit();
1032 uops[1] = new %(wb_decl)s;
1033 uops[1]->setLastMicroop();
1038 def template StoreRegConstructor {{
1039 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1040 uint32_t _dest, uint32_t _base, bool _add,
1041 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1042 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1043 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1044 _shiftAmt, (ArmShiftType)_shiftType,
1045 (IntRegIndex)_index)
1048 if (!(condCode == COND_AL || condCode == COND_UC)) {
1049 for (int x = 0; x < _numDestRegs; x++) {
1050 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1054 assert(numMicroops >= 2);
1055 uops = new StaticInstPtr[numMicroops];
1056 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1057 _shiftAmt, _shiftType, _index);
1058 uops[0]->setDelayedCommit();
1059 uops[1] = new %(wb_decl)s;
1060 uops[1]->setLastMicroop();
1065 def template LoadDRegConstructor {{
1066 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1067 uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
1068 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1069 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1070 (IntRegIndex)_dest, (IntRegIndex)_dest2,
1071 (IntRegIndex)_base, _add,
1072 _shiftAmt, (ArmShiftType)_shiftType,
1073 (IntRegIndex)_index)
1076 if (!(condCode == COND_AL || condCode == COND_UC)) {
1077 for (int x = 0; x < _numDestRegs; x++) {
1078 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1082 assert(numMicroops >= 2);
1083 uops = new StaticInstPtr[numMicroops];
1084 if ((_dest == _index) || (_dest2 == _index)) {
1085 IntRegIndex wbIndexReg = INTREG_UREG0;
1086 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1087 uops[0]->setDelayedCommit();
1088 uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1089 _shiftAmt, _shiftType, _index);
1090 uops[1]->setDelayedCommit();
1091 uops[2] = new %(wb_decl)s;
1092 uops[2]->setLastMicroop();
1094 IntRegIndex wbIndexReg = index;
1095 uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
1096 _shiftAmt, _shiftType, _index);
1097 uops[0]->setDelayedCommit();
1098 uops[1] = new %(wb_decl)s;
1099 uops[1]->setLastMicroop();
1105 def template LoadRegConstructor {{
1106 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1107 uint32_t _dest, uint32_t _base, bool _add,
1108 int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
1109 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1110 (IntRegIndex)_dest, (IntRegIndex)_base, _add,
1111 _shiftAmt, (ArmShiftType)_shiftType,
1112 (IntRegIndex)_index)
1115 bool conditional M5_VAR_USED = false;
1116 if (!(condCode == COND_AL || condCode == COND_UC)) {
1118 for (int x = 0; x < _numDestRegs; x++) {
1119 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1123 assert(numMicroops >= 2);
1124 uops = new StaticInstPtr[numMicroops];
1125 if (_dest == INTREG_PC && !isFloating()) {
1126 IntRegIndex wbIndexReg = index;
1127 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1128 _shiftAmt, _shiftType, _index);
1129 uops[0]->setDelayedCommit();
1130 uops[1] = new %(wb_decl)s;
1131 uops[1]->setDelayedCommit();
1132 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1133 uops[2]->setFlag(StaticInst::IsControl);
1134 uops[2]->setFlag(StaticInst::IsIndirectControl);
1136 uops[2]->setFlag(StaticInst::IsCondControl);
1138 uops[2]->setFlag(StaticInst::IsUncondControl);
1139 uops[2]->setLastMicroop();
1140 } else if(_dest == _index) {
1141 IntRegIndex wbIndexReg = INTREG_UREG0;
1142 uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
1143 uops[0]->setDelayedCommit();
1144 uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
1145 _shiftAmt, _shiftType, _index);
1146 uops[1]->setDelayedCommit();
1147 uops[2] = new %(wb_decl)s;
1148 uops[2]->setLastMicroop();
1150 IntRegIndex wbIndexReg = index;
1151 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
1152 _shiftAmt, _shiftType, _index);
1153 uops[0]->setDelayedCommit();
1154 uops[1] = new %(wb_decl)s;
1155 uops[1]->setLastMicroop();
1159 if (_dest == INTREG_PC && !isFloating()) {
1160 flags[IsControl] = true;
1161 flags[IsIndirectControl] = true;
1163 flags[IsCondControl] = true;
1165 flags[IsUncondControl] = true;
1171 def template LoadImmConstructor {{
1172 inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
1173 uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
1174 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
1175 (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
1178 bool conditional M5_VAR_USED = false;
1179 if (!(condCode == COND_AL || condCode == COND_UC)) {
1181 for (int x = 0; x < _numDestRegs; x++) {
1182 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
1186 assert(numMicroops >= 2);
1187 uops = new StaticInstPtr[numMicroops];
1188 if (_dest == INTREG_PC && !isFloating()) {
1189 uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
1191 uops[0]->setDelayedCommit();
1192 uops[1] = new %(wb_decl)s;
1193 uops[1]->setDelayedCommit();
1194 uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
1195 uops[2]->setFlag(StaticInst::IsControl);
1196 uops[2]->setFlag(StaticInst::IsIndirectControl);
1198 uops[2]->setFlag(StaticInst::IsCondControl);
1200 uops[2]->setFlag(StaticInst::IsUncondControl);
1201 if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s)
1202 uops[2]->setFlag(StaticInst::IsReturn);
1203 uops[2]->setLastMicroop();
1205 uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
1206 uops[0]->setDelayedCommit();
1207 uops[1] = new %(wb_decl)s;
1208 uops[1]->setLastMicroop();
1211 if (_dest == INTREG_PC && !isFloating()) {
1212 flags[IsControl] = true;
1213 flags[IsIndirectControl] = true;
1215 flags[IsCondControl] = true;
1217 flags[IsUncondControl] = true;