src/arch/arm/isa/templates/neon.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2010-2012 ARM Limited
   4 // All rights reserved
   5 //
   6 // The license below extends only to copyright in the software and shall
   7 // not be construed as granting a license to any other intellectual
   8 // property including but not limited to intellectual property relating
   9 // to a hardware implementation of the functionality of the software
  10 // licensed hereunder.  You may use the software subject to the license
  11 // terms below provided that you ensure that this notice is replicated
  12 // unmodified and in its entirety in all distributions of the software,
  13 // modified or unmodified, in source code or in binary form.
  14 //
  15 // Redistribution and use in source and binary forms, with or without
  16 // modification, are permitted provided that the following conditions are
  17 // met: redistributions of source code must retain the above copyright
  18 // notice, this list of conditions and the following disclaimer;
  19 // redistributions in binary form must reproduce the above copyright
  20 // notice, this list of conditions and the following disclaimer in the
  21 // documentation and/or other materials provided with the distribution;
  22 // neither the name of the copyright holders nor the names of its
  23 // contributors may be used to endorse or promote products derived from
  24 // this software without specific prior written permission.
  25 //
  26 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37 //
  38 // Authors: Gabe Black
  39
  40 let {{
  41     simdEnabledCheckCode = '''
  42     {
  43         uint32_t issEnCheck;
  44         bool trapEnCheck;
  45         uint32_t seq;
  46         if (!vfpNeonEnabled(seq, Hcptr, Nsacr, Cpacr, Cpsr, issEnCheck,
  47                             trapEnCheck, xc->tcBase(), Fpexc, true))
  48             {return disabledFault();}
  49         if (trapEnCheck) {
  50             CPSR cpsrEnCheck = Cpsr;
  51             if (cpsrEnCheck.mode == MODE_HYP) {
  52                 return new UndefinedInstruction(machInst, issEnCheck,
  53                                                 EC_TRAPPED_HCPTR);
  54             } else {
  55                 if (!inSecureState(Scr, Cpsr)) {
  56                     return new HypervisorTrap(machInst, issEnCheck,
  57                                               EC_TRAPPED_HCPTR);
  58                 }
  59             }
  60         }
  61     }
  62     '''
  63 }};
  64
  65
  66 def template NeonRegRegRegOpDeclare {{
  67 template <class _Element>
  68 class %(class_name)s : public %(base_class)s
  69 {
  70   protected:
  71     typedef _Element Element;
  72   public:
  73     // Constructor
  74     %(class_name)s(ExtMachInst machInst,
  75                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
  76         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
  77                          _dest, _op1, _op2)
  78     {
  79         %(constructor)s;
  80         if (!(condCode == COND_AL || condCode == COND_UC)) {
  81             for (int x = 0; x < _numDestRegs; x++) {
  82                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
  83             }
  84         }
  85     }
  86
  87     %(BasicExecDeclare)s
  88 };
  89 }};
  90
  91 def template NeonRegRegRegImmOpDeclare {{
  92 template <class _Element>
  93 class %(class_name)s : public %(base_class)s
  94 {
  95   protected:
  96     typedef _Element Element;
  97   public:
  98     // Constructor
  99     %(class_name)s(ExtMachInst machInst,
 100                    IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
 101                    uint64_t _imm)
 102         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 103                          _dest, _op1, _op2, _imm)
 104     {
 105         %(constructor)s;
 106         if (!(condCode == COND_AL || condCode == COND_UC)) {
 107             for (int x = 0; x < _numDestRegs; x++) {
 108                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
 109             }
 110         }
 111     }
 112
 113     %(BasicExecDeclare)s
 114 };
 115 }};
 116
 117 def template NeonRegRegImmOpDeclare {{
 118 template <class _Element>
 119 class %(class_name)s : public %(base_class)s
 120 {
 121   protected:
 122     typedef _Element Element;
 123   public:
 124     // Constructor
 125     %(class_name)s(ExtMachInst machInst,
 126                    IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
 127         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 128                          _dest, _op1, _imm)
 129     {
 130         %(constructor)s;
 131         if (!(condCode == COND_AL || condCode == COND_UC)) {
 132             for (int x = 0; x < _numDestRegs; x++) {
 133                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
 134             }
 135         }
 136     }
 137
 138     %(BasicExecDeclare)s
 139 };
 140 }};
 141
 142 def template NeonRegImmOpDeclare {{
 143 template <class _Element>
 144 class %(class_name)s : public %(base_class)s
 145 {
 146   protected:
 147     typedef _Element Element;
 148   public:
 149     // Constructor
 150     %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm)
 151         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
 152     {
 153         %(constructor)s;
 154         if (!(condCode == COND_AL || condCode == COND_UC)) {
 155             for (int x = 0; x < _numDestRegs; x++) {
 156                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
 157             }
 158         }
 159     }
 160
 161     %(BasicExecDeclare)s
 162 };
 163 }};
 164
 165 def template NeonRegRegOpDeclare {{
 166 template <class _Element>
 167 class %(class_name)s : public %(base_class)s
 168 {
 169   protected:
 170     typedef _Element Element;
 171   public:
 172     // Constructor
 173     %(class_name)s(ExtMachInst machInst,
 174                    IntRegIndex _dest, IntRegIndex _op1)
 175         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
 176                          _dest, _op1)
 177     {
 178         %(constructor)s;
 179         if (!(condCode == COND_AL || condCode == COND_UC)) {
 180             for (int x = 0; x < _numDestRegs; x++) {
 181                 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
 182             }
 183         }
 184     }
 185
 186     %(BasicExecDeclare)s
 187 };
 188 }};
 189
 190 def template NeonExecDeclare {{
 191     template
 192     Fault %(class_name)s<%(targs)s>::execute(
 193             %(CPU_exec_context)s *, Trace::InstRecord *) const;
 194 }};
 195
 196 output header {{
 197     template <class T>
 198     // Implement a less-than-zero function: ltz()
 199     // this function exists because some versions of GCC complain when a
 200     // comparison is done between a unsigned variable and 0 and for GCC 4.2
 201     // there is no way to disable this warning
 202     inline bool ltz(T t);
 203
 204     template <>
 205     inline bool ltz(uint8_t) { return false; }
 206     template <>
 207     inline bool ltz(uint16_t) { return false; }
 208     template <>
 209     inline bool ltz(uint32_t) { return false; }
 210     template <>
 211     inline bool ltz(uint64_t) { return false; }
 212     template <>
 213     inline bool ltz(int8_t v) { return v < 0; }
 214     template <>
 215     inline bool ltz(int16_t v) { return v < 0; }
 216     template <>
 217     inline bool ltz(int32_t v) { return v < 0; }
 218     template <>
 219     inline bool ltz(int64_t v) { return v < 0; }
 220 }};
 221
 222 def template NeonEqualRegExecute {{
 223     template <class Element>
 224     Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
 225             Trace::InstRecord *traceData) const
 226     {
 227         Fault fault = NoFault;
 228         %(op_decl)s;
 229         %(op_rd)s;
 230
 231         const unsigned rCount = %(r_count)d;
 232         const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
 233
 234         union RegVect {
 235             FloatRegBits regs[rCount];
 236             Element elements[eCount];
 237         };
 238
 239         if (%(predicate_test)s)
 240         {
 241             %(code)s;
 242             if (fault == NoFault)
 243             {
 244                 %(op_wb)s;
 245             }
 246         } else {
 247             xc->setPredicate(false);
 248         }
 249
 250         return fault;
 251     }
 252 }};
 253
 254 output header {{
 255         template <typename T>
 256             struct bigger_type_t;
 257
 258         template<> struct bigger_type_t<uint8_t> { typedef uint16_t type; };
 259         template<> struct bigger_type_t<uint16_t> { typedef uint32_t type; };
 260         template<> struct bigger_type_t<uint32_t> { typedef uint64_t type; };
 261
 262         template<> struct bigger_type_t<int8_t> { typedef int16_t type; };
 263         template<> struct bigger_type_t<int16_t> { typedef int32_t type; };
 264         template<> struct bigger_type_t<int32_t> { typedef int64_t type; };
 265 }};
 266
 267 def template NeonUnequalRegExecute {{
 268     template <class Element>
 269     Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
 270             Trace::InstRecord *traceData) const
 271     {
 272         typedef typename bigger_type_t<Element>::type BigElement;
 273         Fault fault = NoFault;
 274         %(op_decl)s;
 275         %(op_rd)s;
 276
 277         const unsigned rCount = %(r_count)d;
 278         const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
 279
 280         union RegVect {
 281             FloatRegBits regs[rCount];
 282             Element elements[eCount];
 283             BigElement bigElements[eCount / 2];
 284         };
 285
 286         union BigRegVect {
 287             FloatRegBits regs[2 * rCount];
 288             BigElement elements[eCount];
 289         };
 290
 291         if (%(predicate_test)s)
 292         {
 293             %(code)s;
 294             if (fault == NoFault)
 295             {
 296                 %(op_wb)s;
 297             }
 298         } else {
 299             xc->setPredicate(false);
 300         }
 301
 302         return fault;
 303     }
 304 }};