src/arch/arm/isa/templates/semihost.isa

   1 // -*- mode:c++ -*-
   2 // Copyright (c) 2018 ARM Limited
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  36
  37 //
  38 // A new class of Semihosting constructor templates has been added.
  39 // Their main purpose is to check if the Exception Generation
  40 // Instructions (HLT, SVC) are actually a semihosting command.
  41 // If that is the case, the IsReadBarrier and IsWriteBarrier flags are raised,
  42 // so that in the O3 model we perform a coherent memory access during
  43 // the semihosting operation.
  44 // Please note: since we don't have a thread context pointer in the
  45 // constructor we cannot check if semihosting is enabled in the
  46 // system. This is not affecting functional correctness, it just
  47 // means O3 models will flush the LSQ even if semihosting is disabled
  48 // when a semihosting immediate is recognized.
  49
  50 def template SemihostConstructor {{
  51     %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
  52         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
  53     {
  54         %(set_reg_idx_arr)s;
  55         %(constructor)s;
  56         if (!(condCode == COND_AL || condCode == COND_UC)) {
  57             for (int x = 0; x < _numDestRegs; x++) {
  58                 setSrcRegIdx(_numSrcRegs++, destRegIdx(x));
  59             }
  60         }
  61
  62         // In AArch32 semihosting commands can be issued by either
  63         // SVC and HLT instructions. Another degree of freedom
  64         // is added by the operating mode (Arm or Thumb)
  65         auto semihost_imm = machInst.thumb? %(thumb_semihost)s :
  66                                             %(arm_semihost)s;
  67         if (_imm == semihost_imm) {
  68             flags[IsReadBarrier] = true;
  69             flags[IsWriteBarrier] = true;
  70         }
  71     }
  72 }};
  73
  74 def template SemihostConstructor64 {{
  75     %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) :
  76         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
  77     {
  78         %(set_reg_idx_arr)s;
  79         %(constructor)s;
  80
  81         // In AArch64 there is only one instruction for issuing
  82         // semhosting commands: HLT #0xF000
  83         if (_imm == 0xF000) {
  84             flags[IsReadBarrier] = true;
  85             flags[IsWriteBarrier] = true;
  86         }
  87     }
  88 }};