2 * Copyright (c) 2010-2020 ARM Limited
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38 #include "arch/arm/isa.hh"
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/interrupts.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "arch/arm/tlbi_op.hh"
46 #include "cpu/base.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "debug/Arm.hh"
49 #include "debug/MiscRegs.hh"
50 #include "dev/arm/generic_timer.hh"
51 #include "dev/arm/gic_v3.hh"
52 #include "dev/arm/gic_v3_cpu_interface.hh"
53 #include "params/ArmISA.hh"
54 #include "sim/faults.hh"
55 #include "sim/stat_control.hh"
56 #include "sim/system.hh"
61 ISA::ISA(Params
*p
) : BaseISA(p
), system(NULL
),
62 _decoderFlavor(p
->decoderFlavor
), _vecRegRenameMode(Enums::Full
),
63 pmu(p
->pmu
), haveGICv3CPUInterface(false), impdefAsNop(p
->impdef_nop
),
66 miscRegs
[MISCREG_SCTLR_RST
] = 0;
68 // Hook up a dummy device if we haven't been configured with a
69 // real PMU. By using a dummy device, we don't need to check that
70 // the PMU exist every time we try to access a PMU register.
74 // Give all ISA devices a pointer to this ISA
77 system
= dynamic_cast<ArmSystem
*>(p
->system
);
79 // Cache system-level properties
80 if (FullSystem
&& system
) {
81 highestELIs64
= system
->highestELIs64();
82 haveSecurity
= system
->haveSecurity();
83 haveLPAE
= system
->haveLPAE();
84 haveCrypto
= system
->haveCrypto();
85 haveVirtualization
= system
->haveVirtualization();
86 haveLargeAsid64
= system
->haveLargeAsid64();
87 physAddrRange
= system
->physAddrRange();
88 haveSVE
= system
->haveSVE();
89 havePAN
= system
->havePAN();
90 sveVL
= system
->sveVL();
91 haveLSE
= system
->haveLSE();
93 highestELIs64
= true; // ArmSystem::highestELIs64 does the same
94 haveSecurity
= haveLPAE
= haveVirtualization
= false;
96 haveLargeAsid64
= false;
97 physAddrRange
= 32; // dummy value
100 sveVL
= p
->sve_vl_se
;
104 // Initial rename mode depends on highestEL
105 const_cast<Enums::VecRegRenameMode
&>(_vecRegRenameMode
) =
106 highestELIs64
? Enums::Full
: Enums::Elem
;
108 initializeMiscRegMetadata();
109 preUnflattenMiscReg();
114 std::vector
<struct ISA::MiscRegLUTEntry
> ISA::lookUpMiscReg(NUM_MISCREGS
);
119 return dynamic_cast<const Params
*>(_params
);
123 ISA::clear(ThreadContext
*tc
)
126 // Invalidate cached copies of miscregs in the TLBs
127 getITBPtr(tc
)->invalidateMiscReg();
128 getDTBPtr(tc
)->invalidateMiscReg();
134 const Params
*p(params());
136 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
137 memset(miscRegs
, 0, sizeof(miscRegs
));
141 // We always initialize AArch64 ID registers even
142 // if we are in AArch32. This is done since if we
143 // are in SE mode we don't know if our ArmProcess is
144 // AArch32 or AArch64
147 // Start with an event in the mailbox
148 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
150 // Separate Instruction and Data TLBs
151 miscRegs
[MISCREG_TLBTR
] = 1;
154 mvfr0
.advSimdRegisters
= 2;
155 mvfr0
.singlePrecision
= 2;
156 mvfr0
.doublePrecision
= 2;
157 mvfr0
.vfpExceptionTrapping
= 0;
159 mvfr0
.squareRoot
= 1;
160 mvfr0
.shortVectors
= 1;
161 mvfr0
.roundingModes
= 1;
162 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
165 mvfr1
.flushToZero
= 1;
166 mvfr1
.defaultNaN
= 1;
167 mvfr1
.advSimdLoadStore
= 1;
168 mvfr1
.advSimdInteger
= 1;
169 mvfr1
.advSimdSinglePrecision
= 1;
170 mvfr1
.advSimdHalfPrecision
= 1;
171 mvfr1
.vfpHalfPrecision
= 1;
172 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
174 // Reset values of PRRR and NMRR are implementation dependent
176 // @todo: PRRR and NMRR in secure state?
177 miscRegs
[MISCREG_PRRR_NS
] =
191 miscRegs
[MISCREG_NMRR_NS
] =
208 if (FullSystem
&& system
->highestELIs64()) {
209 // Initialize AArch64 state
214 // Initialize AArch32 state...
215 clear32(p
, sctlr_rst
);
219 ISA::clear32(const ArmISAParams
*p
, const SCTLR
&sctlr_rst
)
222 cpsr
.mode
= MODE_USER
;
225 miscRegs
[MISCREG_MVBAR
] = system
->resetAddr();
228 miscRegs
[MISCREG_CPSR
] = cpsr
;
232 sctlr
.te
= (bool) sctlr_rst
.te
;
233 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
234 sctlr
.v
= (bool) sctlr_rst
.v
;
239 sctlr
.rao4
= 0xf; // SCTLR[6:3]
242 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
243 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
244 miscRegs
[MISCREG_HCPTR
] = 0;
246 miscRegs
[MISCREG_CPACR
] = 0;
248 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
251 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
253 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
254 // Enforce consistency with system-level settings
255 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
259 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
260 miscRegs
[MISCREG_SCR
] = 0;
261 miscRegs
[MISCREG_VBAR_S
] = 0;
263 // we're always non-secure
264 miscRegs
[MISCREG_SCR
] = 1;
267 //XXX We need to initialize the rest of the state.
271 ISA::clear64(const ArmISAParams
*p
)
274 Addr rvbar
= system
->resetAddr();
275 switch (system
->highestEL()) {
276 // Set initial EL to highest implemented EL using associated stack
277 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
280 cpsr
.mode
= MODE_EL3H
;
281 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
284 cpsr
.mode
= MODE_EL2H
;
285 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
288 cpsr
.mode
= MODE_EL1H
;
289 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
292 panic("Invalid highest implemented exception level");
296 // Initialize rest of CPSR
297 cpsr
.daif
= 0xf; // Mask all interrupts
300 miscRegs
[MISCREG_CPSR
] = cpsr
;
303 // Initialize other control registers
304 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
306 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50830;
307 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
308 } else if (haveVirtualization
) {
309 // also MISCREG_SCTLR_EL2 (by mapping)
310 miscRegs
[MISCREG_HSCTLR
] = 0x30c50830;
312 // also MISCREG_SCTLR_EL1 (by mapping)
313 miscRegs
[MISCREG_SCTLR_NS
] = 0x30d00800 | 0x00050030; // RES1 | init
315 miscRegs
[MISCREG_SCR_EL3
] = 1;
320 ISA::initID32(const ArmISAParams
*p
)
322 // Initialize configurable default values
327 else if (highestELIs64
)
328 // Cortex-A57 TRM r0p0 MIDR
331 // Cortex-A15 TRM r0p0 MIDR
334 miscRegs
[MISCREG_MIDR
] = midr
;
335 miscRegs
[MISCREG_MIDR_EL1
] = midr
;
336 miscRegs
[MISCREG_VPIDR
] = midr
;
338 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
339 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
340 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
341 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
342 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
343 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
345 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
346 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
347 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
348 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
350 miscRegs
[MISCREG_ID_ISAR5
] = insertBits(
351 miscRegs
[MISCREG_ID_ISAR5
], 19, 4,
352 haveCrypto
? 0x1112 : 0x0);
356 ISA::initID64(const ArmISAParams
*p
)
358 // Initialize configurable id registers
359 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
360 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
361 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
362 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
363 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
365 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
366 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
367 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
368 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
369 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
370 miscRegs
[MISCREG_ID_AA64MMFR2_EL1
] = p
->id_aa64mmfr2_el1
;
372 miscRegs
[MISCREG_ID_DFR0_EL1
] =
373 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
375 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
378 miscRegs
[MISCREG_ID_AA64ZFR0_EL1
] = 0; // SVEver 0
380 miscRegs
[MISCREG_ZCR_EL3
] = sveVL
- 1;
381 } else if (haveVirtualization
) {
382 miscRegs
[MISCREG_ZCR_EL2
] = sveVL
- 1;
384 miscRegs
[MISCREG_ZCR_EL1
] = sveVL
- 1;
387 // Enforce consistency with system-level settings...
390 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
391 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
392 haveSecurity
? 0x2 : 0x0);
394 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
395 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
396 haveVirtualization
? 0x2 : 0x0);
398 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
399 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 35, 32,
400 haveSVE
? 0x1 : 0x0);
401 // Large ASID support
402 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
403 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
404 haveLargeAsid64
? 0x2 : 0x0);
405 // Physical address size
406 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
407 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
408 encodePhysAddrRange64(physAddrRange
));
410 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = insertBits(
411 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
], 19, 4,
412 haveCrypto
? 0x1112 : 0x0);
414 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = insertBits(
415 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
], 23, 20,
416 haveLSE
? 0x2 : 0x0);
418 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = insertBits(
419 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
], 23, 20,
420 havePAN
? 0x1 : 0x0);
424 ISA::startup(ThreadContext
*tc
)
426 pmu
->setThreadContext(tc
);
429 Gicv3
*gicv3
= dynamic_cast<Gicv3
*>(system
->getGIC());
431 haveGICv3CPUInterface
= true;
432 gicv3CpuInterface
.reset(gicv3
->getCPUInterface(tc
->contextId()));
433 gicv3CpuInterface
->setISA(this);
434 gicv3CpuInterface
->setThreadContext(tc
);
443 ISA::readMiscRegNoEffect(int misc_reg
) const
445 assert(misc_reg
< NumMiscRegs
);
447 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
448 const auto &map
= getMiscIndices(misc_reg
);
449 int lower
= map
.first
, upper
= map
.second
;
450 // NB!: apply architectural masks according to desired register,
451 // despite possibly getting value from different (mapped) register.
452 auto val
= !upper
? miscRegs
[lower
] : ((miscRegs
[lower
] & mask(32))
453 |(miscRegs
[upper
] << 32));
454 if (val
& reg
.res0()) {
455 DPRINTF(MiscRegs
, "Reading MiscReg %s with set res0 bits: %#x\n",
456 miscRegName
[misc_reg
], val
& reg
.res0());
458 if ((val
& reg
.res1()) != reg
.res1()) {
459 DPRINTF(MiscRegs
, "Reading MiscReg %s with clear res1 bits: %#x\n",
460 miscRegName
[misc_reg
], (val
& reg
.res1()) ^ reg
.res1());
462 return (val
& ~reg
.raz()) | reg
.rao(); // enforce raz/rao
467 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
473 if (misc_reg
== MISCREG_CPSR
) {
474 cpsr
= miscRegs
[misc_reg
];
476 cpsr
.j
= pc
.jazelle() ? 1 : 0;
477 cpsr
.t
= pc
.thumb() ? 1 : 0;
482 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
483 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
484 warn("Unimplemented system register %s read.\n",
485 miscRegName
[misc_reg
]);
487 panic("Unimplemented system register %s read.\n",
488 miscRegName
[misc_reg
]);
492 switch (unflattenMiscReg(misc_reg
)) {
495 if (!haveVirtualization
)
500 const uint32_t ones
= (uint32_t)(-1);
502 // Only cp10, cp11, and ase are implemented, nothing else should
503 // be readable? (straight copy from the write code)
504 cpacrMask
.cp10
= ones
;
505 cpacrMask
.cp11
= ones
;
506 cpacrMask
.asedis
= ones
;
508 // Security Extensions may limit the readability of CPACR
510 scr
= readMiscRegNoEffect(MISCREG_SCR
);
511 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
512 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
513 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
514 // NB: Skipping the full loop, here
515 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
516 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
519 RegVal val
= readMiscRegNoEffect(MISCREG_CPACR
);
521 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
522 miscRegName
[misc_reg
], val
);
526 case MISCREG_MPIDR_EL1
:
527 return readMPIDR(system
, tc
);
529 case MISCREG_VMPIDR_EL2
:
530 // top bit defined as RES1
531 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
532 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
533 case MISCREG_REVIDR
: // not implemented, so alias MIDR
535 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
536 scr
= readMiscRegNoEffect(MISCREG_SCR
);
537 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
538 return readMiscRegNoEffect(misc_reg
);
540 return readMiscRegNoEffect(MISCREG_VPIDR
);
543 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
544 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
545 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
546 case MISCREG_AIDR
: // AUX ID set to 0
547 case MISCREG_TCMTR
: // No TCM's
551 warn_once("The clidr register always reports 0 caches.\n");
552 warn_once("clidr LoUIS field of 0b001 to match current "
553 "ARM implementations.\n");
556 warn_once("The ccsidr register isn't implemented and "
557 "always reads as 0.\n");
559 case MISCREG_CTR
: // AArch32, ARMv7, top bit set
560 case MISCREG_CTR_EL0
: // AArch64
562 //all caches have the same line size in gem5
563 //4 byte words in ARM
564 unsigned lineSizeWords
=
565 tc
->getSystemPtr()->cacheLineSize() / 4;
566 unsigned log2LineSizeWords
= 0;
568 while (lineSizeWords
>>= 1) {
573 //log2 of minimun i-cache line size (words)
574 ctr
.iCacheLineSize
= log2LineSizeWords
;
575 //b11 - gem5 uses pipt
576 ctr
.l1IndexPolicy
= 0x3;
577 //log2 of minimum d-cache line size (words)
578 ctr
.dCacheLineSize
= log2LineSizeWords
;
579 //log2 of max reservation size (words)
580 ctr
.erg
= log2LineSizeWords
;
581 //log2 of max writeback size (words)
582 ctr
.cwg
= log2LineSizeWords
;
583 //b100 - gem5 format is ARMv7
589 warn("Not doing anything for miscreg ACTLR\n");
592 case MISCREG_PMXEVTYPER_PMCCFILTR
:
593 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
594 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
595 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
596 return pmu
->readMiscReg(misc_reg
);
599 panic("shouldn't be reading this register seperately\n");
600 case MISCREG_FPSCR_QC
:
601 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
602 case MISCREG_FPSCR_EXC
:
603 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
606 const uint32_t ones
= (uint32_t)(-1);
608 fpscrMask
.ioc
= ones
;
609 fpscrMask
.dzc
= ones
;
610 fpscrMask
.ofc
= ones
;
611 fpscrMask
.ufc
= ones
;
612 fpscrMask
.ixc
= ones
;
613 fpscrMask
.idc
= ones
;
619 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
623 const uint32_t ones
= (uint32_t)(-1);
625 fpscrMask
.len
= ones
;
626 fpscrMask
.fz16
= ones
;
627 fpscrMask
.stride
= ones
;
628 fpscrMask
.rMode
= ones
;
631 fpscrMask
.ahp
= ones
;
632 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
637 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
638 cpsr
.c
= tc
->readCCReg(CCREG_C
);
639 cpsr
.v
= tc
->readCCReg(CCREG_V
);
645 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
650 return tc
->readIntReg(INTREG_SP0
);
654 return tc
->readIntReg(INTREG_SP1
);
658 return tc
->readIntReg(INTREG_SP2
);
662 return miscRegs
[MISCREG_CPSR
] & 0x1;
664 case MISCREG_CURRENTEL
:
666 return miscRegs
[MISCREG_CPSR
] & 0xc;
670 return miscRegs
[MISCREG_CPSR
] & 0x400000;
674 // mostly unimplemented, just set NumCPUs field from sim and return
676 // b00:1CPU to b11:4CPUs
677 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
680 case MISCREG_DBGDIDR
:
681 /* For now just implement the version number.
682 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
685 case MISCREG_DBGDSCRint
:
689 auto ic
= dynamic_cast<ArmISA::Interrupts
*>(
690 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
692 readMiscRegNoEffect(MISCREG_HCR
),
693 readMiscRegNoEffect(MISCREG_CPSR
),
694 readMiscRegNoEffect(MISCREG_SCR
));
696 case MISCREG_ISR_EL1
:
698 auto ic
= dynamic_cast<ArmISA::Interrupts
*>(
699 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
701 readMiscRegNoEffect(MISCREG_HCR_EL2
),
702 readMiscRegNoEffect(MISCREG_CPSR
),
703 readMiscRegNoEffect(MISCREG_SCR_EL3
));
705 case MISCREG_DCZID_EL0
:
706 return 0x04; // DC ZVA clear 64-byte chunks
709 RegVal val
= readMiscRegNoEffect(misc_reg
);
710 // The trap bit associated with CP14 is defined as RAZ
712 // If a CP bit in NSACR is 0 then the corresponding bit in
714 bool secure_lookup
= haveSecurity
&&
715 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
716 readMiscRegNoEffect(MISCREG_CPSR
));
717 if (!secure_lookup
) {
718 RegVal mask
= readMiscRegNoEffect(MISCREG_NSACR
);
719 val
|= (mask
^ 0x7FFF) & 0xBFFF;
721 // Set the bits for unimplemented coprocessors to RAO/WI
725 case MISCREG_HDFAR
: // alias for secure DFAR
726 return readMiscRegNoEffect(MISCREG_DFAR_S
);
727 case MISCREG_HIFAR
: // alias for secure IFAR
728 return readMiscRegNoEffect(MISCREG_IFAR_S
);
730 case MISCREG_ID_PFR0
:
731 // !ThumbEE | !Jazelle | Thumb | ARM
733 case MISCREG_ID_PFR1
:
734 { // Timer | Virti | !M Profile | TrustZone | ARMv4
735 bool haveTimer
= (system
->getGenericTimer() != NULL
);
737 | (haveSecurity
? 0x00000010 : 0x0)
738 | (haveVirtualization
? 0x00001000 : 0x0)
739 | (haveTimer
? 0x00010000 : 0x0);
741 case MISCREG_ID_AA64PFR0_EL1
:
742 return 0x0000000000000002 | // AArch{64,32} supported at EL0
743 0x0000000000000020 | // EL1
744 (haveVirtualization
? 0x0000000000000200 : 0) | // EL2
745 (haveSecurity
? 0x0000000000002000 : 0) | // EL3
746 (haveSVE
? 0x0000000100000000 : 0) | // SVE
747 (haveGICv3CPUInterface
? 0x0000000001000000 : 0);
748 case MISCREG_ID_AA64PFR1_EL1
:
749 return 0; // bits [63:0] RES0 (reserved for future use)
751 // Generic Timer registers
752 case MISCREG_CNTHV_CTL_EL2
:
753 case MISCREG_CNTHV_CVAL_EL2
:
754 case MISCREG_CNTHV_TVAL_EL2
:
755 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
756 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
757 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
758 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
759 return getGenericTimer(tc
).readMiscReg(misc_reg
);
761 case MISCREG_ICC_AP0R0
... MISCREG_ICH_LRC15
:
762 case MISCREG_ICC_PMR_EL1
... MISCREG_ICC_IGRPEN1_EL3
:
763 case MISCREG_ICH_AP0R0_EL2
... MISCREG_ICH_LR15_EL2
:
764 return getGICv3CPUInterface(tc
).readMiscReg(misc_reg
);
770 return readMiscRegNoEffect(misc_reg
);
774 ISA::setMiscRegNoEffect(int misc_reg
, RegVal val
)
776 assert(misc_reg
< NumMiscRegs
);
778 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
779 const auto &map
= getMiscIndices(misc_reg
);
780 int lower
= map
.first
, upper
= map
.second
;
782 auto v
= (val
& ~reg
.wi()) | reg
.rao();
784 miscRegs
[lower
] = bits(v
, 31, 0);
785 miscRegs
[upper
] = bits(v
, 63, 32);
786 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
787 misc_reg
, lower
, upper
, v
);
790 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
796 ISA::setMiscReg(int misc_reg
, RegVal val
, ThreadContext
*tc
)
803 if (misc_reg
== MISCREG_CPSR
) {
807 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
808 int old_mode
= old_cpsr
.mode
;
810 if (old_mode
!= cpsr
.mode
|| cpsr
.il
!= old_cpsr
.il
) {
811 getITBPtr(tc
)->invalidateMiscReg();
812 getDTBPtr(tc
)->invalidateMiscReg();
815 if (cpsr
.pan
!= old_cpsr
.pan
) {
816 getDTBPtr(tc
)->invalidateMiscReg();
819 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
820 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
821 PCState pc
= tc
->pcState();
822 pc
.nextThumb(cpsr
.t
);
823 pc
.nextJazelle(cpsr
.j
);
824 pc
.illegalExec(cpsr
.il
== 1);
826 tc
->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc
) >> 7) - 1);
828 // Follow slightly different semantics if a CheckerCPU object
830 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
832 tc
->pcStateNoRecord(pc
);
838 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
839 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
840 warn("Unimplemented system register %s write with %#x.\n",
841 miscRegName
[misc_reg
], val
);
843 panic("Unimplemented system register %s write with %#x.\n",
844 miscRegName
[misc_reg
], val
);
847 switch (unflattenMiscReg(misc_reg
)) {
851 const uint32_t ones
= (uint32_t)(-1);
853 // Only cp10, cp11, and ase are implemented, nothing else should
855 cpacrMask
.cp10
= ones
;
856 cpacrMask
.cp11
= ones
;
857 cpacrMask
.asedis
= ones
;
859 // Security Extensions may limit the writability of CPACR
861 scr
= readMiscRegNoEffect(MISCREG_SCR
);
862 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
863 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
864 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
865 // NB: Skipping the full loop, here
866 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
867 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
871 RegVal old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
873 newVal
|= old_val
& ~cpacrMask
;
874 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
875 miscRegName
[misc_reg
], newVal
);
878 case MISCREG_CPACR_EL1
:
880 const uint32_t ones
= (uint32_t)(-1);
882 cpacrMask
.tta
= ones
;
883 cpacrMask
.fpen
= ones
;
885 cpacrMask
.zen
= ones
;
888 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
889 miscRegName
[misc_reg
], newVal
);
892 case MISCREG_CPTR_EL2
:
894 const uint32_t ones
= (uint32_t)(-1);
896 cptrMask
.tcpac
= ones
;
904 cptrMask
.res1_13_12_el2
= ones
;
905 cptrMask
.res1_7_0_el2
= ones
;
907 cptrMask
.res1_8_el2
= ones
;
909 cptrMask
.res1_9_el2
= ones
;
911 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
912 miscRegName
[misc_reg
], newVal
);
915 case MISCREG_CPTR_EL3
:
917 const uint32_t ones
= (uint32_t)(-1);
919 cptrMask
.tcpac
= ones
;
926 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
927 miscRegName
[misc_reg
], newVal
);
931 warn_once("The csselr register isn't implemented.\n");
934 case MISCREG_DC_ZVA_Xt
:
935 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
940 const uint32_t ones
= (uint32_t)(-1);
942 fpscrMask
.ioc
= ones
;
943 fpscrMask
.dzc
= ones
;
944 fpscrMask
.ofc
= ones
;
945 fpscrMask
.ufc
= ones
;
946 fpscrMask
.ixc
= ones
;
947 fpscrMask
.idc
= ones
;
948 fpscrMask
.ioe
= ones
;
949 fpscrMask
.dze
= ones
;
950 fpscrMask
.ofe
= ones
;
951 fpscrMask
.ufe
= ones
;
952 fpscrMask
.ixe
= ones
;
953 fpscrMask
.ide
= ones
;
954 fpscrMask
.len
= ones
;
955 fpscrMask
.fz16
= ones
;
956 fpscrMask
.stride
= ones
;
957 fpscrMask
.rMode
= ones
;
960 fpscrMask
.ahp
= ones
;
966 newVal
= (newVal
& (uint32_t)fpscrMask
) |
967 (readMiscRegNoEffect(MISCREG_FPSCR
) &
968 ~(uint32_t)fpscrMask
);
969 tc
->getDecoderPtr()->setContext(newVal
);
974 const uint32_t ones
= (uint32_t)(-1);
976 fpscrMask
.ioc
= ones
;
977 fpscrMask
.dzc
= ones
;
978 fpscrMask
.ofc
= ones
;
979 fpscrMask
.ufc
= ones
;
980 fpscrMask
.ixc
= ones
;
981 fpscrMask
.idc
= ones
;
987 newVal
= (newVal
& (uint32_t)fpscrMask
) |
988 (readMiscRegNoEffect(MISCREG_FPSCR
) &
989 ~(uint32_t)fpscrMask
);
990 misc_reg
= MISCREG_FPSCR
;
995 const uint32_t ones
= (uint32_t)(-1);
997 fpscrMask
.len
= ones
;
998 fpscrMask
.fz16
= ones
;
999 fpscrMask
.stride
= ones
;
1000 fpscrMask
.rMode
= ones
;
1001 fpscrMask
.fz
= ones
;
1002 fpscrMask
.dn
= ones
;
1003 fpscrMask
.ahp
= ones
;
1004 newVal
= (newVal
& (uint32_t)fpscrMask
) |
1005 (readMiscRegNoEffect(MISCREG_FPSCR
) &
1006 ~(uint32_t)fpscrMask
);
1007 misc_reg
= MISCREG_FPSCR
;
1010 case MISCREG_CPSR_Q
:
1012 assert(!(newVal
& ~CpsrMaskQ
));
1013 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1014 misc_reg
= MISCREG_CPSR
;
1017 case MISCREG_FPSCR_QC
:
1019 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1020 (newVal
& FpscrQcMask
);
1021 misc_reg
= MISCREG_FPSCR
;
1024 case MISCREG_FPSCR_EXC
:
1026 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1027 (newVal
& FpscrExcMask
);
1028 misc_reg
= MISCREG_FPSCR
;
1033 // vfpv3 architecture, section B.6.1 of DDI04068
1034 // bit 29 - valid only if fpexc[31] is 0
1035 const uint32_t fpexcMask
= 0x60000000;
1036 newVal
= (newVal
& fpexcMask
) |
1037 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1042 if (!haveVirtualization
)
1047 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1048 const uint32_t ifsrMask
=
1049 mask(31, 13) | mask(11, 11) | mask(8, 6);
1050 newVal
= newVal
& ~ifsrMask
;
1055 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1056 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1057 newVal
= newVal
& ~dfsrMask
;
1060 case MISCREG_AMAIR0
:
1061 case MISCREG_AMAIR1
:
1063 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1064 // Valid only with LPAE
1067 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1071 getITBPtr(tc
)->invalidateMiscReg();
1072 getDTBPtr(tc
)->invalidateMiscReg();
1076 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1077 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1079 MiscRegIndex sctlr_idx
;
1080 if (haveSecurity
&& !highestELIs64
&& !scr
.ns
) {
1081 sctlr_idx
= MISCREG_SCTLR_S
;
1083 sctlr_idx
= MISCREG_SCTLR_NS
;
1086 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1087 SCTLR new_sctlr
= newVal
;
1088 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1089 miscRegs
[sctlr_idx
] = (RegVal
)new_sctlr
;
1090 getITBPtr(tc
)->invalidateMiscReg();
1091 getDTBPtr(tc
)->invalidateMiscReg();
1094 case MISCREG_ID_PFR0
:
1095 case MISCREG_ID_PFR1
:
1096 case MISCREG_ID_DFR0
:
1097 case MISCREG_ID_MMFR0
:
1098 case MISCREG_ID_MMFR1
:
1099 case MISCREG_ID_MMFR2
:
1100 case MISCREG_ID_MMFR3
:
1101 case MISCREG_ID_ISAR0
:
1102 case MISCREG_ID_ISAR1
:
1103 case MISCREG_ID_ISAR2
:
1104 case MISCREG_ID_ISAR3
:
1105 case MISCREG_ID_ISAR4
:
1106 case MISCREG_ID_ISAR5
:
1114 case MISCREG_ID_AA64AFR0_EL1
:
1115 case MISCREG_ID_AA64AFR1_EL1
:
1116 case MISCREG_ID_AA64DFR0_EL1
:
1117 case MISCREG_ID_AA64DFR1_EL1
:
1118 case MISCREG_ID_AA64ISAR0_EL1
:
1119 case MISCREG_ID_AA64ISAR1_EL1
:
1120 case MISCREG_ID_AA64MMFR0_EL1
:
1121 case MISCREG_ID_AA64MMFR1_EL1
:
1122 case MISCREG_ID_AA64MMFR2_EL1
:
1123 case MISCREG_ID_AA64PFR0_EL1
:
1124 case MISCREG_ID_AA64PFR1_EL1
:
1125 // ID registers are constants.
1128 // TLB Invalidate All
1129 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1132 scr
= readMiscReg(MISCREG_SCR
, tc
);
1134 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1138 // TLB Invalidate All, Inner Shareable
1139 case MISCREG_TLBIALLIS
:
1142 scr
= readMiscReg(MISCREG_SCR
, tc
);
1144 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1145 tlbiOp
.broadcast(tc
);
1148 // Instruction TLB Invalidate All
1149 case MISCREG_ITLBIALL
:
1152 scr
= readMiscReg(MISCREG_SCR
, tc
);
1154 ITLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1158 // Data TLB Invalidate All
1159 case MISCREG_DTLBIALL
:
1162 scr
= readMiscReg(MISCREG_SCR
, tc
);
1164 DTLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1168 // TLB Invalidate by VA
1169 // mcr tlbimval(is) is invalidating all matching entries
1170 // regardless of the level of lookup, since in gem5 we cache
1171 // in the tlb the last level of lookup only.
1172 case MISCREG_TLBIMVA
:
1173 case MISCREG_TLBIMVAL
:
1176 scr
= readMiscReg(MISCREG_SCR
, tc
);
1179 haveSecurity
&& !scr
.ns
,
1180 mbits(newVal
, 31, 12),
1186 // TLB Invalidate by VA, Inner Shareable
1187 case MISCREG_TLBIMVAIS
:
1188 case MISCREG_TLBIMVALIS
:
1191 scr
= readMiscReg(MISCREG_SCR
, tc
);
1194 haveSecurity
&& !scr
.ns
,
1195 mbits(newVal
, 31, 12),
1198 tlbiOp
.broadcast(tc
);
1201 // TLB Invalidate by ASID match
1202 case MISCREG_TLBIASID
:
1205 scr
= readMiscReg(MISCREG_SCR
, tc
);
1207 TLBIASID
tlbiOp(EL1
,
1208 haveSecurity
&& !scr
.ns
,
1214 // TLB Invalidate by ASID match, Inner Shareable
1215 case MISCREG_TLBIASIDIS
:
1218 scr
= readMiscReg(MISCREG_SCR
, tc
);
1220 TLBIASID
tlbiOp(EL1
,
1221 haveSecurity
&& !scr
.ns
,
1224 tlbiOp
.broadcast(tc
);
1227 // mcr tlbimvaal(is) is invalidating all matching entries
1228 // regardless of the level of lookup, since in gem5 we cache
1229 // in the tlb the last level of lookup only.
1230 // TLB Invalidate by VA, All ASID
1231 case MISCREG_TLBIMVAA
:
1232 case MISCREG_TLBIMVAAL
:
1235 scr
= readMiscReg(MISCREG_SCR
, tc
);
1237 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1238 mbits(newVal
, 31,12));
1243 // TLB Invalidate by VA, All ASID, Inner Shareable
1244 case MISCREG_TLBIMVAAIS
:
1245 case MISCREG_TLBIMVAALIS
:
1248 scr
= readMiscReg(MISCREG_SCR
, tc
);
1250 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1251 mbits(newVal
, 31,12));
1253 tlbiOp
.broadcast(tc
);
1256 // mcr tlbimvalh(is) is invalidating all matching entries
1257 // regardless of the level of lookup, since in gem5 we cache
1258 // in the tlb the last level of lookup only.
1259 // TLB Invalidate by VA, Hyp mode
1260 case MISCREG_TLBIMVAH
:
1261 case MISCREG_TLBIMVALH
:
1264 scr
= readMiscReg(MISCREG_SCR
, tc
);
1266 TLBIMVAA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1267 mbits(newVal
, 31,12));
1272 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1273 case MISCREG_TLBIMVAHIS
:
1274 case MISCREG_TLBIMVALHIS
:
1277 scr
= readMiscReg(MISCREG_SCR
, tc
);
1279 TLBIMVAA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1280 mbits(newVal
, 31,12));
1282 tlbiOp
.broadcast(tc
);
1285 // mcr tlbiipas2l(is) is invalidating all matching entries
1286 // regardless of the level of lookup, since in gem5 we cache
1287 // in the tlb the last level of lookup only.
1288 // TLB Invalidate by Intermediate Physical Address, Stage 2
1289 case MISCREG_TLBIIPAS2
:
1290 case MISCREG_TLBIIPAS2L
:
1293 scr
= readMiscReg(MISCREG_SCR
, tc
);
1296 haveSecurity
&& !scr
.ns
,
1297 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1302 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1304 case MISCREG_TLBIIPAS2IS
:
1305 case MISCREG_TLBIIPAS2LIS
:
1308 scr
= readMiscReg(MISCREG_SCR
, tc
);
1311 haveSecurity
&& !scr
.ns
,
1312 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1314 tlbiOp
.broadcast(tc
);
1317 // Instruction TLB Invalidate by VA
1318 case MISCREG_ITLBIMVA
:
1321 scr
= readMiscReg(MISCREG_SCR
, tc
);
1323 ITLBIMVA
tlbiOp(EL1
,
1324 haveSecurity
&& !scr
.ns
,
1325 mbits(newVal
, 31, 12),
1331 // Data TLB Invalidate by VA
1332 case MISCREG_DTLBIMVA
:
1335 scr
= readMiscReg(MISCREG_SCR
, tc
);
1337 DTLBIMVA
tlbiOp(EL1
,
1338 haveSecurity
&& !scr
.ns
,
1339 mbits(newVal
, 31, 12),
1345 // Instruction TLB Invalidate by ASID match
1346 case MISCREG_ITLBIASID
:
1349 scr
= readMiscReg(MISCREG_SCR
, tc
);
1351 ITLBIASID
tlbiOp(EL1
,
1352 haveSecurity
&& !scr
.ns
,
1358 // Data TLB Invalidate by ASID match
1359 case MISCREG_DTLBIASID
:
1362 scr
= readMiscReg(MISCREG_SCR
, tc
);
1364 DTLBIASID
tlbiOp(EL1
,
1365 haveSecurity
&& !scr
.ns
,
1371 // TLB Invalidate All, Non-Secure Non-Hyp
1372 case MISCREG_TLBIALLNSNH
:
1376 TLBIALLN
tlbiOp(EL1
);
1380 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1381 case MISCREG_TLBIALLNSNHIS
:
1385 TLBIALLN
tlbiOp(EL1
);
1386 tlbiOp
.broadcast(tc
);
1389 // TLB Invalidate All, Hyp mode
1390 case MISCREG_TLBIALLH
:
1394 TLBIALLN
tlbiOp(EL2
);
1398 // TLB Invalidate All, Hyp mode, Inner Shareable
1399 case MISCREG_TLBIALLHIS
:
1403 TLBIALLN
tlbiOp(EL2
);
1404 tlbiOp
.broadcast(tc
);
1407 // AArch64 TLB Invalidate All, EL3
1408 case MISCREG_TLBI_ALLE3
:
1412 TLBIALL
tlbiOp(EL3
, true);
1416 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1417 case MISCREG_TLBI_ALLE3IS
:
1421 TLBIALL
tlbiOp(EL3
, true);
1422 tlbiOp
.broadcast(tc
);
1425 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1426 case MISCREG_TLBI_ALLE2
:
1427 case MISCREG_TLBI_ALLE2IS
:
1430 scr
= readMiscReg(MISCREG_SCR
, tc
);
1432 TLBIALL
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
);
1436 // AArch64 TLB Invalidate All, EL1
1437 case MISCREG_TLBI_ALLE1
:
1438 case MISCREG_TLBI_VMALLE1
:
1439 case MISCREG_TLBI_VMALLS12E1
:
1440 // @todo: handle VMID and stage 2 to enable Virtualization
1443 scr
= readMiscReg(MISCREG_SCR
, tc
);
1445 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1449 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1450 case MISCREG_TLBI_ALLE1IS
:
1451 case MISCREG_TLBI_VMALLE1IS
:
1452 case MISCREG_TLBI_VMALLS12E1IS
:
1453 // @todo: handle VMID and stage 2 to enable Virtualization
1456 scr
= readMiscReg(MISCREG_SCR
, tc
);
1458 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1459 tlbiOp
.broadcast(tc
);
1462 // VAEx(IS) and VALEx(IS) are the same because TLBs
1463 // only store entries
1464 // from the last level of translation table walks
1465 // @todo: handle VMID to enable Virtualization
1466 // AArch64 TLB Invalidate by VA, EL3
1467 case MISCREG_TLBI_VAE3_Xt
:
1468 case MISCREG_TLBI_VALE3_Xt
:
1472 TLBIMVA
tlbiOp(EL3
, true,
1473 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1478 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1479 case MISCREG_TLBI_VAE3IS_Xt
:
1480 case MISCREG_TLBI_VALE3IS_Xt
:
1484 TLBIMVA
tlbiOp(EL3
, true,
1485 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1488 tlbiOp
.broadcast(tc
);
1491 // AArch64 TLB Invalidate by VA, EL2
1492 case MISCREG_TLBI_VAE2_Xt
:
1493 case MISCREG_TLBI_VALE2_Xt
:
1496 scr
= readMiscReg(MISCREG_SCR
, tc
);
1498 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1499 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1504 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1505 case MISCREG_TLBI_VAE2IS_Xt
:
1506 case MISCREG_TLBI_VALE2IS_Xt
:
1509 scr
= readMiscReg(MISCREG_SCR
, tc
);
1511 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1512 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1515 tlbiOp
.broadcast(tc
);
1518 // AArch64 TLB Invalidate by VA, EL1
1519 case MISCREG_TLBI_VAE1_Xt
:
1520 case MISCREG_TLBI_VALE1_Xt
:
1523 scr
= readMiscReg(MISCREG_SCR
, tc
);
1524 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1525 bits(newVal
, 55, 48);
1527 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1528 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1534 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1535 case MISCREG_TLBI_VAE1IS_Xt
:
1536 case MISCREG_TLBI_VALE1IS_Xt
:
1539 scr
= readMiscReg(MISCREG_SCR
, tc
);
1540 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1541 bits(newVal
, 55, 48);
1543 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1544 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1547 tlbiOp
.broadcast(tc
);
1550 // AArch64 TLB Invalidate by ASID, EL1
1551 // @todo: handle VMID to enable Virtualization
1552 case MISCREG_TLBI_ASIDE1_Xt
:
1555 scr
= readMiscReg(MISCREG_SCR
, tc
);
1556 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1557 bits(newVal
, 55, 48);
1559 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1563 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1564 case MISCREG_TLBI_ASIDE1IS_Xt
:
1567 scr
= readMiscReg(MISCREG_SCR
, tc
);
1568 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1569 bits(newVal
, 55, 48);
1571 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1572 tlbiOp
.broadcast(tc
);
1575 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1576 // entries from the last level of translation table walks
1577 // AArch64 TLB Invalidate by VA, All ASID, EL1
1578 case MISCREG_TLBI_VAAE1_Xt
:
1579 case MISCREG_TLBI_VAALE1_Xt
:
1582 scr
= readMiscReg(MISCREG_SCR
, tc
);
1584 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1585 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12);
1590 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1591 case MISCREG_TLBI_VAAE1IS_Xt
:
1592 case MISCREG_TLBI_VAALE1IS_Xt
:
1595 scr
= readMiscReg(MISCREG_SCR
, tc
);
1597 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1598 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12);
1600 tlbiOp
.broadcast(tc
);
1603 // AArch64 TLB Invalidate by Intermediate Physical Address,
1605 case MISCREG_TLBI_IPAS2E1_Xt
:
1606 case MISCREG_TLBI_IPAS2LE1_Xt
:
1609 scr
= readMiscReg(MISCREG_SCR
, tc
);
1611 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1612 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1617 // AArch64 TLB Invalidate by Intermediate Physical Address,
1618 // Stage 2, EL1, Inner Shareable
1619 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1620 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1623 scr
= readMiscReg(MISCREG_SCR
, tc
);
1625 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1626 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1628 tlbiOp
.broadcast(tc
);
1632 warn("Not doing anything for write of miscreg ACTLR\n");
1635 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1636 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1637 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1638 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1639 pmu
->setMiscReg(misc_reg
, newVal
);
1643 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1647 newVal
&= ~((uint32_t) hstrMask
);
1652 // If a CP bit in NSACR is 0 then the corresponding bit in
1653 // HCPTR is RAO/WI. Same applies to NSASEDIS
1654 secure_lookup
= haveSecurity
&&
1655 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1656 readMiscRegNoEffect(MISCREG_CPSR
));
1657 if (!secure_lookup
) {
1658 RegVal oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1660 (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1661 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1665 case MISCREG_HDFAR
: // alias for secure DFAR
1666 misc_reg
= MISCREG_DFAR_S
;
1668 case MISCREG_HIFAR
: // alias for secure IFAR
1669 misc_reg
= MISCREG_IFAR_S
;
1671 case MISCREG_ATS1CPR
:
1672 case MISCREG_ATS1CPW
:
1673 case MISCREG_ATS1CUR
:
1674 case MISCREG_ATS1CUW
:
1675 case MISCREG_ATS12NSOPR
:
1676 case MISCREG_ATS12NSOPW
:
1677 case MISCREG_ATS12NSOUR
:
1678 case MISCREG_ATS12NSOUW
:
1679 case MISCREG_ATS1HR
:
1680 case MISCREG_ATS1HW
:
1682 Request::Flags flags
= 0;
1683 BaseTLB::Mode mode
= BaseTLB::Read
;
1684 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1687 case MISCREG_ATS1CPR
:
1688 flags
= TLB::MustBeOne
;
1689 tranType
= TLB::S1CTran
;
1690 mode
= BaseTLB::Read
;
1692 case MISCREG_ATS1CPW
:
1693 flags
= TLB::MustBeOne
;
1694 tranType
= TLB::S1CTran
;
1695 mode
= BaseTLB::Write
;
1697 case MISCREG_ATS1CUR
:
1698 flags
= TLB::MustBeOne
| TLB::UserMode
;
1699 tranType
= TLB::S1CTran
;
1700 mode
= BaseTLB::Read
;
1702 case MISCREG_ATS1CUW
:
1703 flags
= TLB::MustBeOne
| TLB::UserMode
;
1704 tranType
= TLB::S1CTran
;
1705 mode
= BaseTLB::Write
;
1707 case MISCREG_ATS12NSOPR
:
1709 panic("Security Extensions required for ATS12NSOPR");
1710 flags
= TLB::MustBeOne
;
1711 tranType
= TLB::S1S2NsTran
;
1712 mode
= BaseTLB::Read
;
1714 case MISCREG_ATS12NSOPW
:
1716 panic("Security Extensions required for ATS12NSOPW");
1717 flags
= TLB::MustBeOne
;
1718 tranType
= TLB::S1S2NsTran
;
1719 mode
= BaseTLB::Write
;
1721 case MISCREG_ATS12NSOUR
:
1723 panic("Security Extensions required for ATS12NSOUR");
1724 flags
= TLB::MustBeOne
| TLB::UserMode
;
1725 tranType
= TLB::S1S2NsTran
;
1726 mode
= BaseTLB::Read
;
1728 case MISCREG_ATS12NSOUW
:
1730 panic("Security Extensions required for ATS12NSOUW");
1731 flags
= TLB::MustBeOne
| TLB::UserMode
;
1732 tranType
= TLB::S1S2NsTran
;
1733 mode
= BaseTLB::Write
;
1735 case MISCREG_ATS1HR
: // only really useful from secure mode.
1736 flags
= TLB::MustBeOne
;
1737 tranType
= TLB::HypMode
;
1738 mode
= BaseTLB::Read
;
1740 case MISCREG_ATS1HW
:
1741 flags
= TLB::MustBeOne
;
1742 tranType
= TLB::HypMode
;
1743 mode
= BaseTLB::Write
;
1746 // If we're in timing mode then doing the translation in
1747 // functional mode then we're slightly distorting performance
1748 // results obtained from simulations. The translation should be
1749 // done in the same mode the core is running in. NOTE: This
1750 // can't be an atomic translation because that causes problems
1751 // with unexpected atomic snoop requests.
1752 warn("Translating via %s in functional mode! Fix Me!\n",
1753 miscRegName
[misc_reg
]);
1755 auto req
= std::make_shared
<Request
>(
1756 0, val
, 0, flags
, Request::funcMasterId
,
1757 tc
->pcState().pc(), tc
->contextId());
1759 fault
= getDTBPtr(tc
)->translateFunctional(
1760 req
, tc
, mode
, tranType
);
1762 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1763 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1766 if (fault
== NoFault
) {
1767 Addr paddr
= req
->getPaddr();
1768 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1769 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1770 newVal
= (paddr
& mask(39, 12)) |
1771 (getDTBPtr(tc
)->getAttr());
1773 newVal
= (paddr
& 0xfffff000) |
1774 (getDTBPtr(tc
)->getAttr());
1777 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1780 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1781 armFault
->update(tc
);
1782 // Set fault bit and FSR
1783 FSR fsr
= armFault
->getFsr(tc
);
1785 newVal
= ((fsr
>> 9) & 1) << 11;
1787 // LPAE - rearange fault status
1788 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1790 // VMSA - rearange fault status
1791 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1792 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1793 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1795 newVal
|= 0x1; // F bit
1796 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1797 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1799 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1802 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1807 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1808 const uint32_t ones
= (uint32_t)(-1);
1809 TTBCR ttbcrMask
= 0;
1810 TTBCR ttbcrNew
= newVal
;
1812 // ARM DDI 0406C.b, ARMv7-32
1813 ttbcrMask
.n
= ones
; // T0SZ
1815 ttbcrMask
.pd0
= ones
;
1816 ttbcrMask
.pd1
= ones
;
1818 ttbcrMask
.epd0
= ones
;
1819 ttbcrMask
.irgn0
= ones
;
1820 ttbcrMask
.orgn0
= ones
;
1821 ttbcrMask
.sh0
= ones
;
1822 ttbcrMask
.ps
= ones
; // T1SZ
1823 ttbcrMask
.a1
= ones
;
1824 ttbcrMask
.epd1
= ones
;
1825 ttbcrMask
.irgn1
= ones
;
1826 ttbcrMask
.orgn1
= ones
;
1827 ttbcrMask
.sh1
= ones
;
1829 ttbcrMask
.eae
= ones
;
1831 if (haveLPAE
&& ttbcrNew
.eae
) {
1832 newVal
= newVal
& ttbcrMask
;
1834 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1836 // Invalidate TLB MiscReg
1837 getITBPtr(tc
)->invalidateMiscReg();
1838 getDTBPtr(tc
)->invalidateMiscReg();
1844 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1847 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1848 // ARMv8 AArch32 bit 63-56 only
1849 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1850 newVal
= (newVal
& (~ttbrMask
));
1853 // Invalidate TLB MiscReg
1854 getITBPtr(tc
)->invalidateMiscReg();
1855 getDTBPtr(tc
)->invalidateMiscReg();
1858 case MISCREG_SCTLR_EL1
:
1859 case MISCREG_CONTEXTIDR
:
1866 case MISCREG_SCR_EL3
:
1867 case MISCREG_HCR_EL2
:
1868 case MISCREG_TCR_EL1
:
1869 case MISCREG_TCR_EL2
:
1870 case MISCREG_TCR_EL3
:
1871 case MISCREG_SCTLR_EL2
:
1872 case MISCREG_SCTLR_EL3
:
1873 case MISCREG_HSCTLR
:
1874 case MISCREG_TTBR0_EL1
:
1875 case MISCREG_TTBR1_EL1
:
1876 case MISCREG_TTBR0_EL2
:
1877 case MISCREG_TTBR1_EL2
:
1878 case MISCREG_TTBR0_EL3
:
1879 getITBPtr(tc
)->invalidateMiscReg();
1880 getDTBPtr(tc
)->invalidateMiscReg();
1886 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1887 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1888 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1893 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1894 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1896 misc_reg
= MISCREG_CPSR
;
1899 case MISCREG_SP_EL0
:
1900 tc
->setIntReg(INTREG_SP0
, newVal
);
1902 case MISCREG_SP_EL1
:
1903 tc
->setIntReg(INTREG_SP1
, newVal
);
1905 case MISCREG_SP_EL2
:
1906 tc
->setIntReg(INTREG_SP2
, newVal
);
1910 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1911 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1913 misc_reg
= MISCREG_CPSR
;
1916 case MISCREG_CURRENTEL
:
1918 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1919 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1921 misc_reg
= MISCREG_CPSR
;
1926 // PAN is affecting data accesses
1927 getDTBPtr(tc
)->invalidateMiscReg();
1929 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1930 cpsr
.pan
= (uint8_t) ((CPSR
) newVal
).pan
;
1932 misc_reg
= MISCREG_CPSR
;
1935 case MISCREG_AT_S1E1R_Xt
:
1936 case MISCREG_AT_S1E1W_Xt
:
1937 case MISCREG_AT_S1E0R_Xt
:
1938 case MISCREG_AT_S1E0W_Xt
:
1939 case MISCREG_AT_S1E2R_Xt
:
1940 case MISCREG_AT_S1E2W_Xt
:
1941 case MISCREG_AT_S12E1R_Xt
:
1942 case MISCREG_AT_S12E1W_Xt
:
1943 case MISCREG_AT_S12E0R_Xt
:
1944 case MISCREG_AT_S12E0W_Xt
:
1945 case MISCREG_AT_S1E3R_Xt
:
1946 case MISCREG_AT_S1E3W_Xt
:
1948 RequestPtr req
= std::make_shared
<Request
>();
1949 Request::Flags flags
= 0;
1950 BaseTLB::Mode mode
= BaseTLB::Read
;
1951 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1954 case MISCREG_AT_S1E1R_Xt
:
1955 flags
= TLB::MustBeOne
;
1956 tranType
= TLB::S1E1Tran
;
1957 mode
= BaseTLB::Read
;
1959 case MISCREG_AT_S1E1W_Xt
:
1960 flags
= TLB::MustBeOne
;
1961 tranType
= TLB::S1E1Tran
;
1962 mode
= BaseTLB::Write
;
1964 case MISCREG_AT_S1E0R_Xt
:
1965 flags
= TLB::MustBeOne
| TLB::UserMode
;
1966 tranType
= TLB::S1E0Tran
;
1967 mode
= BaseTLB::Read
;
1969 case MISCREG_AT_S1E0W_Xt
:
1970 flags
= TLB::MustBeOne
| TLB::UserMode
;
1971 tranType
= TLB::S1E0Tran
;
1972 mode
= BaseTLB::Write
;
1974 case MISCREG_AT_S1E2R_Xt
:
1975 flags
= TLB::MustBeOne
;
1976 tranType
= TLB::S1E2Tran
;
1977 mode
= BaseTLB::Read
;
1979 case MISCREG_AT_S1E2W_Xt
:
1980 flags
= TLB::MustBeOne
;
1981 tranType
= TLB::S1E2Tran
;
1982 mode
= BaseTLB::Write
;
1984 case MISCREG_AT_S12E0R_Xt
:
1985 flags
= TLB::MustBeOne
| TLB::UserMode
;
1986 tranType
= TLB::S12E0Tran
;
1987 mode
= BaseTLB::Read
;
1989 case MISCREG_AT_S12E0W_Xt
:
1990 flags
= TLB::MustBeOne
| TLB::UserMode
;
1991 tranType
= TLB::S12E0Tran
;
1992 mode
= BaseTLB::Write
;
1994 case MISCREG_AT_S12E1R_Xt
:
1995 flags
= TLB::MustBeOne
;
1996 tranType
= TLB::S12E1Tran
;
1997 mode
= BaseTLB::Read
;
1999 case MISCREG_AT_S12E1W_Xt
:
2000 flags
= TLB::MustBeOne
;
2001 tranType
= TLB::S12E1Tran
;
2002 mode
= BaseTLB::Write
;
2004 case MISCREG_AT_S1E3R_Xt
:
2005 flags
= TLB::MustBeOne
;
2006 tranType
= TLB::S1E3Tran
;
2007 mode
= BaseTLB::Read
;
2009 case MISCREG_AT_S1E3W_Xt
:
2010 flags
= TLB::MustBeOne
;
2011 tranType
= TLB::S1E3Tran
;
2012 mode
= BaseTLB::Write
;
2015 // If we're in timing mode then doing the translation in
2016 // functional mode then we're slightly distorting performance
2017 // results obtained from simulations. The translation should be
2018 // done in the same mode the core is running in. NOTE: This
2019 // can't be an atomic translation because that causes problems
2020 // with unexpected atomic snoop requests.
2021 warn("Translating via %s in functional mode! Fix Me!\n",
2022 miscRegName
[misc_reg
]);
2024 req
->setVirt(0, val
, 0, flags
, Request::funcMasterId
,
2025 tc
->pcState().pc());
2026 req
->setContext(tc
->contextId());
2027 fault
= getDTBPtr(tc
)->translateFunctional(req
, tc
, mode
,
2031 if (fault
== NoFault
) {
2032 Addr paddr
= req
->getPaddr();
2033 uint64_t attr
= getDTBPtr(tc
)->getAttr();
2034 uint64_t attr1
= attr
>> 56;
2035 if (!attr1
|| attr1
==0x44) {
2037 attr
&= ~ uint64_t(0x80);
2039 newVal
= (paddr
& mask(47, 12)) | attr
;
2041 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2044 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
2045 armFault
->update(tc
);
2046 // Set fault bit and FSR
2047 FSR fsr
= armFault
->getFsr(tc
);
2049 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
2050 if (cpsr
.width
) { // AArch32
2051 newVal
= ((fsr
>> 9) & 1) << 11;
2052 // rearrange fault status
2053 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
2054 newVal
|= 0x1; // F bit
2055 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
2056 newVal
|= armFault
->isStage2() ? 0x200 : 0;
2058 newVal
= 1; // F bit
2059 newVal
|= fsr
<< 1; // FST
2060 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
2061 newVal
|= armFault
->isStage2() ? 1 << 8 : 0; // PTW
2062 newVal
|= armFault
->isStage2() ? 1 << 9 : 0; // S
2063 newVal
|= 1 << 11; // RES1
2066 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2069 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
2072 case MISCREG_SPSR_EL3
:
2073 case MISCREG_SPSR_EL2
:
2074 case MISCREG_SPSR_EL1
:
2076 RegVal spsr_mask
= havePAN
?
2077 ~(0x5 << 21) : ~(0x7 << 21);
2079 newVal
= val
& spsr_mask
;
2082 case MISCREG_L2CTLR
:
2083 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2084 miscRegName
[misc_reg
], uint32_t(val
));
2087 // Generic Timer registers
2088 case MISCREG_CNTHV_CTL_EL2
:
2089 case MISCREG_CNTHV_CVAL_EL2
:
2090 case MISCREG_CNTHV_TVAL_EL2
:
2091 case MISCREG_CNTFRQ
... MISCREG_CNTHP_CTL
:
2092 case MISCREG_CNTPCT
... MISCREG_CNTHP_CVAL
:
2093 case MISCREG_CNTKCTL_EL1
... MISCREG_CNTV_CVAL_EL0
:
2094 case MISCREG_CNTVOFF_EL2
... MISCREG_CNTPS_CVAL_EL1
:
2095 getGenericTimer(tc
).setMiscReg(misc_reg
, newVal
);
2097 case MISCREG_ICC_AP0R0
... MISCREG_ICH_LRC15
:
2098 case MISCREG_ICC_PMR_EL1
... MISCREG_ICC_IGRPEN1_EL3
:
2099 case MISCREG_ICH_AP0R0_EL2
... MISCREG_ICH_LR15_EL2
:
2100 getGICv3CPUInterface(tc
).setMiscReg(misc_reg
, newVal
);
2102 case MISCREG_ZCR_EL3
:
2103 case MISCREG_ZCR_EL2
:
2104 case MISCREG_ZCR_EL1
:
2105 tc
->getDecoderPtr()->setSveLen(
2106 (getCurSveVecLenInBits(tc
) >> 7) - 1);
2110 setMiscRegNoEffect(misc_reg
, newVal
);
2114 ISA::getGenericTimer(ThreadContext
*tc
)
2116 // We only need to create an ISA interface the first time we try
2117 // to access the timer.
2119 return *timer
.get();
2122 GenericTimer
*generic_timer(system
->getGenericTimer());
2123 if (!generic_timer
) {
2124 panic("Trying to get a generic timer from a system that hasn't "
2125 "been configured to use a generic timer.\n");
2128 timer
.reset(new GenericTimerISA(*generic_timer
, tc
->contextId()));
2129 timer
->setThreadContext(tc
);
2131 return *timer
.get();
2135 ISA::getGICv3CPUInterface(ThreadContext
*tc
)
2137 panic_if(!gicv3CpuInterface
, "GICV3 cpu interface is not registered!");
2138 return *gicv3CpuInterface
.get();
2142 ISA::getCurSveVecLenInBits(ThreadContext
*tc
) const
2149 "A ThreadContext is needed to determine the SVE vector length "
2150 "in full-system mode");
2152 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
2153 ExceptionLevel el
= (ExceptionLevel
) (uint8_t) cpsr
.el
;
2157 if (el
== EL1
|| (el
== EL0
&& !ELIsInHost(tc
, el
))) {
2158 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL1
]).len
;
2161 if (el
== EL2
|| (el
== EL0
&& ELIsInHost(tc
, el
))) {
2162 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL2
]).len
;
2163 } else if (haveVirtualization
&& !inSecureState(tc
) &&
2164 (el
== EL0
|| el
== EL1
)) {
2167 static_cast<unsigned>(
2168 static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL2
]).len
));
2172 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL3
]).len
;
2173 } else if (haveSecurity
) {
2176 static_cast<unsigned>(
2177 static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL3
]).len
));
2180 len
= std::min(len
, sveVL
- 1);
2182 return (len
+ 1) * 128;
2186 ISA::zeroSveVecRegUpperPart(VecRegContainer
&vc
, unsigned eCount
)
2188 auto vv
= vc
.as
<uint64_t>();
2189 for (int i
= 2; i
< eCount
; ++i
) {
2194 ISA::MiscRegLUTEntryInitializer::chain
2195 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem
*const sys
) const
2197 switch (FullSystem
? sys
->highestEL() : EL1
) {
2199 case EL1
: priv(); break;
2200 case EL2
: hyp(); break;
2201 case EL3
: mon(); break;
2206 } // namespace ArmISA
2209 ArmISAParams::create()
2211 return new ArmISA::ISA(this);