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misc: Merge branch v20.1.0.3 hotfix into develop
[gem5.git] / src / arch / arm / isa.cc
1 /*
2 * Copyright (c) 2010-2021 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include "arch/arm/isa.hh"
39
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/htm.hh"
42 #include "arch/arm/interrupts.hh"
43 #include "arch/arm/mmu.hh"
44 #include "arch/arm/pmu.hh"
45 #include "arch/arm/self_debug.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlbi_op.hh"
48 #include "cpu/base.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "debug/Arm.hh"
51 #include "debug/MiscRegs.hh"
52 #include "dev/arm/generic_timer.hh"
53 #include "dev/arm/gic_v3.hh"
54 #include "dev/arm/gic_v3_cpu_interface.hh"
55 #include "params/ArmISA.hh"
56 #include "sim/faults.hh"
57 #include "sim/stat_control.hh"
58 #include "sim/system.hh"
59
60 namespace ArmISA
61 {
62
63 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
64 _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
65 pmu(p.pmu), impdefAsNop(p.impdef_nop),
66 afterStartup(false)
67 {
68 miscRegs[MISCREG_SCTLR_RST] = 0;
69
70 // Hook up a dummy device if we haven't been configured with a
71 // real PMU. By using a dummy device, we don't need to check that
72 // the PMU exist every time we try to access a PMU register.
73 if (!pmu)
74 pmu = &dummyDevice;
75
76 // Give all ISA devices a pointer to this ISA
77 pmu->setISA(this);
78
79 system = dynamic_cast<ArmSystem *>(p.system);
80
81 // Cache system-level properties
82 if (FullSystem && system) {
83 highestELIs64 = system->highestELIs64();
84 haveSecurity = system->haveSecurity();
85 haveLPAE = system->haveLPAE();
86 haveCrypto = system->haveCrypto();
87 haveVirtualization = system->haveVirtualization();
88 haveLargeAsid64 = system->haveLargeAsid64();
89 physAddrRange = system->physAddrRange();
90 haveSVE = system->haveSVE();
91 haveVHE = system->haveVHE();
92 havePAN = system->havePAN();
93 haveSecEL2 = system->haveSecEL2();
94 sveVL = system->sveVL();
95 haveLSE = system->haveLSE();
96 haveTME = system->haveTME();
97 } else {
98 highestELIs64 = true; // ArmSystem::highestELIs64 does the same
99 haveSecurity = haveLPAE = haveVirtualization = false;
100 haveCrypto = true;
101 haveLargeAsid64 = false;
102 physAddrRange = 32; // dummy value
103 haveSVE = true;
104 haveVHE = false;
105 havePAN = false;
106 haveSecEL2 = true;
107 sveVL = p.sve_vl_se;
108 haveLSE = true;
109 haveTME = true;
110 }
111
112 // Initial rename mode depends on highestEL
113 const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
114 highestELIs64 ? Enums::Full : Enums::Elem;
115
116 selfDebug = new SelfDebug();
117 initializeMiscRegMetadata();
118 preUnflattenMiscReg();
119
120 clear();
121 }
122
123 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
124
125 const ArmISAParams &
126 ISA::params() const
127 {
128 return dynamic_cast<const Params &>(_params);
129 }
130
131 void
132 ISA::clear()
133 {
134 const Params &p(params());
135
136 // Invalidate cached copies of miscregs in the TLBs
137 if (tc) {
138 getMMUPtr(tc)->invalidateMiscReg();
139 }
140
141 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
142 memset(miscRegs, 0, sizeof(miscRegs));
143
144 initID32(p);
145
146 // We always initialize AArch64 ID registers even
147 // if we are in AArch32. This is done since if we
148 // are in SE mode we don't know if our ArmProcess is
149 // AArch32 or AArch64
150 initID64(p);
151
152 // Start with an event in the mailbox
153 miscRegs[MISCREG_SEV_MAILBOX] = 1;
154
155 // Separate Instruction and Data TLBs
156 miscRegs[MISCREG_TLBTR] = 1;
157
158 MVFR0 mvfr0 = 0;
159 mvfr0.advSimdRegisters = 2;
160 mvfr0.singlePrecision = 2;
161 mvfr0.doublePrecision = 2;
162 mvfr0.vfpExceptionTrapping = 0;
163 mvfr0.divide = 1;
164 mvfr0.squareRoot = 1;
165 mvfr0.shortVectors = 1;
166 mvfr0.roundingModes = 1;
167 miscRegs[MISCREG_MVFR0] = mvfr0;
168
169 MVFR1 mvfr1 = 0;
170 mvfr1.flushToZero = 1;
171 mvfr1.defaultNaN = 1;
172 mvfr1.advSimdLoadStore = 1;
173 mvfr1.advSimdInteger = 1;
174 mvfr1.advSimdSinglePrecision = 1;
175 mvfr1.advSimdHalfPrecision = 1;
176 mvfr1.vfpHalfPrecision = 1;
177 miscRegs[MISCREG_MVFR1] = mvfr1;
178
179 // Reset values of PRRR and NMRR are implementation dependent
180
181 // @todo: PRRR and NMRR in secure state?
182 miscRegs[MISCREG_PRRR_NS] =
183 (1 << 19) | // 19
184 (0 << 18) | // 18
185 (0 << 17) | // 17
186 (1 << 16) | // 16
187 (2 << 14) | // 15:14
188 (0 << 12) | // 13:12
189 (2 << 10) | // 11:10
190 (2 << 8) | // 9:8
191 (2 << 6) | // 7:6
192 (2 << 4) | // 5:4
193 (1 << 2) | // 3:2
194 0; // 1:0
195
196 miscRegs[MISCREG_NMRR_NS] =
197 (1 << 30) | // 31:30
198 (0 << 26) | // 27:26
199 (0 << 24) | // 25:24
200 (3 << 22) | // 23:22
201 (2 << 20) | // 21:20
202 (0 << 18) | // 19:18
203 (0 << 16) | // 17:16
204 (1 << 14) | // 15:14
205 (0 << 12) | // 13:12
206 (2 << 10) | // 11:10
207 (0 << 8) | // 9:8
208 (3 << 6) | // 7:6
209 (2 << 4) | // 5:4
210 (0 << 2) | // 3:2
211 0; // 1:0
212
213 if (FullSystem && system->highestELIs64()) {
214 // Initialize AArch64 state
215 clear64(p);
216 return;
217 }
218
219 // Initialize AArch32 state...
220 clear32(p, sctlr_rst);
221 }
222
223 void
224 ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
225 {
226 CPSR cpsr = 0;
227 cpsr.mode = MODE_USER;
228
229 if (FullSystem) {
230 miscRegs[MISCREG_MVBAR] = system->resetAddr();
231 }
232
233 miscRegs[MISCREG_CPSR] = cpsr;
234 updateRegMap(cpsr);
235
236 SCTLR sctlr = 0;
237 sctlr.te = (bool) sctlr_rst.te;
238 sctlr.nmfi = (bool) sctlr_rst.nmfi;
239 sctlr.v = (bool) sctlr_rst.v;
240 sctlr.u = 1;
241 sctlr.xp = 1;
242 sctlr.rao2 = 1;
243 sctlr.rao3 = 1;
244 sctlr.rao4 = 0xf; // SCTLR[6:3]
245 sctlr.uci = 1;
246 sctlr.dze = 1;
247 miscRegs[MISCREG_SCTLR_NS] = sctlr;
248 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
249 miscRegs[MISCREG_HCPTR] = 0;
250
251 miscRegs[MISCREG_CPACR] = 0;
252
253 miscRegs[MISCREG_FPSID] = p.fpsid;
254
255 if (haveLPAE) {
256 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
257 ttbcr.eae = 0;
258 miscRegs[MISCREG_TTBCR_NS] = ttbcr;
259 // Enforce consistency with system-level settings
260 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
261 }
262
263 if (haveSecurity) {
264 miscRegs[MISCREG_SCTLR_S] = sctlr;
265 miscRegs[MISCREG_SCR] = 0;
266 miscRegs[MISCREG_VBAR_S] = 0;
267 } else {
268 // we're always non-secure
269 miscRegs[MISCREG_SCR] = 1;
270 }
271
272 //XXX We need to initialize the rest of the state.
273 }
274
275 void
276 ISA::clear64(const ArmISAParams &p)
277 {
278 CPSR cpsr = 0;
279 Addr rvbar = system->resetAddr();
280 switch (system->highestEL()) {
281 // Set initial EL to highest implemented EL using associated stack
282 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
283 // value
284 case EL3:
285 cpsr.mode = MODE_EL3H;
286 miscRegs[MISCREG_RVBAR_EL3] = rvbar;
287 break;
288 case EL2:
289 cpsr.mode = MODE_EL2H;
290 miscRegs[MISCREG_RVBAR_EL2] = rvbar;
291 break;
292 case EL1:
293 cpsr.mode = MODE_EL1H;
294 miscRegs[MISCREG_RVBAR_EL1] = rvbar;
295 break;
296 default:
297 panic("Invalid highest implemented exception level");
298 break;
299 }
300
301 // Initialize rest of CPSR
302 cpsr.daif = 0xf; // Mask all interrupts
303 cpsr.ss = 0;
304 cpsr.il = 0;
305 miscRegs[MISCREG_CPSR] = cpsr;
306 updateRegMap(cpsr);
307
308 // Initialize other control registers
309 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
310 if (haveSecurity) {
311 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
312 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields
313 } else if (haveVirtualization) {
314 // also MISCREG_SCTLR_EL2 (by mapping)
315 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
316 } else {
317 // also MISCREG_SCTLR_EL1 (by mapping)
318 miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
319 // Always non-secure
320 miscRegs[MISCREG_SCR_EL3] = 1;
321 }
322 }
323
324 void
325 ISA::initID32(const ArmISAParams &p)
326 {
327 // Initialize configurable default values
328
329 uint32_t midr;
330 if (p.midr != 0x0)
331 midr = p.midr;
332 else if (highestELIs64)
333 // Cortex-A57 TRM r0p0 MIDR
334 midr = 0x410fd070;
335 else
336 // Cortex-A15 TRM r0p0 MIDR
337 midr = 0x410fc0f0;
338
339 miscRegs[MISCREG_MIDR] = midr;
340 miscRegs[MISCREG_MIDR_EL1] = midr;
341 miscRegs[MISCREG_VPIDR] = midr;
342
343 miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
344 miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
345 miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
346 miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
347 miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
348 miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
349 miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
350
351 miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
352 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
353 miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
354 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
355 miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
356
357 miscRegs[MISCREG_ID_ISAR5] = insertBits(
358 miscRegs[MISCREG_ID_ISAR5], 19, 4,
359 haveCrypto ? 0x1112 : 0x0);
360 }
361
362 void
363 ISA::initID64(const ArmISAParams &p)
364 {
365 // Initialize configurable id registers
366 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
367 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
368 miscRegs[MISCREG_ID_AA64DFR0_EL1] =
369 (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
370 (p.pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3
371
372 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
373 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
374 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
375 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
376 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
377 miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
378
379 miscRegs[MISCREG_ID_DFR0_EL1] =
380 (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
381
382 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
383
384 // SVE
385 miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0
386 if (haveSecurity) {
387 miscRegs[MISCREG_ZCR_EL3] = sveVL - 1;
388 } else if (haveVirtualization) {
389 miscRegs[MISCREG_ZCR_EL2] = sveVL - 1;
390 } else {
391 miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
392 }
393
394 // Enforce consistency with system-level settings...
395
396 // EL3
397 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
398 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
399 haveSecurity ? 0x2 : 0x0);
400 // EL2
401 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
402 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
403 haveVirtualization ? 0x2 : 0x0);
404 // SVE
405 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
406 miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
407 haveSVE ? 0x1 : 0x0);
408 // SecEL2
409 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
410 miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
411 haveSecEL2 ? 0x1 : 0x0);
412 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
413 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 39, 36,
414 haveSecEL2 ? 0x1 : 0x0);
415 // Large ASID support
416 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
417 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
418 haveLargeAsid64 ? 0x2 : 0x0);
419 // Physical address size
420 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
421 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
422 encodePhysAddrRange64(physAddrRange));
423 // Crypto
424 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
425 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
426 haveCrypto ? 0x1112 : 0x0);
427 // LSE
428 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
429 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
430 haveLSE ? 0x2 : 0x0);
431 // VHE
432 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
433 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
434 haveVHE ? 0x1 : 0x0);
435 // PAN
436 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
437 miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
438 havePAN ? 0x1 : 0x0);
439 // TME
440 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
441 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 27, 24,
442 haveTME ? 0x1 : 0x0);
443 }
444
445 void
446 ISA::startup()
447 {
448 BaseISA::startup();
449
450 if (tc) {
451 setupThreadContext();
452
453 if (haveTME) {
454 std::unique_ptr<BaseHTMCheckpoint> cpt(new HTMCheckpoint());
455 tc->setHtmCheckpointPtr(std::move(cpt));
456 }
457 }
458
459 afterStartup = true;
460 }
461
462 void
463 ISA::setupThreadContext()
464 {
465 pmu->setThreadContext(tc);
466
467 if (!system)
468 return;
469
470 selfDebug->init(tc);
471
472 Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
473 if (!gicv3)
474 return;
475
476 if (!gicv3CpuInterface)
477 gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
478
479 gicv3CpuInterface->setISA(this);
480 gicv3CpuInterface->setThreadContext(tc);
481 }
482
483 void
484 ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
485 {
486 tc = new_tc;
487 setupThreadContext();
488 }
489
490 RegVal
491 ISA::readMiscRegNoEffect(int misc_reg) const
492 {
493 assert(misc_reg < NumMiscRegs);
494
495 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
496 const auto &map = getMiscIndices(misc_reg);
497 int lower = map.first, upper = map.second;
498 // NB!: apply architectural masks according to desired register,
499 // despite possibly getting value from different (mapped) register.
500 auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
501 |(miscRegs[upper] << 32));
502 if (val & reg.res0()) {
503 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
504 miscRegName[misc_reg], val & reg.res0());
505 }
506 if ((val & reg.res1()) != reg.res1()) {
507 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
508 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
509 }
510 return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
511 }
512
513
514 RegVal
515 ISA::readMiscReg(int misc_reg)
516 {
517 CPSR cpsr = 0;
518 PCState pc = 0;
519 SCR scr = 0;
520
521 if (misc_reg == MISCREG_CPSR) {
522 cpsr = miscRegs[misc_reg];
523 pc = tc->pcState();
524 cpsr.j = pc.jazelle() ? 1 : 0;
525 cpsr.t = pc.thumb() ? 1 : 0;
526 return cpsr;
527 }
528
529 #ifndef NDEBUG
530 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
531 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
532 warn("Unimplemented system register %s read.\n",
533 miscRegName[misc_reg]);
534 else
535 panic("Unimplemented system register %s read.\n",
536 miscRegName[misc_reg]);
537 }
538 #endif
539 misc_reg = redirectRegVHE(tc, misc_reg);
540
541 switch (unflattenMiscReg(misc_reg)) {
542 case MISCREG_HCR:
543 case MISCREG_HCR2:
544 if (!haveVirtualization)
545 return 0;
546 break;
547 case MISCREG_CPACR:
548 {
549 const uint32_t ones = (uint32_t)(-1);
550 CPACR cpacrMask = 0;
551 // Only cp10, cp11, and ase are implemented, nothing else should
552 // be readable? (straight copy from the write code)
553 cpacrMask.cp10 = ones;
554 cpacrMask.cp11 = ones;
555 cpacrMask.asedis = ones;
556
557 // Security Extensions may limit the readability of CPACR
558 if (haveSecurity) {
559 scr = readMiscRegNoEffect(MISCREG_SCR);
560 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
561 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
562 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
563 // NB: Skipping the full loop, here
564 if (!nsacr.cp10) cpacrMask.cp10 = 0;
565 if (!nsacr.cp11) cpacrMask.cp11 = 0;
566 }
567 }
568 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
569 val &= cpacrMask;
570 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
571 miscRegName[misc_reg], val);
572 return val;
573 }
574 case MISCREG_MPIDR:
575 case MISCREG_MPIDR_EL1:
576 return readMPIDR(system, tc);
577 case MISCREG_VMPIDR:
578 case MISCREG_VMPIDR_EL2:
579 // top bit defined as RES1
580 return readMiscRegNoEffect(misc_reg) | 0x80000000;
581 case MISCREG_ID_AFR0: // not implemented, so alias MIDR
582 case MISCREG_REVIDR: // not implemented, so alias MIDR
583 case MISCREG_MIDR:
584 cpsr = readMiscRegNoEffect(MISCREG_CPSR);
585 scr = readMiscRegNoEffect(MISCREG_SCR);
586 if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
587 return readMiscRegNoEffect(misc_reg);
588 } else {
589 return readMiscRegNoEffect(MISCREG_VPIDR);
590 }
591 break;
592 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
593 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
594 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
595 case MISCREG_AIDR: // AUX ID set to 0
596 case MISCREG_TCMTR: // No TCM's
597 return 0;
598
599 case MISCREG_CLIDR:
600 warn_once("The clidr register always reports 0 caches.\n");
601 warn_once("clidr LoUIS field of 0b001 to match current "
602 "ARM implementations.\n");
603 return 0x00200000;
604 case MISCREG_CCSIDR:
605 warn_once("The ccsidr register isn't implemented and "
606 "always reads as 0.\n");
607 break;
608 case MISCREG_CTR: // AArch32, ARMv7, top bit set
609 case MISCREG_CTR_EL0: // AArch64
610 {
611 //all caches have the same line size in gem5
612 //4 byte words in ARM
613 unsigned lineSizeWords =
614 tc->getSystemPtr()->cacheLineSize() / 4;
615 unsigned log2LineSizeWords = 0;
616
617 while (lineSizeWords >>= 1) {
618 ++log2LineSizeWords;
619 }
620
621 CTR ctr = 0;
622 //log2 of minimun i-cache line size (words)
623 ctr.iCacheLineSize = log2LineSizeWords;
624 //b11 - gem5 uses pipt
625 ctr.l1IndexPolicy = 0x3;
626 //log2 of minimum d-cache line size (words)
627 ctr.dCacheLineSize = log2LineSizeWords;
628 //log2 of max reservation size (words)
629 ctr.erg = log2LineSizeWords;
630 //log2 of max writeback size (words)
631 ctr.cwg = log2LineSizeWords;
632 //b100 - gem5 format is ARMv7
633 ctr.format = 0x4;
634
635 return ctr;
636 }
637 case MISCREG_ACTLR:
638 warn("Not doing anything for miscreg ACTLR\n");
639 break;
640
641 case MISCREG_PMXEVTYPER_PMCCFILTR:
642 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
643 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
644 case MISCREG_PMCR ... MISCREG_PMOVSSET:
645 return pmu->readMiscReg(misc_reg);
646
647 case MISCREG_CPSR_Q:
648 panic("shouldn't be reading this register seperately\n");
649 case MISCREG_FPSCR_QC:
650 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
651 case MISCREG_FPSCR_EXC:
652 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
653 case MISCREG_FPSR:
654 {
655 const uint32_t ones = (uint32_t)(-1);
656 FPSCR fpscrMask = 0;
657 fpscrMask.ioc = ones;
658 fpscrMask.dzc = ones;
659 fpscrMask.ofc = ones;
660 fpscrMask.ufc = ones;
661 fpscrMask.ixc = ones;
662 fpscrMask.idc = ones;
663 fpscrMask.qc = ones;
664 fpscrMask.v = ones;
665 fpscrMask.c = ones;
666 fpscrMask.z = ones;
667 fpscrMask.n = ones;
668 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
669 }
670 case MISCREG_FPCR:
671 {
672 const uint32_t ones = (uint32_t)(-1);
673 FPSCR fpscrMask = 0;
674 fpscrMask.len = ones;
675 fpscrMask.fz16 = ones;
676 fpscrMask.stride = ones;
677 fpscrMask.rMode = ones;
678 fpscrMask.fz = ones;
679 fpscrMask.dn = ones;
680 fpscrMask.ahp = ones;
681 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
682 }
683 case MISCREG_NZCV:
684 {
685 CPSR cpsr = 0;
686 cpsr.nz = tc->readCCReg(CCREG_NZ);
687 cpsr.c = tc->readCCReg(CCREG_C);
688 cpsr.v = tc->readCCReg(CCREG_V);
689 return cpsr;
690 }
691 case MISCREG_DAIF:
692 {
693 CPSR cpsr = 0;
694 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
695 return cpsr;
696 }
697 case MISCREG_SP_EL0:
698 {
699 return tc->readIntReg(INTREG_SP0);
700 }
701 case MISCREG_SP_EL1:
702 {
703 return tc->readIntReg(INTREG_SP1);
704 }
705 case MISCREG_SP_EL2:
706 {
707 return tc->readIntReg(INTREG_SP2);
708 }
709 case MISCREG_SPSEL:
710 {
711 return miscRegs[MISCREG_CPSR] & 0x1;
712 }
713 case MISCREG_CURRENTEL:
714 {
715 return miscRegs[MISCREG_CPSR] & 0xc;
716 }
717 case MISCREG_PAN:
718 {
719 return miscRegs[MISCREG_CPSR] & 0x400000;
720 }
721 case MISCREG_L2CTLR:
722 {
723 // mostly unimplemented, just set NumCPUs field from sim and return
724 L2CTLR l2ctlr = 0;
725 // b00:1CPU to b11:4CPUs
726 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
727 return l2ctlr;
728 }
729 case MISCREG_DBGDIDR:
730 /* For now just implement the version number.
731 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
732 */
733 return 0x5 << 16;
734 case MISCREG_DBGDSCRint:
735 return readMiscRegNoEffect(MISCREG_DBGDSCRint);
736 case MISCREG_ISR:
737 {
738 auto ic = dynamic_cast<ArmISA::Interrupts *>(
739 tc->getCpuPtr()->getInterruptController(tc->threadId()));
740 return ic->getISR(
741 readMiscRegNoEffect(MISCREG_HCR),
742 readMiscRegNoEffect(MISCREG_CPSR),
743 readMiscRegNoEffect(MISCREG_SCR));
744 }
745 case MISCREG_ISR_EL1:
746 {
747 auto ic = dynamic_cast<ArmISA::Interrupts *>(
748 tc->getCpuPtr()->getInterruptController(tc->threadId()));
749 return ic->getISR(
750 readMiscRegNoEffect(MISCREG_HCR_EL2),
751 readMiscRegNoEffect(MISCREG_CPSR),
752 readMiscRegNoEffect(MISCREG_SCR_EL3));
753 }
754 case MISCREG_DCZID_EL0:
755 return 0x04; // DC ZVA clear 64-byte chunks
756 case MISCREG_HCPTR:
757 {
758 RegVal val = readMiscRegNoEffect(misc_reg);
759 // The trap bit associated with CP14 is defined as RAZ
760 val &= ~(1 << 14);
761 // If a CP bit in NSACR is 0 then the corresponding bit in
762 // HCPTR is RAO/WI
763 bool secure_lookup = haveSecurity && isSecure(tc);
764 if (!secure_lookup) {
765 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
766 val |= (mask ^ 0x7FFF) & 0xBFFF;
767 }
768 // Set the bits for unimplemented coprocessors to RAO/WI
769 val |= 0x33FF;
770 return (val);
771 }
772 case MISCREG_HDFAR: // alias for secure DFAR
773 return readMiscRegNoEffect(MISCREG_DFAR_S);
774 case MISCREG_HIFAR: // alias for secure IFAR
775 return readMiscRegNoEffect(MISCREG_IFAR_S);
776
777 case MISCREG_ID_PFR0:
778 // !ThumbEE | !Jazelle | Thumb | ARM
779 return 0x00000031;
780 case MISCREG_ID_PFR1:
781 { // Timer | Virti | !M Profile | TrustZone | ARMv4
782 bool haveTimer = (system->getGenericTimer() != NULL);
783 return 0x00000001
784 | (haveSecurity ? 0x00000010 : 0x0)
785 | (haveVirtualization ? 0x00001000 : 0x0)
786 | (haveTimer ? 0x00010000 : 0x0);
787 }
788 case MISCREG_ID_AA64PFR0_EL1:
789 return 0x0000000000000002 | // AArch{64,32} supported at EL0
790 0x0000000000000020 | // EL1
791 (haveVirtualization ? 0x0000000000000200 : 0) | // EL2
792 (haveSecurity ? 0x0000000000002000 : 0) | // EL3
793 (haveSVE ? 0x0000000100000000 : 0) | // SVE
794 (haveSecEL2 ? 0x0000001000000000 : 0) | // SecEL2
795 (gicv3CpuInterface ? 0x0000000001000000 : 0);
796 case MISCREG_ID_AA64PFR1_EL1:
797 return 0; // bits [63:0] RES0 (reserved for future use)
798
799 // Generic Timer registers
800 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
801 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
802 return getGenericTimer().readMiscReg(misc_reg);
803
804 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
805 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
806 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
807 return getGICv3CPUInterface().readMiscReg(misc_reg);
808
809 default:
810 break;
811
812 }
813 return readMiscRegNoEffect(misc_reg);
814 }
815
816 void
817 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
818 {
819 assert(misc_reg < NumMiscRegs);
820
821 const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
822 const auto &map = getMiscIndices(misc_reg);
823 int lower = map.first, upper = map.second;
824
825 auto v = (val & ~reg.wi()) | reg.rao();
826 if (upper > 0) {
827 miscRegs[lower] = bits(v, 31, 0);
828 miscRegs[upper] = bits(v, 63, 32);
829 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
830 miscRegName[misc_reg], misc_reg, lower, upper, v);
831 } else {
832 miscRegs[lower] = v;
833 DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
834 miscRegName[misc_reg], misc_reg, lower, v);
835 }
836 }
837
838 void
839 ISA::setMiscReg(int misc_reg, RegVal val)
840 {
841
842 RegVal newVal = val;
843 bool secure_lookup;
844 SCR scr;
845
846 if (misc_reg == MISCREG_CPSR) {
847 updateRegMap(val);
848
849
850 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
851 int old_mode = old_cpsr.mode;
852 CPSR cpsr = val;
853 if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
854 getMMUPtr(tc)->invalidateMiscReg();
855 }
856
857 if (cpsr.pan != old_cpsr.pan) {
858 getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
859 }
860
861 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
862 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
863 PCState pc = tc->pcState();
864 pc.nextThumb(cpsr.t);
865 pc.nextJazelle(cpsr.j);
866 pc.illegalExec(cpsr.il == 1);
867 selfDebug->setDebugMask(cpsr.d == 1);
868
869 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
870
871 // Follow slightly different semantics if a CheckerCPU object
872 // is connected
873 CheckerCPU *checker = tc->getCheckerCpuPtr();
874 if (checker) {
875 tc->pcStateNoRecord(pc);
876 } else {
877 tc->pcState(pc);
878 }
879 } else {
880 #ifndef NDEBUG
881 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
882 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
883 warn("Unimplemented system register %s write with %#x.\n",
884 miscRegName[misc_reg], val);
885 else
886 panic("Unimplemented system register %s write with %#x.\n",
887 miscRegName[misc_reg], val);
888 }
889 #endif
890 misc_reg = redirectRegVHE(tc, misc_reg);
891
892 switch (unflattenMiscReg(misc_reg)) {
893 case MISCREG_CPACR:
894 {
895
896 const uint32_t ones = (uint32_t)(-1);
897 CPACR cpacrMask = 0;
898 // Only cp10, cp11, and ase are implemented, nothing else should
899 // be writable
900 cpacrMask.cp10 = ones;
901 cpacrMask.cp11 = ones;
902 cpacrMask.asedis = ones;
903
904 // Security Extensions may limit the writability of CPACR
905 if (haveSecurity) {
906 scr = readMiscRegNoEffect(MISCREG_SCR);
907 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
908 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
909 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
910 // NB: Skipping the full loop, here
911 if (!nsacr.cp10) cpacrMask.cp10 = 0;
912 if (!nsacr.cp11) cpacrMask.cp11 = 0;
913 }
914 }
915
916 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
917 newVal &= cpacrMask;
918 newVal |= old_val & ~cpacrMask;
919 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
920 miscRegName[misc_reg], newVal);
921 }
922 break;
923 case MISCREG_CPACR_EL1:
924 {
925 const uint32_t ones = (uint32_t)(-1);
926 CPACR cpacrMask = 0;
927 cpacrMask.tta = ones;
928 cpacrMask.fpen = ones;
929 if (haveSVE) {
930 cpacrMask.zen = ones;
931 }
932 newVal &= cpacrMask;
933 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
934 miscRegName[misc_reg], newVal);
935 }
936 break;
937 case MISCREG_CPTR_EL2:
938 {
939 const uint32_t ones = (uint32_t)(-1);
940 CPTR cptrMask = 0;
941 cptrMask.tcpac = ones;
942 cptrMask.tta = ones;
943 cptrMask.tfp = ones;
944 if (haveSVE) {
945 cptrMask.tz = ones;
946 }
947 newVal &= cptrMask;
948 cptrMask = 0;
949 cptrMask.res1_13_12_el2 = ones;
950 cptrMask.res1_7_0_el2 = ones;
951 if (!haveSVE) {
952 cptrMask.res1_8_el2 = ones;
953 }
954 cptrMask.res1_9_el2 = ones;
955 newVal |= cptrMask;
956 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
957 miscRegName[misc_reg], newVal);
958 }
959 break;
960 case MISCREG_CPTR_EL3:
961 {
962 const uint32_t ones = (uint32_t)(-1);
963 CPTR cptrMask = 0;
964 cptrMask.tcpac = ones;
965 cptrMask.tta = ones;
966 cptrMask.tfp = ones;
967 if (haveSVE) {
968 cptrMask.ez = ones;
969 }
970 newVal &= cptrMask;
971 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
972 miscRegName[misc_reg], newVal);
973 }
974 break;
975 case MISCREG_CSSELR:
976 warn_once("The csselr register isn't implemented.\n");
977 return;
978
979 case MISCREG_DC_ZVA_Xt:
980 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
981 return;
982
983 case MISCREG_FPSCR:
984 {
985 const uint32_t ones = (uint32_t)(-1);
986 FPSCR fpscrMask = 0;
987 fpscrMask.ioc = ones;
988 fpscrMask.dzc = ones;
989 fpscrMask.ofc = ones;
990 fpscrMask.ufc = ones;
991 fpscrMask.ixc = ones;
992 fpscrMask.idc = ones;
993 fpscrMask.ioe = ones;
994 fpscrMask.dze = ones;
995 fpscrMask.ofe = ones;
996 fpscrMask.ufe = ones;
997 fpscrMask.ixe = ones;
998 fpscrMask.ide = ones;
999 fpscrMask.len = ones;
1000 fpscrMask.fz16 = ones;
1001 fpscrMask.stride = ones;
1002 fpscrMask.rMode = ones;
1003 fpscrMask.fz = ones;
1004 fpscrMask.dn = ones;
1005 fpscrMask.ahp = ones;
1006 fpscrMask.qc = ones;
1007 fpscrMask.v = ones;
1008 fpscrMask.c = ones;
1009 fpscrMask.z = ones;
1010 fpscrMask.n = ones;
1011 newVal = (newVal & (uint32_t)fpscrMask) |
1012 (readMiscRegNoEffect(MISCREG_FPSCR) &
1013 ~(uint32_t)fpscrMask);
1014 tc->getDecoderPtr()->setContext(newVal);
1015 }
1016 break;
1017 case MISCREG_FPSR:
1018 {
1019 const uint32_t ones = (uint32_t)(-1);
1020 FPSCR fpscrMask = 0;
1021 fpscrMask.ioc = ones;
1022 fpscrMask.dzc = ones;
1023 fpscrMask.ofc = ones;
1024 fpscrMask.ufc = ones;
1025 fpscrMask.ixc = ones;
1026 fpscrMask.idc = ones;
1027 fpscrMask.qc = ones;
1028 fpscrMask.v = ones;
1029 fpscrMask.c = ones;
1030 fpscrMask.z = ones;
1031 fpscrMask.n = ones;
1032 newVal = (newVal & (uint32_t)fpscrMask) |
1033 (readMiscRegNoEffect(MISCREG_FPSCR) &
1034 ~(uint32_t)fpscrMask);
1035 misc_reg = MISCREG_FPSCR;
1036 }
1037 break;
1038 case MISCREG_FPCR:
1039 {
1040 const uint32_t ones = (uint32_t)(-1);
1041 FPSCR fpscrMask = 0;
1042 fpscrMask.len = ones;
1043 fpscrMask.fz16 = ones;
1044 fpscrMask.stride = ones;
1045 fpscrMask.rMode = ones;
1046 fpscrMask.fz = ones;
1047 fpscrMask.dn = ones;
1048 fpscrMask.ahp = ones;
1049 newVal = (newVal & (uint32_t)fpscrMask) |
1050 (readMiscRegNoEffect(MISCREG_FPSCR) &
1051 ~(uint32_t)fpscrMask);
1052 misc_reg = MISCREG_FPSCR;
1053 }
1054 break;
1055 case MISCREG_CPSR_Q:
1056 {
1057 assert(!(newVal & ~CpsrMaskQ));
1058 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
1059 misc_reg = MISCREG_CPSR;
1060 }
1061 break;
1062 case MISCREG_FPSCR_QC:
1063 {
1064 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1065 (newVal & FpscrQcMask);
1066 misc_reg = MISCREG_FPSCR;
1067 }
1068 break;
1069 case MISCREG_FPSCR_EXC:
1070 {
1071 newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
1072 (newVal & FpscrExcMask);
1073 misc_reg = MISCREG_FPSCR;
1074 }
1075 break;
1076 case MISCREG_FPEXC:
1077 {
1078 // vfpv3 architecture, section B.6.1 of DDI04068
1079 // bit 29 - valid only if fpexc[31] is 0
1080 const uint32_t fpexcMask = 0x60000000;
1081 newVal = (newVal & fpexcMask) |
1082 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
1083 }
1084 break;
1085 case MISCREG_HCR2:
1086 if (!haveVirtualization)
1087 return;
1088 break;
1089 case MISCREG_HCR:
1090 {
1091 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1092 selfDebug->setenableTDETGE((HCR)val, mdcr);
1093 if (!haveVirtualization)
1094 return;
1095 }
1096 break;
1097
1098 case MISCREG_HDCR:
1099 {
1100 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1101 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1102 }
1103 break;
1104 case MISCREG_DBGOSLAR:
1105 {
1106 OSL r = tc->readMiscReg(MISCREG_DBGOSLSR);
1107 const uint32_t temp = (val == 0xC5ACCE55)? 0x1 : 0x0;
1108 selfDebug->updateOSLock((RegVal) temp);
1109 r.oslk = bits(temp,0);
1110 tc->setMiscReg(MISCREG_DBGOSLSR, r);
1111 }
1112 break;
1113 case MISCREG_DBGBCR0:
1114 selfDebug->updateDBGBCR(0, val);
1115 break;
1116 case MISCREG_DBGBCR1:
1117 selfDebug->updateDBGBCR(1, val);
1118 break;
1119 case MISCREG_DBGBCR2:
1120 selfDebug->updateDBGBCR(2, val);
1121 break;
1122 case MISCREG_DBGBCR3:
1123 selfDebug->updateDBGBCR(3, val);
1124 break;
1125 case MISCREG_DBGBCR4:
1126 selfDebug->updateDBGBCR(4, val);
1127 break;
1128 case MISCREG_DBGBCR5:
1129 selfDebug->updateDBGBCR(5, val);
1130 break;
1131 case MISCREG_DBGBCR6:
1132 selfDebug->updateDBGBCR(6, val);
1133 break;
1134 case MISCREG_DBGBCR7:
1135 selfDebug->updateDBGBCR(7, val);
1136 break;
1137 case MISCREG_DBGBCR8:
1138 selfDebug->updateDBGBCR(8, val);
1139 break;
1140 case MISCREG_DBGBCR9:
1141 selfDebug->updateDBGBCR(9, val);
1142 break;
1143 case MISCREG_DBGBCR10:
1144 selfDebug->updateDBGBCR(10, val);
1145 break;
1146 case MISCREG_DBGBCR11:
1147 selfDebug->updateDBGBCR(11, val);
1148 break;
1149 case MISCREG_DBGBCR12:
1150 selfDebug->updateDBGBCR(12, val);
1151 break;
1152 case MISCREG_DBGBCR13:
1153 selfDebug->updateDBGBCR(13, val);
1154 break;
1155 case MISCREG_DBGBCR14:
1156 selfDebug->updateDBGBCR(14, val);
1157 break;
1158 case MISCREG_DBGBCR15:
1159 selfDebug->updateDBGBCR(15, val);
1160 break;
1161 case MISCREG_DBGWCR0:
1162 selfDebug->updateDBGWCR(0, val);
1163 break;
1164 case MISCREG_DBGWCR1:
1165 selfDebug->updateDBGWCR(1, val);
1166 break;
1167 case MISCREG_DBGWCR2:
1168 selfDebug->updateDBGWCR(2, val);
1169 break;
1170 case MISCREG_DBGWCR3:
1171 selfDebug->updateDBGWCR(3, val);
1172 break;
1173 case MISCREG_DBGWCR4:
1174 selfDebug->updateDBGWCR(4, val);
1175 break;
1176 case MISCREG_DBGWCR5:
1177 selfDebug->updateDBGWCR(5, val);
1178 break;
1179 case MISCREG_DBGWCR6:
1180 selfDebug->updateDBGWCR(6, val);
1181 break;
1182 case MISCREG_DBGWCR7:
1183 selfDebug->updateDBGWCR(7, val);
1184 break;
1185 case MISCREG_DBGWCR8:
1186 selfDebug->updateDBGWCR(8, val);
1187 break;
1188 case MISCREG_DBGWCR9:
1189 selfDebug->updateDBGWCR(9, val);
1190 break;
1191 case MISCREG_DBGWCR10:
1192 selfDebug->updateDBGWCR(10, val);
1193 break;
1194 case MISCREG_DBGWCR11:
1195 selfDebug->updateDBGWCR(11, val);
1196 break;
1197 case MISCREG_DBGWCR12:
1198 selfDebug->updateDBGWCR(12, val);
1199 break;
1200 case MISCREG_DBGWCR13:
1201 selfDebug->updateDBGWCR(13, val);
1202 break;
1203 case MISCREG_DBGWCR14:
1204 selfDebug->updateDBGWCR(14, val);
1205 break;
1206 case MISCREG_DBGWCR15:
1207 selfDebug->updateDBGWCR(15, val);
1208 break;
1209
1210 case MISCREG_MDCR_EL2:
1211 {
1212 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1213 selfDebug->setenableTDETGE(hcr, (HDCR)val);
1214 }
1215 break;
1216 case MISCREG_SDCR:
1217 case MISCREG_MDCR_EL3:
1218 {
1219 selfDebug->setbSDD(val);
1220 }
1221 break;
1222 case MISCREG_DBGDSCRext:
1223 {
1224 selfDebug->setMDBGen(val);
1225 DBGDS32 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1226 DBGDS32 v = val;
1227 r.moe = v.moe;
1228 r.udccdis = v.udccdis;
1229 r.mdbgen = v.mdbgen;
1230 tc->setMiscReg(MISCREG_DBGDSCRint, r);
1231 r = tc->readMiscReg(MISCREG_DBGDSCRint);
1232 }
1233
1234 break;
1235 case MISCREG_MDSCR_EL1:
1236 {
1237 selfDebug->setMDSCRvals(val);
1238 }
1239 break;
1240
1241 case MISCREG_OSLAR_EL1:
1242 {
1243 selfDebug->updateOSLock(val);
1244 OSL r = tc->readMiscReg(MISCREG_OSLSR_EL1);
1245 r.oslk = bits(val, 0);
1246 r.oslm_3 = 1;
1247 tc->setMiscReg(MISCREG_OSLSR_EL1, r);
1248 }
1249 break;
1250
1251 case MISCREG_DBGBCR0_EL1:
1252 selfDebug->updateDBGBCR(0, val);
1253 break;
1254 case MISCREG_DBGBCR1_EL1:
1255 selfDebug->updateDBGBCR(1, val);
1256 break;
1257 case MISCREG_DBGBCR2_EL1:
1258 selfDebug->updateDBGBCR(2, val);
1259 break;
1260 case MISCREG_DBGBCR3_EL1:
1261 selfDebug->updateDBGBCR(3, val);
1262 break;
1263 case MISCREG_DBGBCR4_EL1:
1264 selfDebug->updateDBGBCR(4, val);
1265 break;
1266 case MISCREG_DBGBCR5_EL1:
1267 selfDebug->updateDBGBCR(5, val);
1268 break;
1269 case MISCREG_DBGBCR6_EL1:
1270 selfDebug->updateDBGBCR(6, val);
1271 break;
1272 case MISCREG_DBGBCR7_EL1:
1273 selfDebug->updateDBGBCR(7, val);
1274 break;
1275 case MISCREG_DBGBCR8_EL1:
1276 selfDebug->updateDBGBCR(8, val);
1277 break;
1278 case MISCREG_DBGBCR9_EL1:
1279 selfDebug->updateDBGBCR(9, val);
1280 break;
1281 case MISCREG_DBGBCR10_EL1:
1282 selfDebug->updateDBGBCR(10, val);
1283 break;
1284 case MISCREG_DBGBCR11_EL1:
1285 selfDebug->updateDBGBCR(11, val);
1286 break;
1287 case MISCREG_DBGBCR12_EL1:
1288 selfDebug->updateDBGBCR(12, val);
1289 break;
1290 case MISCREG_DBGBCR13_EL1:
1291 selfDebug->updateDBGBCR(13, val);
1292 break;
1293 case MISCREG_DBGBCR14_EL1:
1294 selfDebug->updateDBGBCR(14, val);
1295 break;
1296 case MISCREG_DBGBCR15_EL1:
1297 selfDebug->updateDBGBCR(15, val);
1298 break;
1299 case MISCREG_DBGWCR0_EL1:
1300 selfDebug->updateDBGWCR(0, val);
1301 break;
1302 case MISCREG_DBGWCR1_EL1:
1303 selfDebug->updateDBGWCR(1, val);
1304 break;
1305 case MISCREG_DBGWCR2_EL1:
1306 selfDebug->updateDBGWCR(2, val);
1307 break;
1308 case MISCREG_DBGWCR3_EL1:
1309 selfDebug->updateDBGWCR(3, val);
1310 break;
1311 case MISCREG_DBGWCR4_EL1:
1312 selfDebug->updateDBGWCR(4, val);
1313 break;
1314 case MISCREG_DBGWCR5_EL1:
1315 selfDebug->updateDBGWCR(5, val);
1316 break;
1317 case MISCREG_DBGWCR6_EL1:
1318 selfDebug->updateDBGWCR(6, val);
1319 break;
1320 case MISCREG_DBGWCR7_EL1:
1321 selfDebug->updateDBGWCR(7, val);
1322 break;
1323 case MISCREG_DBGWCR8_EL1:
1324 selfDebug->updateDBGWCR(8, val);
1325 break;
1326 case MISCREG_DBGWCR9_EL1:
1327 selfDebug->updateDBGWCR(9, val);
1328 break;
1329 case MISCREG_DBGWCR10_EL1:
1330 selfDebug->updateDBGWCR(10, val);
1331 break;
1332 case MISCREG_DBGWCR11_EL1:
1333 selfDebug->updateDBGWCR(11, val);
1334 break;
1335 case MISCREG_DBGWCR12_EL1:
1336 selfDebug->updateDBGWCR(12, val);
1337 break;
1338 case MISCREG_DBGWCR13_EL1:
1339 selfDebug->updateDBGWCR(13, val);
1340 break;
1341 case MISCREG_DBGWCR14_EL1:
1342 selfDebug->updateDBGWCR(14, val);
1343 break;
1344 case MISCREG_DBGWCR15_EL1:
1345 selfDebug->updateDBGWCR(15, val);
1346 break;
1347 case MISCREG_IFSR:
1348 {
1349 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1350 const uint32_t ifsrMask =
1351 mask(31, 13) | mask(11, 11) | mask(8, 6);
1352 newVal = newVal & ~ifsrMask;
1353 }
1354 break;
1355 case MISCREG_DFSR:
1356 {
1357 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1358 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
1359 newVal = newVal & ~dfsrMask;
1360 }
1361 break;
1362 case MISCREG_AMAIR0:
1363 case MISCREG_AMAIR1:
1364 {
1365 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1366 // Valid only with LPAE
1367 if (!haveLPAE)
1368 return;
1369 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
1370 }
1371 break;
1372 case MISCREG_SCR:
1373 getMMUPtr(tc)->invalidateMiscReg();
1374 break;
1375 case MISCREG_SCTLR:
1376 {
1377 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
1378 scr = readMiscRegNoEffect(MISCREG_SCR);
1379
1380 MiscRegIndex sctlr_idx;
1381 if (haveSecurity && !highestELIs64 && !scr.ns) {
1382 sctlr_idx = MISCREG_SCTLR_S;
1383 } else {
1384 sctlr_idx = MISCREG_SCTLR_NS;
1385 }
1386
1387 SCTLR sctlr = miscRegs[sctlr_idx];
1388 SCTLR new_sctlr = newVal;
1389 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;
1390 miscRegs[sctlr_idx] = (RegVal)new_sctlr;
1391 getMMUPtr(tc)->invalidateMiscReg();
1392 }
1393 case MISCREG_MIDR:
1394 case MISCREG_ID_PFR0:
1395 case MISCREG_ID_PFR1:
1396 case MISCREG_ID_DFR0:
1397 case MISCREG_ID_MMFR0:
1398 case MISCREG_ID_MMFR1:
1399 case MISCREG_ID_MMFR2:
1400 case MISCREG_ID_MMFR3:
1401 case MISCREG_ID_MMFR4:
1402 case MISCREG_ID_ISAR0:
1403 case MISCREG_ID_ISAR1:
1404 case MISCREG_ID_ISAR2:
1405 case MISCREG_ID_ISAR3:
1406 case MISCREG_ID_ISAR4:
1407 case MISCREG_ID_ISAR5:
1408
1409 case MISCREG_MPIDR:
1410 case MISCREG_FPSID:
1411 case MISCREG_TLBTR:
1412 case MISCREG_MVFR0:
1413 case MISCREG_MVFR1:
1414
1415 case MISCREG_ID_AA64AFR0_EL1:
1416 case MISCREG_ID_AA64AFR1_EL1:
1417 case MISCREG_ID_AA64DFR0_EL1:
1418 case MISCREG_ID_AA64DFR1_EL1:
1419 case MISCREG_ID_AA64ISAR0_EL1:
1420 case MISCREG_ID_AA64ISAR1_EL1:
1421 case MISCREG_ID_AA64MMFR0_EL1:
1422 case MISCREG_ID_AA64MMFR1_EL1:
1423 case MISCREG_ID_AA64MMFR2_EL1:
1424 case MISCREG_ID_AA64PFR0_EL1:
1425 case MISCREG_ID_AA64PFR1_EL1:
1426 // ID registers are constants.
1427 return;
1428
1429 // TLB Invalidate All
1430 case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
1431 {
1432 assert32();
1433 scr = readMiscReg(MISCREG_SCR);
1434
1435 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1436 tlbiOp(tc);
1437 return;
1438 }
1439 // TLB Invalidate All, Inner Shareable
1440 case MISCREG_TLBIALLIS:
1441 {
1442 assert32();
1443 scr = readMiscReg(MISCREG_SCR);
1444
1445 TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1446 tlbiOp.broadcast(tc);
1447 return;
1448 }
1449 // Instruction TLB Invalidate All
1450 case MISCREG_ITLBIALL:
1451 {
1452 assert32();
1453 scr = readMiscReg(MISCREG_SCR);
1454
1455 ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1456 tlbiOp(tc);
1457 return;
1458 }
1459 // Data TLB Invalidate All
1460 case MISCREG_DTLBIALL:
1461 {
1462 assert32();
1463 scr = readMiscReg(MISCREG_SCR);
1464
1465 DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
1466 tlbiOp(tc);
1467 return;
1468 }
1469 // TLB Invalidate by VA
1470 // mcr tlbimval(is) is invalidating all matching entries
1471 // regardless of the level of lookup, since in gem5 we cache
1472 // in the tlb the last level of lookup only.
1473 case MISCREG_TLBIMVA:
1474 case MISCREG_TLBIMVAL:
1475 {
1476 assert32();
1477 scr = readMiscReg(MISCREG_SCR);
1478
1479 TLBIMVA tlbiOp(EL1,
1480 haveSecurity && !scr.ns,
1481 mbits(newVal, 31, 12),
1482 bits(newVal, 7,0));
1483
1484 tlbiOp(tc);
1485 return;
1486 }
1487 // TLB Invalidate by VA, Inner Shareable
1488 case MISCREG_TLBIMVAIS:
1489 case MISCREG_TLBIMVALIS:
1490 {
1491 assert32();
1492 scr = readMiscReg(MISCREG_SCR);
1493
1494 TLBIMVA tlbiOp(EL1,
1495 haveSecurity && !scr.ns,
1496 mbits(newVal, 31, 12),
1497 bits(newVal, 7,0));
1498
1499 tlbiOp.broadcast(tc);
1500 return;
1501 }
1502 // TLB Invalidate by ASID match
1503 case MISCREG_TLBIASID:
1504 {
1505 assert32();
1506 scr = readMiscReg(MISCREG_SCR);
1507
1508 TLBIASID tlbiOp(EL1,
1509 haveSecurity && !scr.ns,
1510 bits(newVal, 7,0));
1511
1512 tlbiOp(tc);
1513 return;
1514 }
1515 // TLB Invalidate by ASID match, Inner Shareable
1516 case MISCREG_TLBIASIDIS:
1517 {
1518 assert32();
1519 scr = readMiscReg(MISCREG_SCR);
1520
1521 TLBIASID tlbiOp(EL1,
1522 haveSecurity && !scr.ns,
1523 bits(newVal, 7,0));
1524
1525 tlbiOp.broadcast(tc);
1526 return;
1527 }
1528 // mcr tlbimvaal(is) is invalidating all matching entries
1529 // regardless of the level of lookup, since in gem5 we cache
1530 // in the tlb the last level of lookup only.
1531 // TLB Invalidate by VA, All ASID
1532 case MISCREG_TLBIMVAA:
1533 case MISCREG_TLBIMVAAL:
1534 {
1535 assert32();
1536 scr = readMiscReg(MISCREG_SCR);
1537
1538 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1539 mbits(newVal, 31,12));
1540
1541 tlbiOp(tc);
1542 return;
1543 }
1544 // TLB Invalidate by VA, All ASID, Inner Shareable
1545 case MISCREG_TLBIMVAAIS:
1546 case MISCREG_TLBIMVAALIS:
1547 {
1548 assert32();
1549 scr = readMiscReg(MISCREG_SCR);
1550
1551 TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
1552 mbits(newVal, 31,12));
1553
1554 tlbiOp.broadcast(tc);
1555 return;
1556 }
1557 // mcr tlbimvalh(is) is invalidating all matching entries
1558 // regardless of the level of lookup, since in gem5 we cache
1559 // in the tlb the last level of lookup only.
1560 // TLB Invalidate by VA, Hyp mode
1561 case MISCREG_TLBIMVAH:
1562 case MISCREG_TLBIMVALH:
1563 {
1564 assert32();
1565 scr = readMiscReg(MISCREG_SCR);
1566
1567 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1568 mbits(newVal, 31,12));
1569
1570 tlbiOp(tc);
1571 return;
1572 }
1573 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1574 case MISCREG_TLBIMVAHIS:
1575 case MISCREG_TLBIMVALHIS:
1576 {
1577 assert32();
1578 scr = readMiscReg(MISCREG_SCR);
1579
1580 TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
1581 mbits(newVal, 31,12));
1582
1583 tlbiOp.broadcast(tc);
1584 return;
1585 }
1586 // mcr tlbiipas2l(is) is invalidating all matching entries
1587 // regardless of the level of lookup, since in gem5 we cache
1588 // in the tlb the last level of lookup only.
1589 // TLB Invalidate by Intermediate Physical Address, Stage 2
1590 case MISCREG_TLBIIPAS2:
1591 case MISCREG_TLBIIPAS2L:
1592 {
1593 assert32();
1594 scr = readMiscReg(MISCREG_SCR);
1595
1596 TLBIIPA tlbiOp(EL1,
1597 haveSecurity && !scr.ns,
1598 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1599
1600 tlbiOp(tc);
1601 return;
1602 }
1603 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1604 // Inner Shareable
1605 case MISCREG_TLBIIPAS2IS:
1606 case MISCREG_TLBIIPAS2LIS:
1607 {
1608 assert32();
1609 scr = readMiscReg(MISCREG_SCR);
1610
1611 TLBIIPA tlbiOp(EL1,
1612 haveSecurity && !scr.ns,
1613 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1614
1615 tlbiOp.broadcast(tc);
1616 return;
1617 }
1618 // Instruction TLB Invalidate by VA
1619 case MISCREG_ITLBIMVA:
1620 {
1621 assert32();
1622 scr = readMiscReg(MISCREG_SCR);
1623
1624 ITLBIMVA tlbiOp(EL1,
1625 haveSecurity && !scr.ns,
1626 mbits(newVal, 31, 12),
1627 bits(newVal, 7,0));
1628
1629 tlbiOp(tc);
1630 return;
1631 }
1632 // Data TLB Invalidate by VA
1633 case MISCREG_DTLBIMVA:
1634 {
1635 assert32();
1636 scr = readMiscReg(MISCREG_SCR);
1637
1638 DTLBIMVA tlbiOp(EL1,
1639 haveSecurity && !scr.ns,
1640 mbits(newVal, 31, 12),
1641 bits(newVal, 7,0));
1642
1643 tlbiOp(tc);
1644 return;
1645 }
1646 // Instruction TLB Invalidate by ASID match
1647 case MISCREG_ITLBIASID:
1648 {
1649 assert32();
1650 scr = readMiscReg(MISCREG_SCR);
1651
1652 ITLBIASID tlbiOp(EL1,
1653 haveSecurity && !scr.ns,
1654 bits(newVal, 7,0));
1655
1656 tlbiOp(tc);
1657 return;
1658 }
1659 // Data TLB Invalidate by ASID match
1660 case MISCREG_DTLBIASID:
1661 {
1662 assert32();
1663 scr = readMiscReg(MISCREG_SCR);
1664
1665 DTLBIASID tlbiOp(EL1,
1666 haveSecurity && !scr.ns,
1667 bits(newVal, 7,0));
1668
1669 tlbiOp(tc);
1670 return;
1671 }
1672 // TLB Invalidate All, Non-Secure Non-Hyp
1673 case MISCREG_TLBIALLNSNH:
1674 {
1675 assert32();
1676
1677 TLBIALLN tlbiOp(EL1);
1678 tlbiOp(tc);
1679 return;
1680 }
1681 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1682 case MISCREG_TLBIALLNSNHIS:
1683 {
1684 assert32();
1685
1686 TLBIALLN tlbiOp(EL1);
1687 tlbiOp.broadcast(tc);
1688 return;
1689 }
1690 // TLB Invalidate All, Hyp mode
1691 case MISCREG_TLBIALLH:
1692 {
1693 assert32();
1694
1695 TLBIALLN tlbiOp(EL2);
1696 tlbiOp(tc);
1697 return;
1698 }
1699 // TLB Invalidate All, Hyp mode, Inner Shareable
1700 case MISCREG_TLBIALLHIS:
1701 {
1702 assert32();
1703
1704 TLBIALLN tlbiOp(EL2);
1705 tlbiOp.broadcast(tc);
1706 return;
1707 }
1708 // AArch64 TLB Invalidate All, EL3
1709 case MISCREG_TLBI_ALLE3:
1710 {
1711 assert64();
1712
1713 TLBIALLEL tlbiOp(EL3, true);
1714 tlbiOp(tc);
1715 return;
1716 }
1717 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1718 case MISCREG_TLBI_ALLE3IS:
1719 {
1720 assert64();
1721
1722 TLBIALLEL tlbiOp(EL3, true);
1723 tlbiOp.broadcast(tc);
1724 return;
1725 }
1726 // AArch64 TLB Invalidate All, EL2
1727 case MISCREG_TLBI_ALLE2:
1728 {
1729 assert64();
1730 scr = readMiscReg(MISCREG_SCR);
1731
1732 TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1733 tlbiOp(tc);
1734 return;
1735 }
1736 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1737 case MISCREG_TLBI_ALLE2IS:
1738 {
1739 assert64();
1740 scr = readMiscReg(MISCREG_SCR);
1741
1742 TLBIALLEL tlbiOp(EL2, haveSecurity && !scr.ns);
1743 tlbiOp.broadcast(tc);
1744 return;
1745 }
1746 // AArch64 TLB Invalidate All, EL1
1747 case MISCREG_TLBI_ALLE1:
1748 {
1749 assert64();
1750 scr = readMiscReg(MISCREG_SCR);
1751
1752 TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1753 tlbiOp(tc);
1754 return;
1755 }
1756 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1757 case MISCREG_TLBI_ALLE1IS:
1758 {
1759 assert64();
1760 scr = readMiscReg(MISCREG_SCR);
1761
1762 TLBIALLEL tlbiOp(EL1, haveSecurity && !scr.ns);
1763 tlbiOp.broadcast(tc);
1764 return;
1765 }
1766 case MISCREG_TLBI_VMALLS12E1:
1767 {
1768 assert64();
1769 scr = readMiscReg(MISCREG_SCR);
1770
1771 TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1772 tlbiOp(tc);
1773 return;
1774 }
1775 case MISCREG_TLBI_VMALLE1:
1776 {
1777 assert64();
1778 scr = readMiscReg(MISCREG_SCR);
1779
1780 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1781 bool is_host = (hcr.tge && hcr.e2h);
1782 ExceptionLevel target_el = is_host ? EL2 : EL1;
1783 TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1784 tlbiOp(tc);
1785 return;
1786 }
1787 case MISCREG_TLBI_VMALLS12E1IS:
1788 {
1789 assert64();
1790 scr = readMiscReg(MISCREG_SCR);
1791
1792 TLBIVMALL tlbiOp(EL1, haveSecurity && !scr.ns, true);
1793 tlbiOp.broadcast(tc);
1794 return;
1795 }
1796 case MISCREG_TLBI_VMALLE1IS:
1797 {
1798 assert64();
1799 scr = readMiscReg(MISCREG_SCR);
1800
1801 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1802 bool is_host = (hcr.tge && hcr.e2h);
1803 ExceptionLevel target_el = is_host ? EL2 : EL1;
1804 TLBIVMALL tlbiOp(target_el, haveSecurity && !scr.ns, false);
1805 tlbiOp.broadcast(tc);
1806 return;
1807 }
1808 // VAEx(IS) and VALEx(IS) are the same because TLBs
1809 // only store entries
1810 // from the last level of translation table walks
1811 // AArch64 TLB Invalidate by VA, EL3
1812 case MISCREG_TLBI_VAE3_Xt:
1813 case MISCREG_TLBI_VALE3_Xt:
1814 {
1815 assert64();
1816
1817 TLBIMVA tlbiOp(EL3, true,
1818 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1819 0xbeef);
1820 tlbiOp(tc);
1821 return;
1822 }
1823 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1824 case MISCREG_TLBI_VAE3IS_Xt:
1825 case MISCREG_TLBI_VALE3IS_Xt:
1826 {
1827 assert64();
1828
1829 TLBIMVA tlbiOp(EL3, true,
1830 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1831 0xbeef);
1832
1833 tlbiOp.broadcast(tc);
1834 return;
1835 }
1836 // AArch64 TLB Invalidate by VA, EL2
1837 case MISCREG_TLBI_VAE2_Xt:
1838 case MISCREG_TLBI_VALE2_Xt:
1839 {
1840 assert64();
1841 scr = readMiscReg(MISCREG_SCR);
1842
1843 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1844 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1845 0xbeef);
1846 tlbiOp(tc);
1847 return;
1848 }
1849 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1850 case MISCREG_TLBI_VAE2IS_Xt:
1851 case MISCREG_TLBI_VALE2IS_Xt:
1852 {
1853 assert64();
1854 scr = readMiscReg(MISCREG_SCR);
1855
1856 TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
1857 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1858 0xbeef);
1859
1860 tlbiOp.broadcast(tc);
1861 return;
1862 }
1863 // AArch64 TLB Invalidate by VA, EL1
1864 case MISCREG_TLBI_VAE1_Xt:
1865 case MISCREG_TLBI_VALE1_Xt:
1866 {
1867 assert64();
1868 scr = readMiscReg(MISCREG_SCR);
1869 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1870 bits(newVal, 55, 48);
1871
1872 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1873 bool is_host = (hcr.tge && hcr.e2h);
1874 ExceptionLevel target_el = is_host ? EL2 : EL1;
1875 TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1876 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1877 asid);
1878
1879 tlbiOp(tc);
1880 return;
1881 }
1882 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1883 case MISCREG_TLBI_VAE1IS_Xt:
1884 case MISCREG_TLBI_VALE1IS_Xt:
1885 {
1886 assert64();
1887 scr = readMiscReg(MISCREG_SCR);
1888 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1889 bits(newVal, 55, 48);
1890
1891 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1892 bool is_host = (hcr.tge && hcr.e2h);
1893 ExceptionLevel target_el = is_host ? EL2 : EL1;
1894 TLBIMVA tlbiOp(target_el, haveSecurity && !scr.ns,
1895 static_cast<Addr>(bits(newVal, 43, 0)) << 12,
1896 asid);
1897
1898 tlbiOp.broadcast(tc);
1899 return;
1900 }
1901 // AArch64 TLB Invalidate by ASID, EL1
1902 case MISCREG_TLBI_ASIDE1_Xt:
1903 {
1904 assert64();
1905 scr = readMiscReg(MISCREG_SCR);
1906 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1907 bits(newVal, 55, 48);
1908
1909 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1910 bool is_host = (hcr.tge && hcr.e2h);
1911 ExceptionLevel target_el = is_host ? EL2 : EL1;
1912 TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1913 tlbiOp(tc);
1914 return;
1915 }
1916 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1917 case MISCREG_TLBI_ASIDE1IS_Xt:
1918 {
1919 assert64();
1920 scr = readMiscReg(MISCREG_SCR);
1921 auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
1922 bits(newVal, 55, 48);
1923
1924 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1925 bool is_host = (hcr.tge && hcr.e2h);
1926 ExceptionLevel target_el = is_host ? EL2 : EL1;
1927 TLBIASID tlbiOp(target_el, haveSecurity && !scr.ns, asid);
1928 tlbiOp.broadcast(tc);
1929 return;
1930 }
1931 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1932 // entries from the last level of translation table walks
1933 // AArch64 TLB Invalidate by VA, All ASID, EL1
1934 case MISCREG_TLBI_VAAE1_Xt:
1935 case MISCREG_TLBI_VAALE1_Xt:
1936 {
1937 assert64();
1938 scr = readMiscReg(MISCREG_SCR);
1939
1940 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1941 bool is_host = (hcr.tge && hcr.e2h);
1942 ExceptionLevel target_el = is_host ? EL2 : EL1;
1943 TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1944 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1945
1946 tlbiOp(tc);
1947 return;
1948 }
1949 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1950 case MISCREG_TLBI_VAAE1IS_Xt:
1951 case MISCREG_TLBI_VAALE1IS_Xt:
1952 {
1953 assert64();
1954 scr = readMiscReg(MISCREG_SCR);
1955
1956 HCR hcr = readMiscReg(MISCREG_HCR_EL2);
1957 bool is_host = (hcr.tge && hcr.e2h);
1958 ExceptionLevel target_el = is_host ? EL2 : EL1;
1959 TLBIMVAA tlbiOp(target_el, haveSecurity && !scr.ns,
1960 static_cast<Addr>(bits(newVal, 43, 0)) << 12);
1961
1962 tlbiOp.broadcast(tc);
1963 return;
1964 }
1965 // AArch64 TLB Invalidate by Intermediate Physical Address,
1966 // Stage 2, EL1
1967 case MISCREG_TLBI_IPAS2E1_Xt:
1968 case MISCREG_TLBI_IPAS2LE1_Xt:
1969 {
1970 assert64();
1971 scr = readMiscReg(MISCREG_SCR);
1972
1973 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1974 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1975
1976 tlbiOp(tc);
1977 return;
1978 }
1979 // AArch64 TLB Invalidate by Intermediate Physical Address,
1980 // Stage 2, EL1, Inner Shareable
1981 case MISCREG_TLBI_IPAS2E1IS_Xt:
1982 case MISCREG_TLBI_IPAS2LE1IS_Xt:
1983 {
1984 assert64();
1985 scr = readMiscReg(MISCREG_SCR);
1986
1987 TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
1988 static_cast<Addr>(bits(newVal, 35, 0)) << 12);
1989
1990 tlbiOp.broadcast(tc);
1991 return;
1992 }
1993 case MISCREG_ACTLR:
1994 warn("Not doing anything for write of miscreg ACTLR\n");
1995 break;
1996
1997 case MISCREG_PMXEVTYPER_PMCCFILTR:
1998 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
1999 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
2000 case MISCREG_PMCR ... MISCREG_PMOVSSET:
2001 pmu->setMiscReg(misc_reg, newVal);
2002 break;
2003
2004
2005 case MISCREG_HSTR: // TJDBX, now redifined to be RES0
2006 {
2007 HSTR hstrMask = 0;
2008 hstrMask.tjdbx = 1;
2009 newVal &= ~((uint32_t) hstrMask);
2010 break;
2011 }
2012 case MISCREG_HCPTR:
2013 {
2014 // If a CP bit in NSACR is 0 then the corresponding bit in
2015 // HCPTR is RAO/WI. Same applies to NSASEDIS
2016 secure_lookup = haveSecurity && isSecure(tc);
2017 if (!secure_lookup) {
2018 RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
2019 RegVal mask =
2020 (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
2021 newVal = (newVal & ~mask) | (oldValue & mask);
2022 }
2023 break;
2024 }
2025 case MISCREG_HDFAR: // alias for secure DFAR
2026 misc_reg = MISCREG_DFAR_S;
2027 break;
2028 case MISCREG_HIFAR: // alias for secure IFAR
2029 misc_reg = MISCREG_IFAR_S;
2030 break;
2031 case MISCREG_ATS1CPR:
2032 addressTranslation(TLB::S1CTran, BaseTLB::Read, 0, val);
2033 return;
2034 case MISCREG_ATS1CPW:
2035 addressTranslation(TLB::S1CTran, BaseTLB::Write, 0, val);
2036 return;
2037 case MISCREG_ATS1CUR:
2038 addressTranslation(TLB::S1CTran, BaseTLB::Read,
2039 TLB::UserMode, val);
2040 return;
2041 case MISCREG_ATS1CUW:
2042 addressTranslation(TLB::S1CTran, BaseTLB::Write,
2043 TLB::UserMode, val);
2044 return;
2045 case MISCREG_ATS12NSOPR:
2046 if (!haveSecurity)
2047 panic("Security Extensions required for ATS12NSOPR");
2048 addressTranslation(TLB::S1S2NsTran, BaseTLB::Read, 0, val);
2049 return;
2050 case MISCREG_ATS12NSOPW:
2051 if (!haveSecurity)
2052 panic("Security Extensions required for ATS12NSOPW");
2053 addressTranslation(TLB::S1S2NsTran, BaseTLB::Write, 0, val);
2054 return;
2055 case MISCREG_ATS12NSOUR:
2056 if (!haveSecurity)
2057 panic("Security Extensions required for ATS12NSOUR");
2058 addressTranslation(TLB::S1S2NsTran, BaseTLB::Read,
2059 TLB::UserMode, val);
2060 return;
2061 case MISCREG_ATS12NSOUW:
2062 if (!haveSecurity)
2063 panic("Security Extensions required for ATS12NSOUW");
2064 addressTranslation(TLB::S1S2NsTran, BaseTLB::Write,
2065 TLB::UserMode, val);
2066 return;
2067 case MISCREG_ATS1HR:
2068 addressTranslation(TLB::HypMode, BaseTLB::Read, 0, val);
2069 return;
2070 case MISCREG_ATS1HW:
2071 addressTranslation(TLB::HypMode, BaseTLB::Write, 0, val);
2072 return;
2073 case MISCREG_TTBCR:
2074 {
2075 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2076 const uint32_t ones = (uint32_t)(-1);
2077 TTBCR ttbcrMask = 0;
2078 TTBCR ttbcrNew = newVal;
2079
2080 // ARM DDI 0406C.b, ARMv7-32
2081 ttbcrMask.n = ones; // T0SZ
2082 if (haveSecurity) {
2083 ttbcrMask.pd0 = ones;
2084 ttbcrMask.pd1 = ones;
2085 }
2086 ttbcrMask.epd0 = ones;
2087 ttbcrMask.irgn0 = ones;
2088 ttbcrMask.orgn0 = ones;
2089 ttbcrMask.sh0 = ones;
2090 ttbcrMask.ps = ones; // T1SZ
2091 ttbcrMask.a1 = ones;
2092 ttbcrMask.epd1 = ones;
2093 ttbcrMask.irgn1 = ones;
2094 ttbcrMask.orgn1 = ones;
2095 ttbcrMask.sh1 = ones;
2096 if (haveLPAE)
2097 ttbcrMask.eae = ones;
2098
2099 if (haveLPAE && ttbcrNew.eae) {
2100 newVal = newVal & ttbcrMask;
2101 } else {
2102 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
2103 }
2104 // Invalidate TLB MiscReg
2105 getMMUPtr(tc)->invalidateMiscReg();
2106 break;
2107 }
2108 case MISCREG_TTBR0:
2109 case MISCREG_TTBR1:
2110 {
2111 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2112 if (haveLPAE) {
2113 if (ttbcr.eae) {
2114 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
2115 // ARMv8 AArch32 bit 63-56 only
2116 uint64_t ttbrMask = mask(63,56) | mask(47,40);
2117 newVal = (newVal & (~ttbrMask));
2118 }
2119 }
2120 // Invalidate TLB MiscReg
2121 getMMUPtr(tc)->invalidateMiscReg();
2122 break;
2123 }
2124 case MISCREG_SCTLR_EL1:
2125 case MISCREG_CONTEXTIDR:
2126 case MISCREG_PRRR:
2127 case MISCREG_NMRR:
2128 case MISCREG_MAIR0:
2129 case MISCREG_MAIR1:
2130 case MISCREG_DACR:
2131 case MISCREG_VTTBR:
2132 case MISCREG_SCR_EL3:
2133 case MISCREG_TCR_EL1:
2134 case MISCREG_TCR_EL2:
2135 case MISCREG_TCR_EL3:
2136 case MISCREG_SCTLR_EL2:
2137 case MISCREG_SCTLR_EL3:
2138 case MISCREG_HSCTLR:
2139 case MISCREG_TTBR0_EL1:
2140 case MISCREG_TTBR1_EL1:
2141 case MISCREG_TTBR0_EL2:
2142 case MISCREG_TTBR1_EL2:
2143 case MISCREG_TTBR0_EL3:
2144 getMMUPtr(tc)->invalidateMiscReg();
2145 break;
2146 case MISCREG_HCR_EL2:
2147 {
2148 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
2149 selfDebug->setenableTDETGE((HCR)val, mdcr);
2150 getMMUPtr(tc)->invalidateMiscReg();
2151 }
2152 break;
2153 case MISCREG_NZCV:
2154 {
2155 CPSR cpsr = val;
2156
2157 tc->setCCReg(CCREG_NZ, cpsr.nz);
2158 tc->setCCReg(CCREG_C, cpsr.c);
2159 tc->setCCReg(CCREG_V, cpsr.v);
2160 }
2161 break;
2162 case MISCREG_DAIF:
2163 {
2164 CPSR cpsr = miscRegs[MISCREG_CPSR];
2165 cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
2166 newVal = cpsr;
2167 misc_reg = MISCREG_CPSR;
2168 }
2169 break;
2170 case MISCREG_SP_EL0:
2171 tc->setIntReg(INTREG_SP0, newVal);
2172 break;
2173 case MISCREG_SP_EL1:
2174 tc->setIntReg(INTREG_SP1, newVal);
2175 break;
2176 case MISCREG_SP_EL2:
2177 tc->setIntReg(INTREG_SP2, newVal);
2178 break;
2179 case MISCREG_SPSEL:
2180 {
2181 CPSR cpsr = miscRegs[MISCREG_CPSR];
2182 cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
2183 newVal = cpsr;
2184 misc_reg = MISCREG_CPSR;
2185 }
2186 break;
2187 case MISCREG_CURRENTEL:
2188 {
2189 CPSR cpsr = miscRegs[MISCREG_CPSR];
2190 cpsr.el = (uint8_t) ((CPSR) newVal).el;
2191 newVal = cpsr;
2192 misc_reg = MISCREG_CPSR;
2193 }
2194 break;
2195 case MISCREG_PAN:
2196 {
2197 // PAN is affecting data accesses
2198 getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
2199
2200 CPSR cpsr = miscRegs[MISCREG_CPSR];
2201 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
2202 newVal = cpsr;
2203 misc_reg = MISCREG_CPSR;
2204 }
2205 break;
2206 case MISCREG_AT_S1E1R_Xt:
2207 addressTranslation64(TLB::S1E1Tran, BaseTLB::Read, 0, val);
2208 return;
2209 case MISCREG_AT_S1E1W_Xt:
2210 addressTranslation64(TLB::S1E1Tran, BaseTLB::Write, 0, val);
2211 return;
2212 case MISCREG_AT_S1E0R_Xt:
2213 addressTranslation64(TLB::S1E0Tran, BaseTLB::Read,
2214 TLB::UserMode, val);
2215 return;
2216 case MISCREG_AT_S1E0W_Xt:
2217 addressTranslation64(TLB::S1E0Tran, BaseTLB::Write,
2218 TLB::UserMode, val);
2219 return;
2220 case MISCREG_AT_S1E2R_Xt:
2221 addressTranslation64(TLB::S1E2Tran, BaseTLB::Read, 0, val);
2222 return;
2223 case MISCREG_AT_S1E2W_Xt:
2224 addressTranslation64(TLB::S1E2Tran, BaseTLB::Write, 0, val);
2225 return;
2226 case MISCREG_AT_S12E1R_Xt:
2227 addressTranslation64(TLB::S12E1Tran, BaseTLB::Read, 0, val);
2228 return;
2229 case MISCREG_AT_S12E1W_Xt:
2230 addressTranslation64(TLB::S12E1Tran, BaseTLB::Write, 0, val);
2231 return;
2232 case MISCREG_AT_S12E0R_Xt:
2233 addressTranslation64(TLB::S12E0Tran, BaseTLB::Read,
2234 TLB::UserMode, val);
2235 return;
2236 case MISCREG_AT_S12E0W_Xt:
2237 addressTranslation64(TLB::S12E0Tran, BaseTLB::Write,
2238 TLB::UserMode, val);
2239 return;
2240 case MISCREG_AT_S1E3R_Xt:
2241 addressTranslation64(TLB::S1E3Tran, BaseTLB::Read, 0, val);
2242 return;
2243 case MISCREG_AT_S1E3W_Xt:
2244 addressTranslation64(TLB::S1E3Tran, BaseTLB::Write, 0, val);
2245 return;
2246 case MISCREG_SPSR_EL3:
2247 case MISCREG_SPSR_EL2:
2248 case MISCREG_SPSR_EL1:
2249 {
2250 RegVal spsr_mask = havePAN ?
2251 ~(0x2 << 22) : ~(0x3 << 22);
2252
2253 newVal = val & spsr_mask;
2254 break;
2255 }
2256 case MISCREG_L2CTLR:
2257 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2258 miscRegName[misc_reg], uint32_t(val));
2259 break;
2260
2261 // Generic Timer registers
2262 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
2263 case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
2264 getGenericTimer().setMiscReg(misc_reg, newVal);
2265 break;
2266 case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15:
2267 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
2268 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2269 getGICv3CPUInterface().setMiscReg(misc_reg, newVal);
2270 return;
2271 case MISCREG_ZCR_EL3:
2272 case MISCREG_ZCR_EL2:
2273 case MISCREG_ZCR_EL1:
2274 tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1);
2275 break;
2276 }
2277 }
2278 setMiscRegNoEffect(misc_reg, newVal);
2279 }
2280
2281 BaseISADevice &
2282 ISA::getGenericTimer()
2283 {
2284 // We only need to create an ISA interface the first time we try
2285 // to access the timer.
2286 if (timer)
2287 return *timer.get();
2288
2289 assert(system);
2290 GenericTimer *generic_timer(system->getGenericTimer());
2291 if (!generic_timer) {
2292 panic("Trying to get a generic timer from a system that hasn't "
2293 "been configured to use a generic timer.\n");
2294 }
2295
2296 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
2297 timer->setThreadContext(tc);
2298
2299 return *timer.get();
2300 }
2301
2302 BaseISADevice &
2303 ISA::getGICv3CPUInterface()
2304 {
2305 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
2306 return *gicv3CpuInterface.get();
2307 }
2308
2309 unsigned
2310 ISA::getCurSveVecLenInBits() const
2311 {
2312 if (!FullSystem) {
2313 return sveVL * 128;
2314 }
2315
2316 panic_if(!tc,
2317 "A ThreadContext is needed to determine the SVE vector length "
2318 "in full-system mode");
2319
2320 CPSR cpsr = miscRegs[MISCREG_CPSR];
2321 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
2322
2323 unsigned len = 0;
2324
2325 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) {
2326 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len;
2327 }
2328
2329 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) {
2330 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len;
2331 } else if (haveVirtualization && !isSecure(tc) &&
2332 (el == EL0 || el == EL1)) {
2333 len = std::min(
2334 len,
2335 static_cast<unsigned>(
2336 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len));
2337 }
2338
2339 if (el == EL3) {
2340 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len;
2341 } else if (haveSecurity) {
2342 len = std::min(
2343 len,
2344 static_cast<unsigned>(
2345 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len));
2346 }
2347
2348 len = std::min(len, sveVL - 1);
2349
2350 return (len + 1) * 128;
2351 }
2352
2353 void
2354 ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
2355 {
2356 auto vv = vc.as<uint64_t>();
2357 for (int i = 2; i < eCount; ++i) {
2358 vv[i] = 0;
2359 }
2360 }
2361
2362 void
2363 ISA::serialize(CheckpointOut &cp) const
2364 {
2365 DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
2366 SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2367 }
2368
2369 void
2370 ISA::unserialize(CheckpointIn &cp)
2371 {
2372 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
2373 UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
2374 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
2375 updateRegMap(tmp_cpsr);
2376 }
2377
2378 void
2379 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
2380 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2381 {
2382 // If we're in timing mode then doing the translation in
2383 // functional mode then we're slightly distorting performance
2384 // results obtained from simulations. The translation should be
2385 // done in the same mode the core is running in. NOTE: This
2386 // can't be an atomic translation because that causes problems
2387 // with unexpected atomic snoop requests.
2388 warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2389
2390 auto req = std::make_shared<Request>(
2391 val, 0, flags, Request::funcRequestorId,
2392 tc->pcState().pc(), tc->contextId());
2393
2394 Fault fault = getMMUPtr(tc)->translateFunctional(
2395 req, tc, mode, tran_type);
2396
2397 PAR par = 0;
2398 if (fault == NoFault) {
2399 Addr paddr = req->getPaddr();
2400 uint64_t attr = getMMUPtr(tc)->getAttr();
2401 uint64_t attr1 = attr >> 56;
2402 if (!attr1 || attr1 ==0x44) {
2403 attr |= 0x100;
2404 attr &= ~ uint64_t(0x80);
2405 }
2406 par = (paddr & mask(47, 12)) | attr;
2407 DPRINTF(MiscRegs,
2408 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2409 val, par);
2410 } else {
2411 ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2412 arm_fault->update(tc);
2413 // Set fault bit and FSR
2414 FSR fsr = arm_fault->getFsr(tc);
2415
2416 par.f = 1; // F bit
2417 par.fst = fsr.status; // FST
2418 par.ptw = (arm_fault->iss() >> 7) & 0x1; // S1PTW
2419 par.s = arm_fault->isStage2() ? 1 : 0; // S
2420
2421 DPRINTF(MiscRegs,
2422 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2423 val, fsr, par);
2424 }
2425 setMiscRegNoEffect(MISCREG_PAR_EL1, par);
2426 return;
2427 }
2428
2429 void
2430 ISA::addressTranslation(TLB::ArmTranslationType tran_type,
2431 BaseTLB::Mode mode, Request::Flags flags, RegVal val)
2432 {
2433 // If we're in timing mode then doing the translation in
2434 // functional mode then we're slightly distorting performance
2435 // results obtained from simulations. The translation should be
2436 // done in the same mode the core is running in. NOTE: This
2437 // can't be an atomic translation because that causes problems
2438 // with unexpected atomic snoop requests.
2439 warn_once("Doing AT (address translation) in functional mode! Fix Me!\n");
2440
2441 auto req = std::make_shared<Request>(
2442 val, 0, flags, Request::funcRequestorId,
2443 tc->pcState().pc(), tc->contextId());
2444
2445 Fault fault = getMMUPtr(tc)->translateFunctional(
2446 req, tc, mode, tran_type);
2447
2448 PAR par = 0;
2449 if (fault == NoFault) {
2450 Addr paddr = req->getPaddr();
2451 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
2452 HCR hcr = readMiscRegNoEffect(MISCREG_HCR);
2453
2454 uint8_t max_paddr_bit = 0;
2455 if (haveLPAE && (ttbcr.eae || tran_type & TLB::HypMode ||
2456 ((tran_type & TLB::S1S2NsTran) && hcr.vm) )) {
2457
2458 max_paddr_bit = 39;
2459 } else {
2460 max_paddr_bit = 31;
2461 }
2462
2463 par = (paddr & mask(max_paddr_bit, 12)) |
2464 (getMMUPtr(tc)->getAttr());
2465
2466 DPRINTF(MiscRegs,
2467 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
2468 val, par);
2469 } else {
2470 ArmFault *arm_fault = static_cast<ArmFault *>(fault.get());
2471 arm_fault->update(tc);
2472 // Set fault bit and FSR
2473 FSR fsr = arm_fault->getFsr(tc);
2474
2475 par.f = 0x1; // F bit
2476 par.lpae = fsr.lpae;
2477 par.ptw = (arm_fault->iss() >> 7) & 0x1;
2478 par.s = arm_fault->isStage2() ? 1 : 0;
2479
2480 if (par.lpae) {
2481 // LPAE - rearange fault status
2482 par.fst = fsr.status;
2483 } else {
2484 // VMSA - rearange fault status
2485 par.fs4_0 = fsr.fsLow | (fsr.fsHigh << 5);
2486 par.fs5 = fsr.ext;
2487 }
2488 DPRINTF(MiscRegs,
2489 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
2490 val, fsr, par);
2491 }
2492 setMiscRegNoEffect(MISCREG_PAR, par);
2493 return;
2494 }
2495
2496 ISA::MiscRegLUTEntryInitializer::chain
2497 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
2498 {
2499 switch (FullSystem ? sys->highestEL() : EL1) {
2500 case EL0:
2501 case EL1: priv(); break;
2502 case EL2: hyp(); break;
2503 case EL3: mon(); break;
2504 }
2505 return *this;
2506 }
2507
2508 } // namespace ArmISA