2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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41 #include "arch/arm/isa.hh"
47 ISA::readMiscRegNoEffect(int misc_reg
)
49 assert(misc_reg
< NumMiscRegs
);
50 if (misc_reg
== MISCREG_SPSR
) {
51 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
54 return miscRegs
[MISCREG_SPSR
];
56 return miscRegs
[MISCREG_SPSR_FIQ
];
58 return miscRegs
[MISCREG_SPSR_IRQ
];
60 return miscRegs
[MISCREG_SPSR_SVC
];
62 return miscRegs
[MISCREG_SPSR_MON
];
64 return miscRegs
[MISCREG_SPSR_ABT
];
66 return miscRegs
[MISCREG_SPSR_UND
];
68 return miscRegs
[MISCREG_SPSR
];
71 return miscRegs
[misc_reg
];
76 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
78 if (misc_reg
== MISCREG_CPSR
) {
79 CPSR cpsr
= miscRegs
[misc_reg
];
80 Addr pc
= tc
->readPC();
81 if (pc
& (ULL(1) << PcJBitShift
))
85 if (pc
& (ULL(1) << PcTBitShift
))
91 if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
92 misc_reg
< MISCREG_CP15_END
) {
93 panic("Unimplemented CP15 register %s read.\n",
94 miscRegName
[misc_reg
]);
98 warn("The clidr register always reports 0 caches.\n");
101 warn("The ccsidr register isn't implemented and "
102 "always reads as 0.\n");
104 case MISCREG_ID_PFR0
:
105 return 0x1031; // ThumbEE | !Jazelle | Thumb | ARM
107 return readMiscRegNoEffect(misc_reg
);
111 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
113 assert(misc_reg
< NumMiscRegs
);
114 if (misc_reg
== MISCREG_SPSR
) {
115 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
118 miscRegs
[MISCREG_SPSR
] = val
;
121 miscRegs
[MISCREG_SPSR_FIQ
] = val
;
124 miscRegs
[MISCREG_SPSR_IRQ
] = val
;
127 miscRegs
[MISCREG_SPSR_SVC
] = val
;
130 miscRegs
[MISCREG_SPSR_MON
] = val
;
133 miscRegs
[MISCREG_SPSR_ABT
] = val
;
136 miscRegs
[MISCREG_SPSR_UND
] = val
;
139 miscRegs
[MISCREG_SPSR
] = val
;
143 miscRegs
[misc_reg
] = val
;
147 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
149 MiscReg newVal
= val
;
150 if (misc_reg
== MISCREG_CPSR
) {
153 DPRINTF(Arm
, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
154 cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
155 Addr npc
= tc
->readNextPC() & ~PcModeMask
;
157 npc
= npc
| (ULL(1) << PcJBitShift
);
159 npc
= npc
| (ULL(1) << PcTBitShift
);
163 if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
164 misc_reg
< MISCREG_CP15_END
) {
165 panic("Unimplemented CP15 register %s wrote with %#x.\n",
166 miscRegName
[misc_reg
], val
);
172 CPACR valCpacr
= val
;
173 newCpacr
.cp10
= valCpacr
.cp10
;
174 newCpacr
.cp11
= valCpacr
.cp11
;
175 if (newCpacr
.cp10
!= 0x3 || newCpacr
.cp11
!= 3) {
176 panic("Disabling coprocessors isn't implemented.\n");
182 warn("The csselr register isn't implemented.\n");
186 const uint32_t ones
= (uint32_t)(-1);
188 fpscrMask
.ioc
= ones
;
189 fpscrMask
.dzc
= ones
;
190 fpscrMask
.ofc
= ones
;
191 fpscrMask
.ufc
= ones
;
192 fpscrMask
.ixc
= ones
;
193 fpscrMask
.idc
= ones
;
194 fpscrMask
.len
= ones
;
195 fpscrMask
.stride
= ones
;
196 fpscrMask
.rMode
= ones
;
199 fpscrMask
.ahp
= ones
;
205 newVal
= (newVal
& (uint32_t)fpscrMask
) |
206 (miscRegs
[MISCREG_FPSCR
] & ~(uint32_t)fpscrMask
);
211 const uint32_t fpexcMask
= 0x60000000;
212 newVal
= (newVal
& fpexcMask
) |
213 (miscRegs
[MISCREG_FPEXC
] & ~fpexcMask
);
218 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
219 SCTLR sctlr
= miscRegs
[MISCREG_SCTLR
];
220 SCTLR new_sctlr
= newVal
;
221 new_sctlr
.nmfi
= (bool)sctlr
.nmfi
;
222 miscRegs
[MISCREG_SCTLR
] = (MiscReg
)new_sctlr
;
231 case MISCREG_TLBIALLIS
:
232 case MISCREG_TLBIALL
:
233 warn("Need to flush all TLBs in MP\n");
234 tc
->getITBPtr()->flushAll();
235 tc
->getDTBPtr()->flushAll();
237 case MISCREG_ITLBIALL
:
238 tc
->getITBPtr()->flushAll();
240 case MISCREG_DTLBIALL
:
241 tc
->getDTBPtr()->flushAll();
243 case MISCREG_TLBIMVAIS
:
244 case MISCREG_TLBIMVA
:
245 warn("Need to flush all TLBs in MP\n");
246 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
248 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
251 case MISCREG_TLBIASIDIS
:
252 case MISCREG_TLBIASID
:
253 warn("Need to flush all TLBs in MP\n");
254 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
255 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
257 case MISCREG_TLBIMVAAIS
:
258 case MISCREG_TLBIMVAA
:
259 warn("Need to flush all TLBs in MP\n");
260 tc
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
261 tc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
263 case MISCREG_ITLBIMVA
:
264 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
267 case MISCREG_DTLBIMVA
:
268 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
271 case MISCREG_ITLBIASID
:
272 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
274 case MISCREG_DTLBIASID
:
275 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
278 setMiscRegNoEffect(misc_reg
, newVal
);