2 * Copyright (c) 2010-2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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41 #include "arch/arm/isa.hh"
42 #include "config/use_checker.hh"
43 #include "debug/Arm.hh"
44 #include "debug/MiscRegs.hh"
45 #include "sim/faults.hh"
46 #include "sim/stat_control.hh"
47 #include "sim/system.hh"
50 #include "cpu/checker/cpu.hh"
59 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
60 uint32_t midr
= miscRegs
[MISCREG_MIDR
];
61 memset(miscRegs
, 0, sizeof(miscRegs
));
63 cpsr
.mode
= MODE_USER
;
64 miscRegs
[MISCREG_CPSR
] = cpsr
;
68 sctlr
.te
= (bool)sctlr_rst
.te
;
69 sctlr
.nmfi
= (bool)sctlr_rst
.nmfi
;
70 sctlr
.v
= (bool)sctlr_rst
.v
;
76 miscRegs
[MISCREG_SCTLR
] = sctlr
;
77 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
79 // Preserve MIDR accross reset
80 miscRegs
[MISCREG_MIDR
] = midr
;
82 /* Start with an event in the mailbox */
83 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
85 // Separate Instruction and Data TLBs.
86 miscRegs
[MISCREG_TLBTR
] = 1;
89 mvfr0
.advSimdRegisters
= 2;
90 mvfr0
.singlePrecision
= 2;
91 mvfr0
.doublePrecision
= 2;
92 mvfr0
.vfpExceptionTrapping
= 0;
95 mvfr0
.shortVectors
= 1;
96 mvfr0
.roundingModes
= 1;
97 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
100 mvfr1
.flushToZero
= 1;
101 mvfr1
.defaultNaN
= 1;
102 mvfr1
.advSimdLoadStore
= 1;
103 mvfr1
.advSimdInteger
= 1;
104 mvfr1
.advSimdSinglePrecision
= 1;
105 mvfr1
.advSimdHalfPrecision
= 1;
106 mvfr1
.vfpHalfPrecision
= 1;
107 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
109 miscRegs
[MISCREG_MPIDR
] = 0;
111 // Reset values of PRRR and NMRR are implementation dependent
113 miscRegs
[MISCREG_PRRR
] =
126 miscRegs
[MISCREG_NMRR
] =
143 miscRegs
[MISCREG_CPACR
] = 0;
144 miscRegs
[MISCREG_FPSID
] = 0x410430A0;
146 // See section B4.1.84 of ARM ARM
147 // All values are latest for ARMv7-A profile
148 miscRegs
[MISCREG_ID_ISAR0
] = 0x02101111;
149 miscRegs
[MISCREG_ID_ISAR1
] = 0x02112111;
150 miscRegs
[MISCREG_ID_ISAR2
] = 0x21232141;
151 miscRegs
[MISCREG_ID_ISAR3
] = 0x01112131;
152 miscRegs
[MISCREG_ID_ISAR4
] = 0x10010142;
153 miscRegs
[MISCREG_ID_ISAR5
] = 0x00000000;
155 //XXX We need to initialize the rest of the state.
159 ISA::readMiscRegNoEffect(int misc_reg
)
161 assert(misc_reg
< NumMiscRegs
);
164 if (misc_reg
== MISCREG_SPSR
)
165 flat_idx
= flattenMiscIndex(misc_reg
);
168 MiscReg val
= miscRegs
[flat_idx
];
170 DPRINTF(MiscRegs
, "Reading From misc reg %d (%d) : %#x\n",
171 misc_reg
, flat_idx
, val
);
177 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
179 if (misc_reg
== MISCREG_CPSR
) {
180 CPSR cpsr
= miscRegs
[misc_reg
];
181 PCState pc
= tc
->pcState();
182 cpsr
.j
= pc
.jazelle() ? 1 : 0;
183 cpsr
.t
= pc
.thumb() ? 1 : 0;
186 if (misc_reg
>= MISCREG_CP15_UNIMP_START
)
187 panic("Unimplemented CP15 register %s read.\n",
188 miscRegName
[misc_reg
]);
194 case MISCREG_ID_MMFR0
:
195 return 0x03; // VMSAv7 support
196 case MISCREG_ID_MMFR2
:
197 return 0x01230000; // no HW access | WFI stalling | ISB and DSB
198 // | all TLB maintenance | no Harvard
199 case MISCREG_ID_MMFR3
:
200 return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
201 // BP Maint | Cache Maint Set/way | Cache Maint MVA
203 warn_once("The clidr register always reports 0 caches.\n");
204 warn_once("clidr LoUIS field of 0b001 to match current "
205 "ARM implementations.\n");
208 warn_once("The ccsidr register isn't implemented and "
209 "always reads as 0.\n");
211 case MISCREG_ID_PFR0
:
212 warn("Returning thumbEE disabled for now since we don't support CP14"
213 "config registers and jumping to ThumbEE vectors\n");
214 return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
215 case MISCREG_ID_PFR1
:
216 warn("reading unimplmented register ID_PFR1");
219 return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
221 warn("Not doing anything for miscreg ACTLR\n");
224 case MISCREG_PMCCNTR
:
226 warn("Not doing anything for read to miscreg %s\n",
227 miscRegName
[misc_reg
]);
230 panic("shouldn't be reading this register seperately\n");
231 case MISCREG_FPSCR_QC
:
232 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
233 case MISCREG_FPSCR_EXC
:
234 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
236 // mostly unimplemented, just set NumCPUs field from sim and return
238 // b00:1CPU to b11:4CPUs
239 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
242 return readMiscRegNoEffect(misc_reg
);
246 ISA::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
248 assert(misc_reg
< NumMiscRegs
);
251 if (misc_reg
== MISCREG_SPSR
)
252 flat_idx
= flattenMiscIndex(misc_reg
);
255 miscRegs
[flat_idx
] = val
;
257 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n", misc_reg
,
262 ISA::setMiscReg(int misc_reg
, const MiscReg
&val
, ThreadContext
*tc
)
265 MiscReg newVal
= val
;
270 if (misc_reg
== MISCREG_CPSR
) {
274 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
275 int old_mode
= old_cpsr
.mode
;
277 if (old_mode
!= cpsr
.mode
) {
278 tc
->getITBPtr()->invalidateMiscReg();
279 tc
->getDTBPtr()->invalidateMiscReg();
282 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
283 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
284 PCState pc
= tc
->pcState();
285 pc
.nextThumb(cpsr
.t
);
286 pc
.nextJazelle(cpsr
.j
);
288 tc
->pcStateNoRecord(pc
);
292 } else if (misc_reg
>= MISCREG_CP15_UNIMP_START
&&
293 misc_reg
< MISCREG_CP15_END
) {
294 panic("Unimplemented CP15 register %s wrote with %#x.\n",
295 miscRegName
[misc_reg
], val
);
301 const uint32_t ones
= (uint32_t)(-1);
303 // Only cp10, cp11, and ase are implemented, nothing else should
305 cpacrMask
.cp10
= ones
;
306 cpacrMask
.cp11
= ones
;
307 cpacrMask
.asedis
= ones
;
309 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
310 miscRegName
[misc_reg
], newVal
);
314 warn_once("The csselr register isn't implemented.\n");
318 const uint32_t ones
= (uint32_t)(-1);
320 fpscrMask
.ioc
= ones
;
321 fpscrMask
.dzc
= ones
;
322 fpscrMask
.ofc
= ones
;
323 fpscrMask
.ufc
= ones
;
324 fpscrMask
.ixc
= ones
;
325 fpscrMask
.idc
= ones
;
326 fpscrMask
.len
= ones
;
327 fpscrMask
.stride
= ones
;
328 fpscrMask
.rMode
= ones
;
331 fpscrMask
.ahp
= ones
;
337 newVal
= (newVal
& (uint32_t)fpscrMask
) |
338 (miscRegs
[MISCREG_FPSCR
] & ~(uint32_t)fpscrMask
);
343 assert(!(newVal
& ~CpsrMaskQ
));
344 newVal
= miscRegs
[MISCREG_CPSR
] | newVal
;
345 misc_reg
= MISCREG_CPSR
;
348 case MISCREG_FPSCR_QC
:
350 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrQcMask
);
351 misc_reg
= MISCREG_FPSCR
;
354 case MISCREG_FPSCR_EXC
:
356 newVal
= miscRegs
[MISCREG_FPSCR
] | (newVal
& FpscrExcMask
);
357 misc_reg
= MISCREG_FPSCR
;
362 // vfpv3 architecture, section B.6.1 of DDI04068
363 // bit 29 - valid only if fpexc[31] is 0
364 const uint32_t fpexcMask
= 0x60000000;
365 newVal
= (newVal
& fpexcMask
) |
366 (miscRegs
[MISCREG_FPEXC
] & ~fpexcMask
);
371 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
372 SCTLR sctlr
= miscRegs
[MISCREG_SCTLR
];
373 SCTLR new_sctlr
= newVal
;
374 new_sctlr
.nmfi
= (bool)sctlr
.nmfi
;
375 miscRegs
[MISCREG_SCTLR
] = (MiscReg
)new_sctlr
;
376 tc
->getITBPtr()->invalidateMiscReg();
377 tc
->getDTBPtr()->invalidateMiscReg();
379 // Check if all CPUs are booted with caches enabled
380 // so we can stop enforcing coherency of some kernel
381 // structures manually.
382 sys
= tc
->getSystemPtr();
383 for (x
= 0; x
< sys
->numContexts(); x
++) {
384 oc
= sys
->getThreadContext(x
);
385 SCTLR other_sctlr
= oc
->readMiscRegNoEffect(MISCREG_SCTLR
);
386 if (!other_sctlr
.c
&& oc
->status() != ThreadContext::Halted
)
390 for (x
= 0; x
< sys
->numContexts(); x
++) {
391 oc
= sys
->getThreadContext(x
);
392 oc
->getDTBPtr()->allCpusCaching();
393 oc
->getITBPtr()->allCpusCaching();
395 CheckerCPU
*checker
=
396 dynamic_cast<CheckerCPU
*>(oc
->getCheckerCpuPtr());
398 checker
->getDTBPtr()->allCpusCaching();
399 checker
->getITBPtr()->allCpusCaching();
411 case MISCREG_TLBIALLIS
:
412 case MISCREG_TLBIALL
:
413 sys
= tc
->getSystemPtr();
414 for (x
= 0; x
< sys
->numContexts(); x
++) {
415 oc
= sys
->getThreadContext(x
);
416 assert(oc
->getITBPtr() && oc
->getDTBPtr());
417 oc
->getITBPtr()->flushAll();
418 oc
->getDTBPtr()->flushAll();
420 CheckerCPU
*checker
=
421 dynamic_cast<CheckerCPU
*>(oc
->getCheckerCpuPtr());
423 checker
->getITBPtr()->flushAll();
424 checker
->getDTBPtr()->flushAll();
429 case MISCREG_ITLBIALL
:
430 tc
->getITBPtr()->flushAll();
432 case MISCREG_DTLBIALL
:
433 tc
->getDTBPtr()->flushAll();
435 case MISCREG_TLBIMVAIS
:
436 case MISCREG_TLBIMVA
:
437 sys
= tc
->getSystemPtr();
438 for (x
= 0; x
< sys
->numContexts(); x
++) {
439 oc
= sys
->getThreadContext(x
);
440 assert(oc
->getITBPtr() && oc
->getDTBPtr());
441 oc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
443 oc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
446 CheckerCPU
*checker
=
447 dynamic_cast<CheckerCPU
*>(oc
->getCheckerCpuPtr());
449 checker
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
451 checker
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
457 case MISCREG_TLBIASIDIS
:
458 case MISCREG_TLBIASID
:
459 sys
= tc
->getSystemPtr();
460 for (x
= 0; x
< sys
->numContexts(); x
++) {
461 oc
= sys
->getThreadContext(x
);
462 assert(oc
->getITBPtr() && oc
->getDTBPtr());
463 oc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
464 oc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
466 CheckerCPU
*checker
=
467 dynamic_cast<CheckerCPU
*>(oc
->getCheckerCpuPtr());
469 checker
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
470 checker
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
475 case MISCREG_TLBIMVAAIS
:
476 case MISCREG_TLBIMVAA
:
477 sys
= tc
->getSystemPtr();
478 for (x
= 0; x
< sys
->numContexts(); x
++) {
479 oc
= sys
->getThreadContext(x
);
480 assert(oc
->getITBPtr() && oc
->getDTBPtr());
481 oc
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
482 oc
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
484 CheckerCPU
*checker
=
485 dynamic_cast<CheckerCPU
*>(oc
->getCheckerCpuPtr());
487 checker
->getITBPtr()->flushMva(mbits(newVal
, 31,12));
488 checker
->getDTBPtr()->flushMva(mbits(newVal
, 31,12));
493 case MISCREG_ITLBIMVA
:
494 tc
->getITBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
497 case MISCREG_DTLBIMVA
:
498 tc
->getDTBPtr()->flushMvaAsid(mbits(newVal
, 31, 12),
501 case MISCREG_ITLBIASID
:
502 tc
->getITBPtr()->flushAsid(bits(newVal
, 7,0));
504 case MISCREG_DTLBIASID
:
505 tc
->getDTBPtr()->flushAsid(bits(newVal
, 7,0));
508 warn("Not doing anything for write of miscreg ACTLR\n");
512 // Performance counters not implemented. Instead, interpret
513 // a reset command to this register to reset the simulator
515 // PMCR_E | PMCR_P | PMCR_C
516 const int ResetAndEnableCounters
= 0x7;
517 if (newVal
== ResetAndEnableCounters
) {
518 inform("Resetting all simobject stats\n");
519 Stats::schedStatEvent(false, true);
523 case MISCREG_PMCCNTR
:
525 warn("Not doing anything for write to miscreg %s\n",
526 miscRegName
[misc_reg
]);
528 case MISCREG_V2PCWPR
:
529 case MISCREG_V2PCWPW
:
530 case MISCREG_V2PCWUR
:
531 case MISCREG_V2PCWUW
:
532 case MISCREG_V2POWPR
:
533 case MISCREG_V2POWPW
:
534 case MISCREG_V2POWUR
:
535 case MISCREG_V2POWUW
:
537 RequestPtr req
= new Request
;
542 case MISCREG_V2PCWPR
:
543 flags
= TLB::MustBeOne
;
544 mode
= BaseTLB::Read
;
546 case MISCREG_V2PCWPW
:
547 flags
= TLB::MustBeOne
;
548 mode
= BaseTLB::Write
;
550 case MISCREG_V2PCWUR
:
551 flags
= TLB::MustBeOne
| TLB::UserMode
;
552 mode
= BaseTLB::Read
;
554 case MISCREG_V2PCWUW
:
555 flags
= TLB::MustBeOne
| TLB::UserMode
;
556 mode
= BaseTLB::Write
;
559 panic("Security Extensions not implemented!");
561 warn("Translating via MISCREG in atomic mode! Fix Me!\n");
562 req
->setVirt(0, val
, 1, flags
, tc
->pcState().pc(),
563 Request::funcMasterId
);
564 fault
= tc
->getDTBPtr()->translateAtomic(req
, tc
, mode
);
565 if (fault
== NoFault
) {
566 miscRegs
[MISCREG_PAR
] =
567 (req
->getPaddr() & 0xfffff000) |
568 (tc
->getDTBPtr()->getAttr() );
570 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
571 val
, miscRegs
[MISCREG_PAR
]);
574 // Set fault bit and FSR
575 FSR fsr
= miscRegs
[MISCREG_DFSR
];
576 miscRegs
[MISCREG_PAR
] =
584 case MISCREG_CONTEXTIDR
:
588 tc
->getITBPtr()->invalidateMiscReg();
589 tc
->getDTBPtr()->invalidateMiscReg();
591 case MISCREG_CPSR_MODE
:
592 // This miscreg is used by copy*Regs to set the CPSR mode
593 // without updating other CPSR variables. It's used to
594 // make sure the register map is in such a state that we can
595 // see all of the registers for the copy.
599 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
600 miscRegName
[misc_reg
], uint32_t(val
));
603 setMiscRegNoEffect(misc_reg
, newVal
);