2 * Copyright (c) 2010-2020 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "arch/arm/isa.hh"
40 #include "arch/arm/faults.hh"
41 #include "arch/arm/interrupts.hh"
42 #include "arch/arm/pmu.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/tlb.hh"
45 #include "arch/arm/tlbi_op.hh"
46 #include "cpu/base.hh"
47 #include "cpu/checker/cpu.hh"
48 #include "debug/Arm.hh"
49 #include "debug/MiscRegs.hh"
50 #include "dev/arm/generic_timer.hh"
51 #include "dev/arm/gic_v3.hh"
52 #include "dev/arm/gic_v3_cpu_interface.hh"
53 #include "params/ArmISA.hh"
54 #include "sim/faults.hh"
55 #include "sim/stat_control.hh"
56 #include "sim/system.hh"
61 ISA::ISA(Params
*p
) : BaseISA(p
), system(NULL
),
62 _decoderFlavor(p
->decoderFlavor
), _vecRegRenameMode(Enums::Full
),
63 pmu(p
->pmu
), haveGICv3CPUInterface(false), impdefAsNop(p
->impdef_nop
),
66 miscRegs
[MISCREG_SCTLR_RST
] = 0;
68 // Hook up a dummy device if we haven't been configured with a
69 // real PMU. By using a dummy device, we don't need to check that
70 // the PMU exist every time we try to access a PMU register.
74 // Give all ISA devices a pointer to this ISA
77 system
= dynamic_cast<ArmSystem
*>(p
->system
);
79 // Cache system-level properties
80 if (FullSystem
&& system
) {
81 highestELIs64
= system
->highestELIs64();
82 haveSecurity
= system
->haveSecurity();
83 haveLPAE
= system
->haveLPAE();
84 haveCrypto
= system
->haveCrypto();
85 haveVirtualization
= system
->haveVirtualization();
86 haveLargeAsid64
= system
->haveLargeAsid64();
87 physAddrRange
= system
->physAddrRange();
88 haveSVE
= system
->haveSVE();
89 havePAN
= system
->havePAN();
90 sveVL
= system
->sveVL();
91 haveLSE
= system
->haveLSE();
93 highestELIs64
= true; // ArmSystem::highestELIs64 does the same
94 haveSecurity
= haveLPAE
= haveVirtualization
= false;
96 haveLargeAsid64
= false;
97 physAddrRange
= 32; // dummy value
100 sveVL
= p
->sve_vl_se
;
104 // Initial rename mode depends on highestEL
105 const_cast<Enums::VecRegRenameMode
&>(_vecRegRenameMode
) =
106 highestELIs64
? Enums::Full
: Enums::Elem
;
108 initializeMiscRegMetadata();
109 preUnflattenMiscReg();
114 std::vector
<struct ISA::MiscRegLUTEntry
> ISA::lookUpMiscReg(NUM_MISCREGS
);
119 return dynamic_cast<const Params
*>(_params
);
123 ISA::clear(ThreadContext
*tc
)
126 // Invalidate cached copies of miscregs in the TLBs
127 getITBPtr(tc
)->invalidateMiscReg();
128 getDTBPtr(tc
)->invalidateMiscReg();
134 const Params
*p(params());
136 SCTLR sctlr_rst
= miscRegs
[MISCREG_SCTLR_RST
];
137 memset(miscRegs
, 0, sizeof(miscRegs
));
141 // We always initialize AArch64 ID registers even
142 // if we are in AArch32. This is done since if we
143 // are in SE mode we don't know if our ArmProcess is
144 // AArch32 or AArch64
147 // Start with an event in the mailbox
148 miscRegs
[MISCREG_SEV_MAILBOX
] = 1;
150 // Separate Instruction and Data TLBs
151 miscRegs
[MISCREG_TLBTR
] = 1;
154 mvfr0
.advSimdRegisters
= 2;
155 mvfr0
.singlePrecision
= 2;
156 mvfr0
.doublePrecision
= 2;
157 mvfr0
.vfpExceptionTrapping
= 0;
159 mvfr0
.squareRoot
= 1;
160 mvfr0
.shortVectors
= 1;
161 mvfr0
.roundingModes
= 1;
162 miscRegs
[MISCREG_MVFR0
] = mvfr0
;
165 mvfr1
.flushToZero
= 1;
166 mvfr1
.defaultNaN
= 1;
167 mvfr1
.advSimdLoadStore
= 1;
168 mvfr1
.advSimdInteger
= 1;
169 mvfr1
.advSimdSinglePrecision
= 1;
170 mvfr1
.advSimdHalfPrecision
= 1;
171 mvfr1
.vfpHalfPrecision
= 1;
172 miscRegs
[MISCREG_MVFR1
] = mvfr1
;
174 // Reset values of PRRR and NMRR are implementation dependent
176 // @todo: PRRR and NMRR in secure state?
177 miscRegs
[MISCREG_PRRR_NS
] =
191 miscRegs
[MISCREG_NMRR_NS
] =
208 if (FullSystem
&& system
->highestELIs64()) {
209 // Initialize AArch64 state
214 // Initialize AArch32 state...
215 clear32(p
, sctlr_rst
);
219 ISA::clear32(const ArmISAParams
*p
, const SCTLR
&sctlr_rst
)
222 cpsr
.mode
= MODE_USER
;
225 miscRegs
[MISCREG_MVBAR
] = system
->resetAddr();
228 miscRegs
[MISCREG_CPSR
] = cpsr
;
232 sctlr
.te
= (bool) sctlr_rst
.te
;
233 sctlr
.nmfi
= (bool) sctlr_rst
.nmfi
;
234 sctlr
.v
= (bool) sctlr_rst
.v
;
239 sctlr
.rao4
= 0xf; // SCTLR[6:3]
242 miscRegs
[MISCREG_SCTLR_NS
] = sctlr
;
243 miscRegs
[MISCREG_SCTLR_RST
] = sctlr_rst
;
244 miscRegs
[MISCREG_HCPTR
] = 0;
246 miscRegs
[MISCREG_CPACR
] = 0;
248 miscRegs
[MISCREG_FPSID
] = p
->fpsid
;
251 TTBCR ttbcr
= miscRegs
[MISCREG_TTBCR_NS
];
253 miscRegs
[MISCREG_TTBCR_NS
] = ttbcr
;
254 // Enforce consistency with system-level settings
255 miscRegs
[MISCREG_ID_MMFR0
] = (miscRegs
[MISCREG_ID_MMFR0
] & ~0xf) | 0x5;
259 miscRegs
[MISCREG_SCTLR_S
] = sctlr
;
260 miscRegs
[MISCREG_SCR
] = 0;
261 miscRegs
[MISCREG_VBAR_S
] = 0;
263 // we're always non-secure
264 miscRegs
[MISCREG_SCR
] = 1;
267 //XXX We need to initialize the rest of the state.
271 ISA::clear64(const ArmISAParams
*p
)
274 Addr rvbar
= system
->resetAddr();
275 switch (system
->highestEL()) {
276 // Set initial EL to highest implemented EL using associated stack
277 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
280 cpsr
.mode
= MODE_EL3H
;
281 miscRegs
[MISCREG_RVBAR_EL3
] = rvbar
;
284 cpsr
.mode
= MODE_EL2H
;
285 miscRegs
[MISCREG_RVBAR_EL2
] = rvbar
;
288 cpsr
.mode
= MODE_EL1H
;
289 miscRegs
[MISCREG_RVBAR_EL1
] = rvbar
;
292 panic("Invalid highest implemented exception level");
296 // Initialize rest of CPSR
297 cpsr
.daif
= 0xf; // Mask all interrupts
300 miscRegs
[MISCREG_CPSR
] = cpsr
;
303 // Initialize other control registers
304 miscRegs
[MISCREG_MPIDR_EL1
] = 0x80000000;
306 miscRegs
[MISCREG_SCTLR_EL3
] = 0x30c50830;
307 miscRegs
[MISCREG_SCR_EL3
] = 0x00000030; // RES1 fields
308 } else if (haveVirtualization
) {
309 // also MISCREG_SCTLR_EL2 (by mapping)
310 miscRegs
[MISCREG_HSCTLR
] = 0x30c50830;
312 // also MISCREG_SCTLR_EL1 (by mapping)
313 miscRegs
[MISCREG_SCTLR_NS
] = 0x30d00800 | 0x00050030; // RES1 | init
315 miscRegs
[MISCREG_SCR_EL3
] = 1;
320 ISA::initID32(const ArmISAParams
*p
)
322 // Initialize configurable default values
327 else if (highestELIs64
)
328 // Cortex-A57 TRM r0p0 MIDR
331 // Cortex-A15 TRM r0p0 MIDR
334 miscRegs
[MISCREG_MIDR
] = midr
;
335 miscRegs
[MISCREG_MIDR_EL1
] = midr
;
336 miscRegs
[MISCREG_VPIDR
] = midr
;
338 miscRegs
[MISCREG_ID_ISAR0
] = p
->id_isar0
;
339 miscRegs
[MISCREG_ID_ISAR1
] = p
->id_isar1
;
340 miscRegs
[MISCREG_ID_ISAR2
] = p
->id_isar2
;
341 miscRegs
[MISCREG_ID_ISAR3
] = p
->id_isar3
;
342 miscRegs
[MISCREG_ID_ISAR4
] = p
->id_isar4
;
343 miscRegs
[MISCREG_ID_ISAR5
] = p
->id_isar5
;
345 miscRegs
[MISCREG_ID_MMFR0
] = p
->id_mmfr0
;
346 miscRegs
[MISCREG_ID_MMFR1
] = p
->id_mmfr1
;
347 miscRegs
[MISCREG_ID_MMFR2
] = p
->id_mmfr2
;
348 miscRegs
[MISCREG_ID_MMFR3
] = p
->id_mmfr3
;
350 miscRegs
[MISCREG_ID_ISAR5
] = insertBits(
351 miscRegs
[MISCREG_ID_ISAR5
], 19, 4,
352 haveCrypto
? 0x1112 : 0x0);
356 ISA::initID64(const ArmISAParams
*p
)
358 // Initialize configurable id registers
359 miscRegs
[MISCREG_ID_AA64AFR0_EL1
] = p
->id_aa64afr0_el1
;
360 miscRegs
[MISCREG_ID_AA64AFR1_EL1
] = p
->id_aa64afr1_el1
;
361 miscRegs
[MISCREG_ID_AA64DFR0_EL1
] =
362 (p
->id_aa64dfr0_el1
& 0xfffffffffffff0ffULL
) |
363 (p
->pmu
? 0x0000000000000100ULL
: 0); // Enable PMUv3
365 miscRegs
[MISCREG_ID_AA64DFR1_EL1
] = p
->id_aa64dfr1_el1
;
366 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = p
->id_aa64isar0_el1
;
367 miscRegs
[MISCREG_ID_AA64ISAR1_EL1
] = p
->id_aa64isar1_el1
;
368 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = p
->id_aa64mmfr0_el1
;
369 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = p
->id_aa64mmfr1_el1
;
370 miscRegs
[MISCREG_ID_AA64MMFR2_EL1
] = p
->id_aa64mmfr2_el1
;
372 miscRegs
[MISCREG_ID_DFR0_EL1
] =
373 (p
->pmu
? 0x03000000ULL
: 0); // Enable PMUv3
375 miscRegs
[MISCREG_ID_DFR0
] = miscRegs
[MISCREG_ID_DFR0_EL1
];
378 miscRegs
[MISCREG_ID_AA64ZFR0_EL1
] = 0; // SVEver 0
380 miscRegs
[MISCREG_ZCR_EL3
] = sveVL
- 1;
381 } else if (haveVirtualization
) {
382 miscRegs
[MISCREG_ZCR_EL2
] = sveVL
- 1;
384 miscRegs
[MISCREG_ZCR_EL1
] = sveVL
- 1;
387 // Enforce consistency with system-level settings...
390 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
391 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 15, 12,
392 haveSecurity
? 0x2 : 0x0);
394 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
395 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 11, 8,
396 haveVirtualization
? 0x2 : 0x0);
398 miscRegs
[MISCREG_ID_AA64PFR0_EL1
] = insertBits(
399 miscRegs
[MISCREG_ID_AA64PFR0_EL1
], 35, 32,
400 haveSVE
? 0x1 : 0x0);
401 // Large ASID support
402 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
403 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 7, 4,
404 haveLargeAsid64
? 0x2 : 0x0);
405 // Physical address size
406 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
] = insertBits(
407 miscRegs
[MISCREG_ID_AA64MMFR0_EL1
], 3, 0,
408 encodePhysAddrRange64(physAddrRange
));
410 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = insertBits(
411 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
], 19, 4,
412 haveCrypto
? 0x1112 : 0x0);
414 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
] = insertBits(
415 miscRegs
[MISCREG_ID_AA64ISAR0_EL1
], 23, 20,
416 haveLSE
? 0x2 : 0x0);
418 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
] = insertBits(
419 miscRegs
[MISCREG_ID_AA64MMFR1_EL1
], 23, 20,
420 havePAN
? 0x1 : 0x0);
424 ISA::startup(ThreadContext
*tc
)
426 pmu
->setThreadContext(tc
);
429 Gicv3
*gicv3
= dynamic_cast<Gicv3
*>(system
->getGIC());
431 haveGICv3CPUInterface
= true;
432 gicv3CpuInterface
.reset(gicv3
->getCPUInterface(tc
->contextId()));
433 gicv3CpuInterface
->setISA(this);
434 gicv3CpuInterface
->setThreadContext(tc
);
443 ISA::readMiscRegNoEffect(int misc_reg
) const
445 assert(misc_reg
< NumMiscRegs
);
447 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
448 const auto &map
= getMiscIndices(misc_reg
);
449 int lower
= map
.first
, upper
= map
.second
;
450 // NB!: apply architectural masks according to desired register,
451 // despite possibly getting value from different (mapped) register.
452 auto val
= !upper
? miscRegs
[lower
] : ((miscRegs
[lower
] & mask(32))
453 |(miscRegs
[upper
] << 32));
454 if (val
& reg
.res0()) {
455 DPRINTF(MiscRegs
, "Reading MiscReg %s with set res0 bits: %#x\n",
456 miscRegName
[misc_reg
], val
& reg
.res0());
458 if ((val
& reg
.res1()) != reg
.res1()) {
459 DPRINTF(MiscRegs
, "Reading MiscReg %s with clear res1 bits: %#x\n",
460 miscRegName
[misc_reg
], (val
& reg
.res1()) ^ reg
.res1());
462 return (val
& ~reg
.raz()) | reg
.rao(); // enforce raz/rao
467 ISA::readMiscReg(int misc_reg
, ThreadContext
*tc
)
473 if (misc_reg
== MISCREG_CPSR
) {
474 cpsr
= miscRegs
[misc_reg
];
476 cpsr
.j
= pc
.jazelle() ? 1 : 0;
477 cpsr
.t
= pc
.thumb() ? 1 : 0;
482 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
483 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
484 warn("Unimplemented system register %s read.\n",
485 miscRegName
[misc_reg
]);
487 panic("Unimplemented system register %s read.\n",
488 miscRegName
[misc_reg
]);
492 switch (unflattenMiscReg(misc_reg
)) {
495 if (!haveVirtualization
)
500 const uint32_t ones
= (uint32_t)(-1);
502 // Only cp10, cp11, and ase are implemented, nothing else should
503 // be readable? (straight copy from the write code)
504 cpacrMask
.cp10
= ones
;
505 cpacrMask
.cp11
= ones
;
506 cpacrMask
.asedis
= ones
;
508 // Security Extensions may limit the readability of CPACR
510 scr
= readMiscRegNoEffect(MISCREG_SCR
);
511 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
512 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
513 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
514 // NB: Skipping the full loop, here
515 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
516 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
519 RegVal val
= readMiscRegNoEffect(MISCREG_CPACR
);
521 DPRINTF(MiscRegs
, "Reading misc reg %s: %#x\n",
522 miscRegName
[misc_reg
], val
);
526 case MISCREG_MPIDR_EL1
:
527 return readMPIDR(system
, tc
);
529 case MISCREG_VMPIDR_EL2
:
530 // top bit defined as RES1
531 return readMiscRegNoEffect(misc_reg
) | 0x80000000;
532 case MISCREG_ID_AFR0
: // not implemented, so alias MIDR
533 case MISCREG_REVIDR
: // not implemented, so alias MIDR
535 cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
536 scr
= readMiscRegNoEffect(MISCREG_SCR
);
537 if ((cpsr
.mode
== MODE_HYP
) || inSecureState(scr
, cpsr
)) {
538 return readMiscRegNoEffect(misc_reg
);
540 return readMiscRegNoEffect(MISCREG_VPIDR
);
543 case MISCREG_JOSCR
: // Jazelle trivial implementation, RAZ/WI
544 case MISCREG_JMCR
: // Jazelle trivial implementation, RAZ/WI
545 case MISCREG_JIDR
: // Jazelle trivial implementation, RAZ/WI
546 case MISCREG_AIDR
: // AUX ID set to 0
547 case MISCREG_TCMTR
: // No TCM's
551 warn_once("The clidr register always reports 0 caches.\n");
552 warn_once("clidr LoUIS field of 0b001 to match current "
553 "ARM implementations.\n");
556 warn_once("The ccsidr register isn't implemented and "
557 "always reads as 0.\n");
559 case MISCREG_CTR
: // AArch32, ARMv7, top bit set
560 case MISCREG_CTR_EL0
: // AArch64
562 //all caches have the same line size in gem5
563 //4 byte words in ARM
564 unsigned lineSizeWords
=
565 tc
->getSystemPtr()->cacheLineSize() / 4;
566 unsigned log2LineSizeWords
= 0;
568 while (lineSizeWords
>>= 1) {
573 //log2 of minimun i-cache line size (words)
574 ctr
.iCacheLineSize
= log2LineSizeWords
;
575 //b11 - gem5 uses pipt
576 ctr
.l1IndexPolicy
= 0x3;
577 //log2 of minimum d-cache line size (words)
578 ctr
.dCacheLineSize
= log2LineSizeWords
;
579 //log2 of max reservation size (words)
580 ctr
.erg
= log2LineSizeWords
;
581 //log2 of max writeback size (words)
582 ctr
.cwg
= log2LineSizeWords
;
583 //b100 - gem5 format is ARMv7
589 warn("Not doing anything for miscreg ACTLR\n");
592 case MISCREG_PMXEVTYPER_PMCCFILTR
:
593 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
594 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
595 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
596 return pmu
->readMiscReg(misc_reg
);
599 panic("shouldn't be reading this register seperately\n");
600 case MISCREG_FPSCR_QC
:
601 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrQcMask
;
602 case MISCREG_FPSCR_EXC
:
603 return readMiscRegNoEffect(MISCREG_FPSCR
) & ~FpscrExcMask
;
606 const uint32_t ones
= (uint32_t)(-1);
608 fpscrMask
.ioc
= ones
;
609 fpscrMask
.dzc
= ones
;
610 fpscrMask
.ofc
= ones
;
611 fpscrMask
.ufc
= ones
;
612 fpscrMask
.ixc
= ones
;
613 fpscrMask
.idc
= ones
;
619 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
623 const uint32_t ones
= (uint32_t)(-1);
625 fpscrMask
.len
= ones
;
626 fpscrMask
.fz16
= ones
;
627 fpscrMask
.stride
= ones
;
628 fpscrMask
.rMode
= ones
;
631 fpscrMask
.ahp
= ones
;
632 return readMiscRegNoEffect(MISCREG_FPSCR
) & (uint32_t)fpscrMask
;
637 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
638 cpsr
.c
= tc
->readCCReg(CCREG_C
);
639 cpsr
.v
= tc
->readCCReg(CCREG_V
);
645 cpsr
.daif
= (uint8_t) ((CPSR
) miscRegs
[MISCREG_CPSR
]).daif
;
650 return tc
->readIntReg(INTREG_SP0
);
654 return tc
->readIntReg(INTREG_SP1
);
658 return tc
->readIntReg(INTREG_SP2
);
662 return miscRegs
[MISCREG_CPSR
] & 0x1;
664 case MISCREG_CURRENTEL
:
666 return miscRegs
[MISCREG_CPSR
] & 0xc;
670 return miscRegs
[MISCREG_CPSR
] & 0x400000;
674 // mostly unimplemented, just set NumCPUs field from sim and return
676 // b00:1CPU to b11:4CPUs
677 l2ctlr
.numCPUs
= tc
->getSystemPtr()->numContexts() - 1;
680 case MISCREG_DBGDIDR
:
681 /* For now just implement the version number.
682 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
685 case MISCREG_DBGDSCRint
:
689 auto ic
= dynamic_cast<ArmISA::Interrupts
*>(
690 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
692 readMiscRegNoEffect(MISCREG_HCR
),
693 readMiscRegNoEffect(MISCREG_CPSR
),
694 readMiscRegNoEffect(MISCREG_SCR
));
696 case MISCREG_ISR_EL1
:
698 auto ic
= dynamic_cast<ArmISA::Interrupts
*>(
699 tc
->getCpuPtr()->getInterruptController(tc
->threadId()));
701 readMiscRegNoEffect(MISCREG_HCR_EL2
),
702 readMiscRegNoEffect(MISCREG_CPSR
),
703 readMiscRegNoEffect(MISCREG_SCR_EL3
));
705 case MISCREG_DCZID_EL0
:
706 return 0x04; // DC ZVA clear 64-byte chunks
709 RegVal val
= readMiscRegNoEffect(misc_reg
);
710 // The trap bit associated with CP14 is defined as RAZ
712 // If a CP bit in NSACR is 0 then the corresponding bit in
714 bool secure_lookup
= haveSecurity
&&
715 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
716 readMiscRegNoEffect(MISCREG_CPSR
));
717 if (!secure_lookup
) {
718 RegVal mask
= readMiscRegNoEffect(MISCREG_NSACR
);
719 val
|= (mask
^ 0x7FFF) & 0xBFFF;
721 // Set the bits for unimplemented coprocessors to RAO/WI
725 case MISCREG_HDFAR
: // alias for secure DFAR
726 return readMiscRegNoEffect(MISCREG_DFAR_S
);
727 case MISCREG_HIFAR
: // alias for secure IFAR
728 return readMiscRegNoEffect(MISCREG_IFAR_S
);
730 case MISCREG_ID_PFR0
:
731 // !ThumbEE | !Jazelle | Thumb | ARM
733 case MISCREG_ID_PFR1
:
734 { // Timer | Virti | !M Profile | TrustZone | ARMv4
735 bool haveTimer
= (system
->getGenericTimer() != NULL
);
737 | (haveSecurity
? 0x00000010 : 0x0)
738 | (haveVirtualization
? 0x00001000 : 0x0)
739 | (haveTimer
? 0x00010000 : 0x0);
741 case MISCREG_ID_AA64PFR0_EL1
:
742 return 0x0000000000000002 | // AArch{64,32} supported at EL0
743 0x0000000000000020 | // EL1
744 (haveVirtualization
? 0x0000000000000200 : 0) | // EL2
745 (haveSecurity
? 0x0000000000002000 : 0) | // EL3
746 (haveSVE
? 0x0000000100000000 : 0) | // SVE
747 (haveGICv3CPUInterface
? 0x0000000001000000 : 0);
748 case MISCREG_ID_AA64PFR1_EL1
:
749 return 0; // bits [63:0] RES0 (reserved for future use)
751 // Generic Timer registers
752 case MISCREG_CNTFRQ
... MISCREG_CNTVOFF
:
753 case MISCREG_CNTFRQ_EL0
... MISCREG_CNTVOFF_EL2
:
754 return getGenericTimer(tc
).readMiscReg(misc_reg
);
756 case MISCREG_ICC_AP0R0
... MISCREG_ICH_LRC15
:
757 case MISCREG_ICC_PMR_EL1
... MISCREG_ICC_IGRPEN1_EL3
:
758 case MISCREG_ICH_AP0R0_EL2
... MISCREG_ICH_LR15_EL2
:
759 return getGICv3CPUInterface(tc
).readMiscReg(misc_reg
);
765 return readMiscRegNoEffect(misc_reg
);
769 ISA::setMiscRegNoEffect(int misc_reg
, RegVal val
)
771 assert(misc_reg
< NumMiscRegs
);
773 const auto ®
= lookUpMiscReg
[misc_reg
]; // bit masks
774 const auto &map
= getMiscIndices(misc_reg
);
775 int lower
= map
.first
, upper
= map
.second
;
777 auto v
= (val
& ~reg
.wi()) | reg
.rao();
779 miscRegs
[lower
] = bits(v
, 31, 0);
780 miscRegs
[upper
] = bits(v
, 63, 32);
781 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d:%d) : %#x\n",
782 misc_reg
, lower
, upper
, v
);
785 DPRINTF(MiscRegs
, "Writing to misc reg %d (%d) : %#x\n",
791 ISA::setMiscReg(int misc_reg
, RegVal val
, ThreadContext
*tc
)
798 if (misc_reg
== MISCREG_CPSR
) {
802 CPSR old_cpsr
= miscRegs
[MISCREG_CPSR
];
803 int old_mode
= old_cpsr
.mode
;
805 if (old_mode
!= cpsr
.mode
|| cpsr
.il
!= old_cpsr
.il
) {
806 getITBPtr(tc
)->invalidateMiscReg();
807 getDTBPtr(tc
)->invalidateMiscReg();
810 if (cpsr
.pan
!= old_cpsr
.pan
) {
811 getDTBPtr(tc
)->invalidateMiscReg();
814 DPRINTF(Arm
, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
815 miscRegs
[misc_reg
], cpsr
, cpsr
.f
, cpsr
.i
, cpsr
.a
, cpsr
.mode
);
816 PCState pc
= tc
->pcState();
817 pc
.nextThumb(cpsr
.t
);
818 pc
.nextJazelle(cpsr
.j
);
819 pc
.illegalExec(cpsr
.il
== 1);
821 tc
->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc
) >> 7) - 1);
823 // Follow slightly different semantics if a CheckerCPU object
825 CheckerCPU
*checker
= tc
->getCheckerCpuPtr();
827 tc
->pcStateNoRecord(pc
);
833 if (!miscRegInfo
[misc_reg
][MISCREG_IMPLEMENTED
]) {
834 if (miscRegInfo
[misc_reg
][MISCREG_WARN_NOT_FAIL
])
835 warn("Unimplemented system register %s write with %#x.\n",
836 miscRegName
[misc_reg
], val
);
838 panic("Unimplemented system register %s write with %#x.\n",
839 miscRegName
[misc_reg
], val
);
842 switch (unflattenMiscReg(misc_reg
)) {
846 const uint32_t ones
= (uint32_t)(-1);
848 // Only cp10, cp11, and ase are implemented, nothing else should
850 cpacrMask
.cp10
= ones
;
851 cpacrMask
.cp11
= ones
;
852 cpacrMask
.asedis
= ones
;
854 // Security Extensions may limit the writability of CPACR
856 scr
= readMiscRegNoEffect(MISCREG_SCR
);
857 CPSR cpsr
= readMiscRegNoEffect(MISCREG_CPSR
);
858 if (scr
.ns
&& (cpsr
.mode
!= MODE_MON
) && ELIs32(tc
, EL3
)) {
859 NSACR nsacr
= readMiscRegNoEffect(MISCREG_NSACR
);
860 // NB: Skipping the full loop, here
861 if (!nsacr
.cp10
) cpacrMask
.cp10
= 0;
862 if (!nsacr
.cp11
) cpacrMask
.cp11
= 0;
866 RegVal old_val
= readMiscRegNoEffect(MISCREG_CPACR
);
868 newVal
|= old_val
& ~cpacrMask
;
869 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
870 miscRegName
[misc_reg
], newVal
);
873 case MISCREG_CPACR_EL1
:
875 const uint32_t ones
= (uint32_t)(-1);
877 cpacrMask
.tta
= ones
;
878 cpacrMask
.fpen
= ones
;
880 cpacrMask
.zen
= ones
;
883 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
884 miscRegName
[misc_reg
], newVal
);
887 case MISCREG_CPTR_EL2
:
889 const uint32_t ones
= (uint32_t)(-1);
891 cptrMask
.tcpac
= ones
;
899 cptrMask
.res1_13_12_el2
= ones
;
900 cptrMask
.res1_7_0_el2
= ones
;
902 cptrMask
.res1_8_el2
= ones
;
904 cptrMask
.res1_9_el2
= ones
;
906 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
907 miscRegName
[misc_reg
], newVal
);
910 case MISCREG_CPTR_EL3
:
912 const uint32_t ones
= (uint32_t)(-1);
914 cptrMask
.tcpac
= ones
;
921 DPRINTF(MiscRegs
, "Writing misc reg %s: %#x\n",
922 miscRegName
[misc_reg
], newVal
);
926 warn_once("The csselr register isn't implemented.\n");
929 case MISCREG_DC_ZVA_Xt
:
930 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
935 const uint32_t ones
= (uint32_t)(-1);
937 fpscrMask
.ioc
= ones
;
938 fpscrMask
.dzc
= ones
;
939 fpscrMask
.ofc
= ones
;
940 fpscrMask
.ufc
= ones
;
941 fpscrMask
.ixc
= ones
;
942 fpscrMask
.idc
= ones
;
943 fpscrMask
.ioe
= ones
;
944 fpscrMask
.dze
= ones
;
945 fpscrMask
.ofe
= ones
;
946 fpscrMask
.ufe
= ones
;
947 fpscrMask
.ixe
= ones
;
948 fpscrMask
.ide
= ones
;
949 fpscrMask
.len
= ones
;
950 fpscrMask
.fz16
= ones
;
951 fpscrMask
.stride
= ones
;
952 fpscrMask
.rMode
= ones
;
955 fpscrMask
.ahp
= ones
;
961 newVal
= (newVal
& (uint32_t)fpscrMask
) |
962 (readMiscRegNoEffect(MISCREG_FPSCR
) &
963 ~(uint32_t)fpscrMask
);
964 tc
->getDecoderPtr()->setContext(newVal
);
969 const uint32_t ones
= (uint32_t)(-1);
971 fpscrMask
.ioc
= ones
;
972 fpscrMask
.dzc
= ones
;
973 fpscrMask
.ofc
= ones
;
974 fpscrMask
.ufc
= ones
;
975 fpscrMask
.ixc
= ones
;
976 fpscrMask
.idc
= ones
;
982 newVal
= (newVal
& (uint32_t)fpscrMask
) |
983 (readMiscRegNoEffect(MISCREG_FPSCR
) &
984 ~(uint32_t)fpscrMask
);
985 misc_reg
= MISCREG_FPSCR
;
990 const uint32_t ones
= (uint32_t)(-1);
992 fpscrMask
.len
= ones
;
993 fpscrMask
.fz16
= ones
;
994 fpscrMask
.stride
= ones
;
995 fpscrMask
.rMode
= ones
;
998 fpscrMask
.ahp
= ones
;
999 newVal
= (newVal
& (uint32_t)fpscrMask
) |
1000 (readMiscRegNoEffect(MISCREG_FPSCR
) &
1001 ~(uint32_t)fpscrMask
);
1002 misc_reg
= MISCREG_FPSCR
;
1005 case MISCREG_CPSR_Q
:
1007 assert(!(newVal
& ~CpsrMaskQ
));
1008 newVal
= readMiscRegNoEffect(MISCREG_CPSR
) | newVal
;
1009 misc_reg
= MISCREG_CPSR
;
1012 case MISCREG_FPSCR_QC
:
1014 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1015 (newVal
& FpscrQcMask
);
1016 misc_reg
= MISCREG_FPSCR
;
1019 case MISCREG_FPSCR_EXC
:
1021 newVal
= readMiscRegNoEffect(MISCREG_FPSCR
) |
1022 (newVal
& FpscrExcMask
);
1023 misc_reg
= MISCREG_FPSCR
;
1028 // vfpv3 architecture, section B.6.1 of DDI04068
1029 // bit 29 - valid only if fpexc[31] is 0
1030 const uint32_t fpexcMask
= 0x60000000;
1031 newVal
= (newVal
& fpexcMask
) |
1032 (readMiscRegNoEffect(MISCREG_FPEXC
) & ~fpexcMask
);
1037 if (!haveVirtualization
)
1042 // ARM ARM (ARM DDI 0406C.b) B4.1.96
1043 const uint32_t ifsrMask
=
1044 mask(31, 13) | mask(11, 11) | mask(8, 6);
1045 newVal
= newVal
& ~ifsrMask
;
1050 // ARM ARM (ARM DDI 0406C.b) B4.1.52
1051 const uint32_t dfsrMask
= mask(31, 14) | mask(8, 8);
1052 newVal
= newVal
& ~dfsrMask
;
1055 case MISCREG_AMAIR0
:
1056 case MISCREG_AMAIR1
:
1058 // ARM ARM (ARM DDI 0406C.b) B4.1.5
1059 // Valid only with LPAE
1062 DPRINTF(MiscRegs
, "Writing AMAIR: %#x\n", newVal
);
1066 getITBPtr(tc
)->invalidateMiscReg();
1067 getDTBPtr(tc
)->invalidateMiscReg();
1071 DPRINTF(MiscRegs
, "Writing SCTLR: %#x\n", newVal
);
1072 scr
= readMiscRegNoEffect(MISCREG_SCR
);
1074 MiscRegIndex sctlr_idx
;
1075 if (haveSecurity
&& !highestELIs64
&& !scr
.ns
) {
1076 sctlr_idx
= MISCREG_SCTLR_S
;
1078 sctlr_idx
= MISCREG_SCTLR_NS
;
1081 SCTLR sctlr
= miscRegs
[sctlr_idx
];
1082 SCTLR new_sctlr
= newVal
;
1083 new_sctlr
.nmfi
= ((bool)sctlr
.nmfi
) && !haveVirtualization
;
1084 miscRegs
[sctlr_idx
] = (RegVal
)new_sctlr
;
1085 getITBPtr(tc
)->invalidateMiscReg();
1086 getDTBPtr(tc
)->invalidateMiscReg();
1089 case MISCREG_ID_PFR0
:
1090 case MISCREG_ID_PFR1
:
1091 case MISCREG_ID_DFR0
:
1092 case MISCREG_ID_MMFR0
:
1093 case MISCREG_ID_MMFR1
:
1094 case MISCREG_ID_MMFR2
:
1095 case MISCREG_ID_MMFR3
:
1096 case MISCREG_ID_ISAR0
:
1097 case MISCREG_ID_ISAR1
:
1098 case MISCREG_ID_ISAR2
:
1099 case MISCREG_ID_ISAR3
:
1100 case MISCREG_ID_ISAR4
:
1101 case MISCREG_ID_ISAR5
:
1109 case MISCREG_ID_AA64AFR0_EL1
:
1110 case MISCREG_ID_AA64AFR1_EL1
:
1111 case MISCREG_ID_AA64DFR0_EL1
:
1112 case MISCREG_ID_AA64DFR1_EL1
:
1113 case MISCREG_ID_AA64ISAR0_EL1
:
1114 case MISCREG_ID_AA64ISAR1_EL1
:
1115 case MISCREG_ID_AA64MMFR0_EL1
:
1116 case MISCREG_ID_AA64MMFR1_EL1
:
1117 case MISCREG_ID_AA64MMFR2_EL1
:
1118 case MISCREG_ID_AA64PFR0_EL1
:
1119 case MISCREG_ID_AA64PFR1_EL1
:
1120 // ID registers are constants.
1123 // TLB Invalidate All
1124 case MISCREG_TLBIALL
: // TLBI all entries, EL0&1,
1127 scr
= readMiscReg(MISCREG_SCR
, tc
);
1129 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1133 // TLB Invalidate All, Inner Shareable
1134 case MISCREG_TLBIALLIS
:
1137 scr
= readMiscReg(MISCREG_SCR
, tc
);
1139 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1140 tlbiOp
.broadcast(tc
);
1143 // Instruction TLB Invalidate All
1144 case MISCREG_ITLBIALL
:
1147 scr
= readMiscReg(MISCREG_SCR
, tc
);
1149 ITLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1153 // Data TLB Invalidate All
1154 case MISCREG_DTLBIALL
:
1157 scr
= readMiscReg(MISCREG_SCR
, tc
);
1159 DTLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1163 // TLB Invalidate by VA
1164 // mcr tlbimval(is) is invalidating all matching entries
1165 // regardless of the level of lookup, since in gem5 we cache
1166 // in the tlb the last level of lookup only.
1167 case MISCREG_TLBIMVA
:
1168 case MISCREG_TLBIMVAL
:
1171 scr
= readMiscReg(MISCREG_SCR
, tc
);
1174 haveSecurity
&& !scr
.ns
,
1175 mbits(newVal
, 31, 12),
1181 // TLB Invalidate by VA, Inner Shareable
1182 case MISCREG_TLBIMVAIS
:
1183 case MISCREG_TLBIMVALIS
:
1186 scr
= readMiscReg(MISCREG_SCR
, tc
);
1189 haveSecurity
&& !scr
.ns
,
1190 mbits(newVal
, 31, 12),
1193 tlbiOp
.broadcast(tc
);
1196 // TLB Invalidate by ASID match
1197 case MISCREG_TLBIASID
:
1200 scr
= readMiscReg(MISCREG_SCR
, tc
);
1202 TLBIASID
tlbiOp(EL1
,
1203 haveSecurity
&& !scr
.ns
,
1209 // TLB Invalidate by ASID match, Inner Shareable
1210 case MISCREG_TLBIASIDIS
:
1213 scr
= readMiscReg(MISCREG_SCR
, tc
);
1215 TLBIASID
tlbiOp(EL1
,
1216 haveSecurity
&& !scr
.ns
,
1219 tlbiOp
.broadcast(tc
);
1222 // mcr tlbimvaal(is) is invalidating all matching entries
1223 // regardless of the level of lookup, since in gem5 we cache
1224 // in the tlb the last level of lookup only.
1225 // TLB Invalidate by VA, All ASID
1226 case MISCREG_TLBIMVAA
:
1227 case MISCREG_TLBIMVAAL
:
1230 scr
= readMiscReg(MISCREG_SCR
, tc
);
1232 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1233 mbits(newVal
, 31,12));
1238 // TLB Invalidate by VA, All ASID, Inner Shareable
1239 case MISCREG_TLBIMVAAIS
:
1240 case MISCREG_TLBIMVAALIS
:
1243 scr
= readMiscReg(MISCREG_SCR
, tc
);
1245 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1246 mbits(newVal
, 31,12));
1248 tlbiOp
.broadcast(tc
);
1251 // mcr tlbimvalh(is) is invalidating all matching entries
1252 // regardless of the level of lookup, since in gem5 we cache
1253 // in the tlb the last level of lookup only.
1254 // TLB Invalidate by VA, Hyp mode
1255 case MISCREG_TLBIMVAH
:
1256 case MISCREG_TLBIMVALH
:
1259 scr
= readMiscReg(MISCREG_SCR
, tc
);
1261 TLBIMVAA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1262 mbits(newVal
, 31,12));
1267 // TLB Invalidate by VA, Hyp mode, Inner Shareable
1268 case MISCREG_TLBIMVAHIS
:
1269 case MISCREG_TLBIMVALHIS
:
1272 scr
= readMiscReg(MISCREG_SCR
, tc
);
1274 TLBIMVAA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1275 mbits(newVal
, 31,12));
1277 tlbiOp
.broadcast(tc
);
1280 // mcr tlbiipas2l(is) is invalidating all matching entries
1281 // regardless of the level of lookup, since in gem5 we cache
1282 // in the tlb the last level of lookup only.
1283 // TLB Invalidate by Intermediate Physical Address, Stage 2
1284 case MISCREG_TLBIIPAS2
:
1285 case MISCREG_TLBIIPAS2L
:
1288 scr
= readMiscReg(MISCREG_SCR
, tc
);
1291 haveSecurity
&& !scr
.ns
,
1292 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1297 // TLB Invalidate by Intermediate Physical Address, Stage 2,
1299 case MISCREG_TLBIIPAS2IS
:
1300 case MISCREG_TLBIIPAS2LIS
:
1303 scr
= readMiscReg(MISCREG_SCR
, tc
);
1306 haveSecurity
&& !scr
.ns
,
1307 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1309 tlbiOp
.broadcast(tc
);
1312 // Instruction TLB Invalidate by VA
1313 case MISCREG_ITLBIMVA
:
1316 scr
= readMiscReg(MISCREG_SCR
, tc
);
1318 ITLBIMVA
tlbiOp(EL1
,
1319 haveSecurity
&& !scr
.ns
,
1320 mbits(newVal
, 31, 12),
1326 // Data TLB Invalidate by VA
1327 case MISCREG_DTLBIMVA
:
1330 scr
= readMiscReg(MISCREG_SCR
, tc
);
1332 DTLBIMVA
tlbiOp(EL1
,
1333 haveSecurity
&& !scr
.ns
,
1334 mbits(newVal
, 31, 12),
1340 // Instruction TLB Invalidate by ASID match
1341 case MISCREG_ITLBIASID
:
1344 scr
= readMiscReg(MISCREG_SCR
, tc
);
1346 ITLBIASID
tlbiOp(EL1
,
1347 haveSecurity
&& !scr
.ns
,
1353 // Data TLB Invalidate by ASID match
1354 case MISCREG_DTLBIASID
:
1357 scr
= readMiscReg(MISCREG_SCR
, tc
);
1359 DTLBIASID
tlbiOp(EL1
,
1360 haveSecurity
&& !scr
.ns
,
1366 // TLB Invalidate All, Non-Secure Non-Hyp
1367 case MISCREG_TLBIALLNSNH
:
1371 TLBIALLN
tlbiOp(EL1
);
1375 // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
1376 case MISCREG_TLBIALLNSNHIS
:
1380 TLBIALLN
tlbiOp(EL1
);
1381 tlbiOp
.broadcast(tc
);
1384 // TLB Invalidate All, Hyp mode
1385 case MISCREG_TLBIALLH
:
1389 TLBIALLN
tlbiOp(EL2
);
1393 // TLB Invalidate All, Hyp mode, Inner Shareable
1394 case MISCREG_TLBIALLHIS
:
1398 TLBIALLN
tlbiOp(EL2
);
1399 tlbiOp
.broadcast(tc
);
1402 // AArch64 TLB Invalidate All, EL3
1403 case MISCREG_TLBI_ALLE3
:
1407 TLBIALL
tlbiOp(EL3
, true);
1411 // AArch64 TLB Invalidate All, EL3, Inner Shareable
1412 case MISCREG_TLBI_ALLE3IS
:
1416 TLBIALL
tlbiOp(EL3
, true);
1417 tlbiOp
.broadcast(tc
);
1420 // AArch64 TLB Invalidate All, EL2, Inner Shareable
1421 case MISCREG_TLBI_ALLE2
:
1422 case MISCREG_TLBI_ALLE2IS
:
1425 scr
= readMiscReg(MISCREG_SCR
, tc
);
1427 TLBIALL
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
);
1431 // AArch64 TLB Invalidate All, EL1
1432 case MISCREG_TLBI_ALLE1
:
1433 case MISCREG_TLBI_VMALLE1
:
1434 case MISCREG_TLBI_VMALLS12E1
:
1435 // @todo: handle VMID and stage 2 to enable Virtualization
1438 scr
= readMiscReg(MISCREG_SCR
, tc
);
1440 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1444 // AArch64 TLB Invalidate All, EL1, Inner Shareable
1445 case MISCREG_TLBI_ALLE1IS
:
1446 case MISCREG_TLBI_VMALLE1IS
:
1447 case MISCREG_TLBI_VMALLS12E1IS
:
1448 // @todo: handle VMID and stage 2 to enable Virtualization
1451 scr
= readMiscReg(MISCREG_SCR
, tc
);
1453 TLBIALL
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
);
1454 tlbiOp
.broadcast(tc
);
1457 // VAEx(IS) and VALEx(IS) are the same because TLBs
1458 // only store entries
1459 // from the last level of translation table walks
1460 // @todo: handle VMID to enable Virtualization
1461 // AArch64 TLB Invalidate by VA, EL3
1462 case MISCREG_TLBI_VAE3_Xt
:
1463 case MISCREG_TLBI_VALE3_Xt
:
1467 TLBIMVA
tlbiOp(EL3
, true,
1468 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1473 // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
1474 case MISCREG_TLBI_VAE3IS_Xt
:
1475 case MISCREG_TLBI_VALE3IS_Xt
:
1479 TLBIMVA
tlbiOp(EL3
, true,
1480 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1483 tlbiOp
.broadcast(tc
);
1486 // AArch64 TLB Invalidate by VA, EL2
1487 case MISCREG_TLBI_VAE2_Xt
:
1488 case MISCREG_TLBI_VALE2_Xt
:
1491 scr
= readMiscReg(MISCREG_SCR
, tc
);
1493 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1494 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1499 // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
1500 case MISCREG_TLBI_VAE2IS_Xt
:
1501 case MISCREG_TLBI_VALE2IS_Xt
:
1504 scr
= readMiscReg(MISCREG_SCR
, tc
);
1506 TLBIMVA
tlbiOp(EL2
, haveSecurity
&& !scr
.ns
,
1507 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1510 tlbiOp
.broadcast(tc
);
1513 // AArch64 TLB Invalidate by VA, EL1
1514 case MISCREG_TLBI_VAE1_Xt
:
1515 case MISCREG_TLBI_VALE1_Xt
:
1518 scr
= readMiscReg(MISCREG_SCR
, tc
);
1519 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1520 bits(newVal
, 55, 48);
1522 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1523 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1529 // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
1530 case MISCREG_TLBI_VAE1IS_Xt
:
1531 case MISCREG_TLBI_VALE1IS_Xt
:
1534 scr
= readMiscReg(MISCREG_SCR
, tc
);
1535 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1536 bits(newVal
, 55, 48);
1538 TLBIMVA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1539 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12,
1542 tlbiOp
.broadcast(tc
);
1545 // AArch64 TLB Invalidate by ASID, EL1
1546 // @todo: handle VMID to enable Virtualization
1547 case MISCREG_TLBI_ASIDE1_Xt
:
1550 scr
= readMiscReg(MISCREG_SCR
, tc
);
1551 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1552 bits(newVal
, 55, 48);
1554 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1558 // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
1559 case MISCREG_TLBI_ASIDE1IS_Xt
:
1562 scr
= readMiscReg(MISCREG_SCR
, tc
);
1563 auto asid
= haveLargeAsid64
? bits(newVal
, 63, 48) :
1564 bits(newVal
, 55, 48);
1566 TLBIASID
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
, asid
);
1567 tlbiOp
.broadcast(tc
);
1570 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
1571 // entries from the last level of translation table walks
1572 // AArch64 TLB Invalidate by VA, All ASID, EL1
1573 case MISCREG_TLBI_VAAE1_Xt
:
1574 case MISCREG_TLBI_VAALE1_Xt
:
1577 scr
= readMiscReg(MISCREG_SCR
, tc
);
1579 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1580 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12);
1585 // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
1586 case MISCREG_TLBI_VAAE1IS_Xt
:
1587 case MISCREG_TLBI_VAALE1IS_Xt
:
1590 scr
= readMiscReg(MISCREG_SCR
, tc
);
1592 TLBIMVAA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1593 static_cast<Addr
>(bits(newVal
, 43, 0)) << 12);
1595 tlbiOp
.broadcast(tc
);
1598 // AArch64 TLB Invalidate by Intermediate Physical Address,
1600 case MISCREG_TLBI_IPAS2E1_Xt
:
1601 case MISCREG_TLBI_IPAS2LE1_Xt
:
1604 scr
= readMiscReg(MISCREG_SCR
, tc
);
1606 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1607 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1612 // AArch64 TLB Invalidate by Intermediate Physical Address,
1613 // Stage 2, EL1, Inner Shareable
1614 case MISCREG_TLBI_IPAS2E1IS_Xt
:
1615 case MISCREG_TLBI_IPAS2LE1IS_Xt
:
1618 scr
= readMiscReg(MISCREG_SCR
, tc
);
1620 TLBIIPA
tlbiOp(EL1
, haveSecurity
&& !scr
.ns
,
1621 static_cast<Addr
>(bits(newVal
, 35, 0)) << 12);
1623 tlbiOp
.broadcast(tc
);
1627 warn("Not doing anything for write of miscreg ACTLR\n");
1630 case MISCREG_PMXEVTYPER_PMCCFILTR
:
1631 case MISCREG_PMINTENSET_EL1
... MISCREG_PMOVSSET_EL0
:
1632 case MISCREG_PMEVCNTR0_EL0
... MISCREG_PMEVTYPER5_EL0
:
1633 case MISCREG_PMCR
... MISCREG_PMOVSSET
:
1634 pmu
->setMiscReg(misc_reg
, newVal
);
1638 case MISCREG_HSTR
: // TJDBX, now redifined to be RES0
1642 newVal
&= ~((uint32_t) hstrMask
);
1647 // If a CP bit in NSACR is 0 then the corresponding bit in
1648 // HCPTR is RAO/WI. Same applies to NSASEDIS
1649 secure_lookup
= haveSecurity
&&
1650 inSecureState(readMiscRegNoEffect(MISCREG_SCR
),
1651 readMiscRegNoEffect(MISCREG_CPSR
));
1652 if (!secure_lookup
) {
1653 RegVal oldValue
= readMiscRegNoEffect(MISCREG_HCPTR
);
1655 (readMiscRegNoEffect(MISCREG_NSACR
) ^ 0x7FFF) & 0xBFFF;
1656 newVal
= (newVal
& ~mask
) | (oldValue
& mask
);
1660 case MISCREG_HDFAR
: // alias for secure DFAR
1661 misc_reg
= MISCREG_DFAR_S
;
1663 case MISCREG_HIFAR
: // alias for secure IFAR
1664 misc_reg
= MISCREG_IFAR_S
;
1666 case MISCREG_ATS1CPR
:
1667 case MISCREG_ATS1CPW
:
1668 case MISCREG_ATS1CUR
:
1669 case MISCREG_ATS1CUW
:
1670 case MISCREG_ATS12NSOPR
:
1671 case MISCREG_ATS12NSOPW
:
1672 case MISCREG_ATS12NSOUR
:
1673 case MISCREG_ATS12NSOUW
:
1674 case MISCREG_ATS1HR
:
1675 case MISCREG_ATS1HW
:
1677 Request::Flags flags
= 0;
1678 BaseTLB::Mode mode
= BaseTLB::Read
;
1679 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1682 case MISCREG_ATS1CPR
:
1683 flags
= TLB::MustBeOne
;
1684 tranType
= TLB::S1CTran
;
1685 mode
= BaseTLB::Read
;
1687 case MISCREG_ATS1CPW
:
1688 flags
= TLB::MustBeOne
;
1689 tranType
= TLB::S1CTran
;
1690 mode
= BaseTLB::Write
;
1692 case MISCREG_ATS1CUR
:
1693 flags
= TLB::MustBeOne
| TLB::UserMode
;
1694 tranType
= TLB::S1CTran
;
1695 mode
= BaseTLB::Read
;
1697 case MISCREG_ATS1CUW
:
1698 flags
= TLB::MustBeOne
| TLB::UserMode
;
1699 tranType
= TLB::S1CTran
;
1700 mode
= BaseTLB::Write
;
1702 case MISCREG_ATS12NSOPR
:
1704 panic("Security Extensions required for ATS12NSOPR");
1705 flags
= TLB::MustBeOne
;
1706 tranType
= TLB::S1S2NsTran
;
1707 mode
= BaseTLB::Read
;
1709 case MISCREG_ATS12NSOPW
:
1711 panic("Security Extensions required for ATS12NSOPW");
1712 flags
= TLB::MustBeOne
;
1713 tranType
= TLB::S1S2NsTran
;
1714 mode
= BaseTLB::Write
;
1716 case MISCREG_ATS12NSOUR
:
1718 panic("Security Extensions required for ATS12NSOUR");
1719 flags
= TLB::MustBeOne
| TLB::UserMode
;
1720 tranType
= TLB::S1S2NsTran
;
1721 mode
= BaseTLB::Read
;
1723 case MISCREG_ATS12NSOUW
:
1725 panic("Security Extensions required for ATS12NSOUW");
1726 flags
= TLB::MustBeOne
| TLB::UserMode
;
1727 tranType
= TLB::S1S2NsTran
;
1728 mode
= BaseTLB::Write
;
1730 case MISCREG_ATS1HR
: // only really useful from secure mode.
1731 flags
= TLB::MustBeOne
;
1732 tranType
= TLB::HypMode
;
1733 mode
= BaseTLB::Read
;
1735 case MISCREG_ATS1HW
:
1736 flags
= TLB::MustBeOne
;
1737 tranType
= TLB::HypMode
;
1738 mode
= BaseTLB::Write
;
1741 // If we're in timing mode then doing the translation in
1742 // functional mode then we're slightly distorting performance
1743 // results obtained from simulations. The translation should be
1744 // done in the same mode the core is running in. NOTE: This
1745 // can't be an atomic translation because that causes problems
1746 // with unexpected atomic snoop requests.
1747 warn("Translating via %s in functional mode! Fix Me!\n",
1748 miscRegName
[misc_reg
]);
1750 auto req
= std::make_shared
<Request
>(
1751 val
, 0, flags
, Request::funcMasterId
,
1752 tc
->pcState().pc(), tc
->contextId());
1754 fault
= getDTBPtr(tc
)->translateFunctional(
1755 req
, tc
, mode
, tranType
);
1757 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1758 HCR hcr
= readMiscRegNoEffect(MISCREG_HCR
);
1761 if (fault
== NoFault
) {
1762 Addr paddr
= req
->getPaddr();
1763 if (haveLPAE
&& (ttbcr
.eae
|| tranType
& TLB::HypMode
||
1764 ((tranType
& TLB::S1S2NsTran
) && hcr
.vm
) )) {
1765 newVal
= (paddr
& mask(39, 12)) |
1766 (getDTBPtr(tc
)->getAttr());
1768 newVal
= (paddr
& 0xfffff000) |
1769 (getDTBPtr(tc
)->getAttr());
1772 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
1775 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
1776 armFault
->update(tc
);
1777 // Set fault bit and FSR
1778 FSR fsr
= armFault
->getFsr(tc
);
1780 newVal
= ((fsr
>> 9) & 1) << 11;
1782 // LPAE - rearange fault status
1783 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
1785 // VMSA - rearange fault status
1786 newVal
|= ((fsr
>> 0) & 0xf) << 1;
1787 newVal
|= ((fsr
>> 10) & 0x1) << 5;
1788 newVal
|= ((fsr
>> 12) & 0x1) << 6;
1790 newVal
|= 0x1; // F bit
1791 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
1792 newVal
|= armFault
->isStage2() ? 0x200 : 0;
1794 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
1797 setMiscRegNoEffect(MISCREG_PAR
, newVal
);
1802 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1803 const uint32_t ones
= (uint32_t)(-1);
1804 TTBCR ttbcrMask
= 0;
1805 TTBCR ttbcrNew
= newVal
;
1807 // ARM DDI 0406C.b, ARMv7-32
1808 ttbcrMask
.n
= ones
; // T0SZ
1810 ttbcrMask
.pd0
= ones
;
1811 ttbcrMask
.pd1
= ones
;
1813 ttbcrMask
.epd0
= ones
;
1814 ttbcrMask
.irgn0
= ones
;
1815 ttbcrMask
.orgn0
= ones
;
1816 ttbcrMask
.sh0
= ones
;
1817 ttbcrMask
.ps
= ones
; // T1SZ
1818 ttbcrMask
.a1
= ones
;
1819 ttbcrMask
.epd1
= ones
;
1820 ttbcrMask
.irgn1
= ones
;
1821 ttbcrMask
.orgn1
= ones
;
1822 ttbcrMask
.sh1
= ones
;
1824 ttbcrMask
.eae
= ones
;
1826 if (haveLPAE
&& ttbcrNew
.eae
) {
1827 newVal
= newVal
& ttbcrMask
;
1829 newVal
= (newVal
& ttbcrMask
) | (ttbcr
& (~ttbcrMask
));
1831 // Invalidate TLB MiscReg
1832 getITBPtr(tc
)->invalidateMiscReg();
1833 getDTBPtr(tc
)->invalidateMiscReg();
1839 TTBCR ttbcr
= readMiscRegNoEffect(MISCREG_TTBCR
);
1842 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
1843 // ARMv8 AArch32 bit 63-56 only
1844 uint64_t ttbrMask
= mask(63,56) | mask(47,40);
1845 newVal
= (newVal
& (~ttbrMask
));
1848 // Invalidate TLB MiscReg
1849 getITBPtr(tc
)->invalidateMiscReg();
1850 getDTBPtr(tc
)->invalidateMiscReg();
1853 case MISCREG_SCTLR_EL1
:
1854 case MISCREG_CONTEXTIDR
:
1861 case MISCREG_SCR_EL3
:
1862 case MISCREG_HCR_EL2
:
1863 case MISCREG_TCR_EL1
:
1864 case MISCREG_TCR_EL2
:
1865 case MISCREG_TCR_EL3
:
1866 case MISCREG_SCTLR_EL2
:
1867 case MISCREG_SCTLR_EL3
:
1868 case MISCREG_HSCTLR
:
1869 case MISCREG_TTBR0_EL1
:
1870 case MISCREG_TTBR1_EL1
:
1871 case MISCREG_TTBR0_EL2
:
1872 case MISCREG_TTBR1_EL2
:
1873 case MISCREG_TTBR0_EL3
:
1874 getITBPtr(tc
)->invalidateMiscReg();
1875 getDTBPtr(tc
)->invalidateMiscReg();
1881 tc
->setCCReg(CCREG_NZ
, cpsr
.nz
);
1882 tc
->setCCReg(CCREG_C
, cpsr
.c
);
1883 tc
->setCCReg(CCREG_V
, cpsr
.v
);
1888 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1889 cpsr
.daif
= (uint8_t) ((CPSR
) newVal
).daif
;
1891 misc_reg
= MISCREG_CPSR
;
1894 case MISCREG_SP_EL0
:
1895 tc
->setIntReg(INTREG_SP0
, newVal
);
1897 case MISCREG_SP_EL1
:
1898 tc
->setIntReg(INTREG_SP1
, newVal
);
1900 case MISCREG_SP_EL2
:
1901 tc
->setIntReg(INTREG_SP2
, newVal
);
1905 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1906 cpsr
.sp
= (uint8_t) ((CPSR
) newVal
).sp
;
1908 misc_reg
= MISCREG_CPSR
;
1911 case MISCREG_CURRENTEL
:
1913 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1914 cpsr
.el
= (uint8_t) ((CPSR
) newVal
).el
;
1916 misc_reg
= MISCREG_CPSR
;
1921 // PAN is affecting data accesses
1922 getDTBPtr(tc
)->invalidateMiscReg();
1924 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
1925 cpsr
.pan
= (uint8_t) ((CPSR
) newVal
).pan
;
1927 misc_reg
= MISCREG_CPSR
;
1930 case MISCREG_AT_S1E1R_Xt
:
1931 case MISCREG_AT_S1E1W_Xt
:
1932 case MISCREG_AT_S1E0R_Xt
:
1933 case MISCREG_AT_S1E0W_Xt
:
1934 case MISCREG_AT_S1E2R_Xt
:
1935 case MISCREG_AT_S1E2W_Xt
:
1936 case MISCREG_AT_S12E1R_Xt
:
1937 case MISCREG_AT_S12E1W_Xt
:
1938 case MISCREG_AT_S12E0R_Xt
:
1939 case MISCREG_AT_S12E0W_Xt
:
1940 case MISCREG_AT_S1E3R_Xt
:
1941 case MISCREG_AT_S1E3W_Xt
:
1943 RequestPtr req
= std::make_shared
<Request
>();
1944 Request::Flags flags
= 0;
1945 BaseTLB::Mode mode
= BaseTLB::Read
;
1946 TLB::ArmTranslationType tranType
= TLB::NormalTran
;
1949 case MISCREG_AT_S1E1R_Xt
:
1950 flags
= TLB::MustBeOne
;
1951 tranType
= TLB::S1E1Tran
;
1952 mode
= BaseTLB::Read
;
1954 case MISCREG_AT_S1E1W_Xt
:
1955 flags
= TLB::MustBeOne
;
1956 tranType
= TLB::S1E1Tran
;
1957 mode
= BaseTLB::Write
;
1959 case MISCREG_AT_S1E0R_Xt
:
1960 flags
= TLB::MustBeOne
| TLB::UserMode
;
1961 tranType
= TLB::S1E0Tran
;
1962 mode
= BaseTLB::Read
;
1964 case MISCREG_AT_S1E0W_Xt
:
1965 flags
= TLB::MustBeOne
| TLB::UserMode
;
1966 tranType
= TLB::S1E0Tran
;
1967 mode
= BaseTLB::Write
;
1969 case MISCREG_AT_S1E2R_Xt
:
1970 flags
= TLB::MustBeOne
;
1971 tranType
= TLB::S1E2Tran
;
1972 mode
= BaseTLB::Read
;
1974 case MISCREG_AT_S1E2W_Xt
:
1975 flags
= TLB::MustBeOne
;
1976 tranType
= TLB::S1E2Tran
;
1977 mode
= BaseTLB::Write
;
1979 case MISCREG_AT_S12E0R_Xt
:
1980 flags
= TLB::MustBeOne
| TLB::UserMode
;
1981 tranType
= TLB::S12E0Tran
;
1982 mode
= BaseTLB::Read
;
1984 case MISCREG_AT_S12E0W_Xt
:
1985 flags
= TLB::MustBeOne
| TLB::UserMode
;
1986 tranType
= TLB::S12E0Tran
;
1987 mode
= BaseTLB::Write
;
1989 case MISCREG_AT_S12E1R_Xt
:
1990 flags
= TLB::MustBeOne
;
1991 tranType
= TLB::S12E1Tran
;
1992 mode
= BaseTLB::Read
;
1994 case MISCREG_AT_S12E1W_Xt
:
1995 flags
= TLB::MustBeOne
;
1996 tranType
= TLB::S12E1Tran
;
1997 mode
= BaseTLB::Write
;
1999 case MISCREG_AT_S1E3R_Xt
:
2000 flags
= TLB::MustBeOne
;
2001 tranType
= TLB::S1E3Tran
;
2002 mode
= BaseTLB::Read
;
2004 case MISCREG_AT_S1E3W_Xt
:
2005 flags
= TLB::MustBeOne
;
2006 tranType
= TLB::S1E3Tran
;
2007 mode
= BaseTLB::Write
;
2010 // If we're in timing mode then doing the translation in
2011 // functional mode then we're slightly distorting performance
2012 // results obtained from simulations. The translation should be
2013 // done in the same mode the core is running in. NOTE: This
2014 // can't be an atomic translation because that causes problems
2015 // with unexpected atomic snoop requests.
2016 warn("Translating via %s in functional mode! Fix Me!\n",
2017 miscRegName
[misc_reg
]);
2019 req
->setVirt(val
, 0, flags
, Request::funcMasterId
,
2020 tc
->pcState().pc());
2021 req
->setContext(tc
->contextId());
2022 fault
= getDTBPtr(tc
)->translateFunctional(req
, tc
, mode
,
2026 if (fault
== NoFault
) {
2027 Addr paddr
= req
->getPaddr();
2028 uint64_t attr
= getDTBPtr(tc
)->getAttr();
2029 uint64_t attr1
= attr
>> 56;
2030 if (!attr1
|| attr1
==0x44) {
2032 attr
&= ~ uint64_t(0x80);
2034 newVal
= (paddr
& mask(47, 12)) | attr
;
2036 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
2039 ArmFault
*armFault
= static_cast<ArmFault
*>(fault
.get());
2040 armFault
->update(tc
);
2041 // Set fault bit and FSR
2042 FSR fsr
= armFault
->getFsr(tc
);
2044 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
2045 if (cpsr
.width
) { // AArch32
2046 newVal
= ((fsr
>> 9) & 1) << 11;
2047 // rearrange fault status
2048 newVal
|= ((fsr
>> 0) & 0x3f) << 1;
2049 newVal
|= 0x1; // F bit
2050 newVal
|= ((armFault
->iss() >> 7) & 0x1) << 8;
2051 newVal
|= armFault
->isStage2() ? 0x200 : 0;
2053 newVal
= 1; // F bit
2054 newVal
|= fsr
<< 1; // FST
2055 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
2056 newVal
|= armFault
->isStage2() ? 1 << 8 : 0; // PTW
2057 newVal
|= armFault
->isStage2() ? 1 << 9 : 0; // S
2058 newVal
|= 1 << 11; // RES1
2061 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
2064 setMiscRegNoEffect(MISCREG_PAR_EL1
, newVal
);
2067 case MISCREG_SPSR_EL3
:
2068 case MISCREG_SPSR_EL2
:
2069 case MISCREG_SPSR_EL1
:
2071 RegVal spsr_mask
= havePAN
?
2072 ~(0x5 << 21) : ~(0x7 << 21);
2074 newVal
= val
& spsr_mask
;
2077 case MISCREG_L2CTLR
:
2078 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
2079 miscRegName
[misc_reg
], uint32_t(val
));
2082 // Generic Timer registers
2083 case MISCREG_CNTFRQ
... MISCREG_CNTVOFF
:
2084 case MISCREG_CNTFRQ_EL0
... MISCREG_CNTVOFF_EL2
:
2085 getGenericTimer(tc
).setMiscReg(misc_reg
, newVal
);
2087 case MISCREG_ICC_AP0R0
... MISCREG_ICH_LRC15
:
2088 case MISCREG_ICC_PMR_EL1
... MISCREG_ICC_IGRPEN1_EL3
:
2089 case MISCREG_ICH_AP0R0_EL2
... MISCREG_ICH_LR15_EL2
:
2090 getGICv3CPUInterface(tc
).setMiscReg(misc_reg
, newVal
);
2092 case MISCREG_ZCR_EL3
:
2093 case MISCREG_ZCR_EL2
:
2094 case MISCREG_ZCR_EL1
:
2095 tc
->getDecoderPtr()->setSveLen(
2096 (getCurSveVecLenInBits(tc
) >> 7) - 1);
2100 setMiscRegNoEffect(misc_reg
, newVal
);
2104 ISA::getGenericTimer(ThreadContext
*tc
)
2106 // We only need to create an ISA interface the first time we try
2107 // to access the timer.
2109 return *timer
.get();
2112 GenericTimer
*generic_timer(system
->getGenericTimer());
2113 if (!generic_timer
) {
2114 panic("Trying to get a generic timer from a system that hasn't "
2115 "been configured to use a generic timer.\n");
2118 timer
.reset(new GenericTimerISA(*generic_timer
, tc
->contextId()));
2119 timer
->setThreadContext(tc
);
2121 return *timer
.get();
2125 ISA::getGICv3CPUInterface(ThreadContext
*tc
)
2127 panic_if(!gicv3CpuInterface
, "GICV3 cpu interface is not registered!");
2128 return *gicv3CpuInterface
.get();
2132 ISA::getCurSveVecLenInBits(ThreadContext
*tc
) const
2139 "A ThreadContext is needed to determine the SVE vector length "
2140 "in full-system mode");
2142 CPSR cpsr
= miscRegs
[MISCREG_CPSR
];
2143 ExceptionLevel el
= (ExceptionLevel
) (uint8_t) cpsr
.el
;
2147 if (el
== EL1
|| (el
== EL0
&& !ELIsInHost(tc
, el
))) {
2148 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL1
]).len
;
2151 if (el
== EL2
|| (el
== EL0
&& ELIsInHost(tc
, el
))) {
2152 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL2
]).len
;
2153 } else if (haveVirtualization
&& !inSecureState(tc
) &&
2154 (el
== EL0
|| el
== EL1
)) {
2157 static_cast<unsigned>(
2158 static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL2
]).len
));
2162 len
= static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL3
]).len
;
2163 } else if (haveSecurity
) {
2166 static_cast<unsigned>(
2167 static_cast<ZCR
>(miscRegs
[MISCREG_ZCR_EL3
]).len
));
2170 len
= std::min(len
, sveVL
- 1);
2172 return (len
+ 1) * 128;
2176 ISA::zeroSveVecRegUpperPart(VecRegContainer
&vc
, unsigned eCount
)
2178 auto vv
= vc
.as
<uint64_t>();
2179 for (int i
= 2; i
< eCount
; ++i
) {
2184 ISA::MiscRegLUTEntryInitializer::chain
2185 ISA::MiscRegLUTEntryInitializer::highest(ArmSystem
*const sys
) const
2187 switch (FullSystem
? sys
->highestEL() : EL1
) {
2189 case EL1
: priv(); break;
2190 case EL2
: hyp(); break;
2191 case EL3
: mon(); break;
2196 } // namespace ArmISA
2199 ArmISAParams::create()
2201 return new ArmISA::ISA(this);